DE19983138T1 - Verfahren und Vorrichtung zum Verändern einer Taktfrequenz auf einer Phase-zu-Phase-Basis - Google Patents

Verfahren und Vorrichtung zum Verändern einer Taktfrequenz auf einer Phase-zu-Phase-Basis

Info

Publication number
DE19983138T1
DE19983138T1 DE19983138T DE19983138T DE19983138T1 DE 19983138 T1 DE19983138 T1 DE 19983138T1 DE 19983138 T DE19983138 T DE 19983138T DE 19983138 T DE19983138 T DE 19983138T DE 19983138 T1 DE19983138 T1 DE 19983138T1
Authority
DE
Germany
Prior art keywords
phase
changing
clock frequency
basis
phase basis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19983138T
Other languages
English (en)
Other versions
DE19983138B4 (de
Inventor
Jason C Stinson
Edwin R Lilya
Mathew B Nazareth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE19983138T1 publication Critical patent/DE19983138T1/de
Application granted granted Critical
Publication of DE19983138B4 publication Critical patent/DE19983138B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
DE19983138T 1998-04-30 1999-04-23 Verfahren und Vorrichtung zum Verändern einer Taktfrequenz auf einer Phase-zu-Phase-Basis Expired - Fee Related DE19983138B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/071,375 US6127858A (en) 1998-04-30 1998-04-30 Method and apparatus for varying a clock frequency on a phase by phase basis
US09/071,375 1998-04-30
PCT/US1999/008888 WO1999056393A1 (en) 1998-04-30 1999-04-23 Method and apparatus for varying a clock frequency on a phase by phase basis

Publications (2)

Publication Number Publication Date
DE19983138T1 true DE19983138T1 (de) 2001-03-29
DE19983138B4 DE19983138B4 (de) 2005-12-22

Family

ID=22100907

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19983138T Expired - Fee Related DE19983138B4 (de) 1998-04-30 1999-04-23 Verfahren und Vorrichtung zum Verändern einer Taktfrequenz auf einer Phase-zu-Phase-Basis

Country Status (6)

Country Link
US (1) US6127858A (de)
AU (1) AU3758299A (de)
DE (1) DE19983138B4 (de)
GB (1) GB2353156B (de)
HK (1) HK1030841A1 (de)
WO (1) WO1999056393A1 (de)

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* Cited by examiner, † Cited by third party
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KR100277903B1 (ko) * 1998-10-19 2001-01-15 김영환 가변 클럭 오퍼레이션을 갖는 마이크로 프로세서
WO2001003342A1 (de) * 1999-06-30 2001-01-11 Infineon Technologies Ag Schaltungsanordnung zur takterzeugung in einem kommunikationssystem
JP2001255958A (ja) * 2000-03-10 2001-09-21 Konica Corp クロック発生装置、基板および画像形成装置ならびにクロック発生方法
US20010032323A1 (en) * 2000-04-06 2001-10-18 Konica Corporation Clock generating device
US6774766B1 (en) * 2000-07-21 2004-08-10 E-Tag Systems, Inc. Method for efficiently querying and identifying multiple items on a communication channel
US6671848B1 (en) 2001-03-20 2003-12-30 Advanced Micro Devices, Inc. Test circuit for exposing higher order speed paths
US6653879B2 (en) * 2001-05-25 2003-11-25 Infineon Technologies Ag Method and system for managing a pulse width of a signal pulse
US6892157B2 (en) * 2001-06-28 2005-05-10 Intel Corporation On-die automatic selection of manipulated clock pulse
US7333527B2 (en) * 2001-11-27 2008-02-19 Sun Microsystems, Inc. EMI reduction using tunable delay lines
US7081777B2 (en) * 2002-05-28 2006-07-25 Realtek Semiconductor Corp. Multiple-phase switching circuit
US20040085082A1 (en) * 2002-10-30 2004-05-06 Townley Kent Richard High -frequency scan testability with low-speed testers
US20040193975A1 (en) * 2003-03-26 2004-09-30 Tarango Tony M. Method and an apparatus for transmit phase select
DE10330593B4 (de) * 2003-07-07 2010-11-04 Qimonda Ag Integrierter Taktversorgungsbaustein für ein Speichermodul, Speichermodul, welches den integrierten Taktversorgungsbaustein umfasst, sowie Verfahren zum Betreiben des Speichermoduls unter Testbedingungen
US7199611B2 (en) 2003-08-22 2007-04-03 Hewlett-Packard Development Company, L.P. System to temporarily modify an output waveform
US6943586B2 (en) * 2003-08-22 2005-09-13 Hewlett-Packard Development Company, L.P. Method and system to temporarily modify an output waveform
US6956420B2 (en) * 2003-09-30 2005-10-18 Intel Corporation Duty cycle compensation in clock circuit
US7290188B1 (en) * 2004-08-31 2007-10-30 Advanced Micro Devices, Inc. Method and apparatus for capturing the internal state of a processor for second and higher order speepaths
JPWO2008032701A1 (ja) * 2006-09-13 2010-01-28 日本電気株式会社 クロック調整回路と半導体集積回路装置
US8412974B2 (en) * 2009-11-13 2013-04-02 International Business Machines Corporation Global synchronization of parallel processors using clock pulse width modulation
WO2012035651A1 (ja) * 2010-09-17 2012-03-22 富士通株式会社 回路装置、周波数変更回路、回路装置の試験方法、及び周波数変更回路の制御方法
CN108604316B (zh) 2015-11-27 2022-11-15 光子公司 用于与自旋存储的量子信息交互的系统、装置及方法
US10698439B1 (en) * 2019-01-31 2020-06-30 Qualcomm Incorporated Efficient clock forwarding scheme

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JPS60229521A (ja) * 1984-04-27 1985-11-14 Sony Tektronix Corp デジタル信号遅延回路
US4777385A (en) * 1987-02-09 1988-10-11 Rca Licensing Corporation Signal transient improvement circuit
US4980585A (en) * 1989-12-01 1990-12-25 Intel Corporation Method and apparatus for synthesizing digital waveforms
US5093841A (en) * 1990-01-30 1992-03-03 Nynex Corporation Clock acquisition in a spread spectrum system
US5045715A (en) * 1990-03-19 1991-09-03 Apple Computer, Inc. Circuit for generating stretched clock phases on a cycle by cycle basis
JPH04268811A (ja) * 1991-02-22 1992-09-24 Yokogawa Hewlett Packard Ltd タイミングジェネレータ
US5376848A (en) * 1993-04-05 1994-12-27 Motorola, Inc. Delay matching circuit
FR2710800B1 (fr) * 1993-09-27 1995-12-15 Sgs Thomson Microelectronics Ligne à retard numérique.
US5463337A (en) * 1993-11-30 1995-10-31 At&T Corp. Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein
US5796673A (en) * 1994-10-06 1998-08-18 Mosaid Technologies Incorporated Delay locked loop implementation in a synchronous dynamic random access memory
US5692165A (en) * 1995-09-12 1997-11-25 Micron Electronics Inc. Memory controller with low skew control signal
US5661731A (en) * 1996-06-27 1997-08-26 Intel Corporation Method for shrinking a clock cycle when testing high speed microprocessor designs
US5818890A (en) * 1996-09-24 1998-10-06 Motorola, Inc. Method for synchronizing signals and structures therefor

Also Published As

Publication number Publication date
GB0026501D0 (en) 2000-12-13
WO1999056393A1 (en) 1999-11-04
GB2353156B (en) 2003-04-16
GB2353156A (en) 2001-02-14
US6127858A (en) 2000-10-03
AU3758299A (en) 1999-11-16
HK1030841A1 (en) 2001-05-18
DE19983138B4 (de) 2005-12-22

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8607 Notification of search results after publication
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee