DE1954966C3 - Elektrische Speichermatrix in Kompaktbauweise - Google Patents

Elektrische Speichermatrix in Kompaktbauweise

Info

Publication number
DE1954966C3
DE1954966C3 DE1954966A DE1954966A DE1954966C3 DE 1954966 C3 DE1954966 C3 DE 1954966C3 DE 1954966 A DE1954966 A DE 1954966A DE 1954966 A DE1954966 A DE 1954966A DE 1954966 C3 DE1954966 C3 DE 1954966C3
Authority
DE
Germany
Prior art keywords
conductors
state
switch
monostable
elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE1954966A
Other languages
German (de)
English (en)
Other versions
DE1954966B2 (de
DE1954966A1 (de
Inventor
Ronald George Birmingham Mich. Neale (V.St.A.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Energy Conversion Devices Inc
Original Assignee
Energy Conversion Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Energy Conversion Devices Inc filed Critical Energy Conversion Devices Inc
Publication of DE1954966A1 publication Critical patent/DE1954966A1/de
Publication of DE1954966B2 publication Critical patent/DE1954966B2/de
Application granted granted Critical
Publication of DE1954966C3 publication Critical patent/DE1954966C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Landscapes

  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Thin Film Transistor (AREA)
DE1954966A 1968-11-04 1969-10-31 Elektrische Speichermatrix in Kompaktbauweise Expired DE1954966C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US77301368A 1968-11-04 1968-11-04

Publications (3)

Publication Number Publication Date
DE1954966A1 DE1954966A1 (de) 1970-05-06
DE1954966B2 DE1954966B2 (de) 1975-01-09
DE1954966C3 true DE1954966C3 (de) 1975-09-04

Family

ID=25096913

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1954966A Expired DE1954966C3 (de) 1968-11-04 1969-10-31 Elektrische Speichermatrix in Kompaktbauweise

Country Status (8)

Country Link
US (1) US3629863A (enExample)
JP (1) JPS5545988B1 (enExample)
BE (1) BE741169A (enExample)
CH (1) CH513570A (enExample)
DE (1) DE1954966C3 (enExample)
FR (1) FR2032272A1 (enExample)
GB (1) GB1295453A (enExample)
NL (1) NL6916593A (enExample)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1308711A (en) * 1969-03-13 1973-03-07 Energy Conversion Devices Inc Combination switch units and integrated circuits
US3739356A (en) * 1971-06-21 1973-06-12 Ibm Heterojunction information storage unit
US3875566A (en) * 1973-10-29 1975-04-01 Energy Conversion Devices Inc Resetting filament-forming memory semiconductor devices with multiple reset pulses
DE2425467B1 (de) * 1974-05-27 1975-11-06 Heimann Gmbh Festwertspeichermatrix
US3979586A (en) * 1974-12-09 1976-09-07 Xerox Corporation Non-crystalline device memory array
US4181913A (en) * 1977-05-31 1980-01-01 Xerox Corporation Resistive electrode amorphous semiconductor negative resistance device
US4162538A (en) * 1977-07-27 1979-07-24 Xerox Corporation Thin film programmable read-only memory having transposable input and output lines
US4203123A (en) * 1977-12-12 1980-05-13 Burroughs Corporation Thin film memory device employing amorphous semiconductor materials
US4677742A (en) * 1983-01-18 1987-07-07 Energy Conversion Devices, Inc. Electronic matrix arrays and method for making the same
AU562641B2 (en) 1983-01-18 1987-06-18 Energy Conversion Devices Inc. Electronic matrix array
US4795657A (en) * 1984-04-13 1989-01-03 Energy Conversion Devices, Inc. Method of fabricating a programmable array
JPH0691223B2 (ja) * 1987-07-06 1994-11-14 三菱電機株式会社 Ｒｏｍ装置及びその形成方法
US4931763A (en) * 1988-02-16 1990-06-05 California Institute Of Technology Memory switches based on metal oxide thin films
US5989943A (en) * 1989-09-07 1999-11-23 Quicklogic Corporation Method for fabrication of programmable interconnect structure
US5502315A (en) * 1989-09-07 1996-03-26 Quicklogic Corporation Electrically programmable interconnect structure having a PECVD amorphous silicon element
US5294846A (en) * 1992-08-17 1994-03-15 Paivinen John O Method and apparatus for programming anti-fuse devices
US5424655A (en) * 1994-05-20 1995-06-13 Quicklogic Corporation Programmable application specific integrated circuit employing antifuses and methods therefor
US5900767A (en) * 1995-06-24 1999-05-04 U.S. Philips Corporation Electronic devices comprising an array
US5949088A (en) * 1996-10-25 1999-09-07 Micron Technology, Inc. Intermediate SRAM array product and method of conditioning memory elements thereof
US6888750B2 (en) 2000-04-28 2005-05-03 Matrix Semiconductor, Inc. Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
EP2323164B1 (en) 2000-08-14 2015-11-25 SanDisk 3D LLC Multilevel memory array and method for making same
US6580124B1 (en) 2000-08-14 2003-06-17 Matrix Semiconductor Inc. Multigate semiconductor device with vertical channel current and method of fabrication
US6897514B2 (en) 2001-03-28 2005-05-24 Matrix Semiconductor, Inc. Two mask floating gate EEPROM and method of making
US6593624B2 (en) 2001-09-25 2003-07-15 Matrix Semiconductor, Inc. Thin film transistors with vertically offset drain regions
US6841813B2 (en) 2001-08-13 2005-01-11 Matrix Semiconductor, Inc. TFT mask ROM and method for making same
US6590797B1 (en) 2002-01-09 2003-07-08 Tower Semiconductor Ltd. Multi-bit programmable memory cell having multiple anti-fuse elements
US6853049B2 (en) 2002-03-13 2005-02-08 Matrix Semiconductor, Inc. Silicide-silicon oxide-semiconductor antifuse device and method of making
US6737675B2 (en) 2002-06-27 2004-05-18 Matrix Semiconductor, Inc. High density 3D rail stack arrays
US7589343B2 (en) * 2002-12-13 2009-09-15 Intel Corporation Memory and access device and method therefor
US6795338B2 (en) * 2002-12-13 2004-09-21 Intel Corporation Memory having access devices using phase change material such as chalcogenide
US7391664B2 (en) * 2006-04-27 2008-06-24 Ovonyx, Inc. Page mode access for non-volatile memory arrays
US7684225B2 (en) * 2006-10-13 2010-03-23 Ovonyx, Inc. Sequential and video access for non-volatile memory arrays
US8377741B2 (en) * 2008-12-30 2013-02-19 Stmicroelectronics S.R.L. Self-heating phase change memory cell architecture
US9627395B2 (en) 2015-02-11 2017-04-18 Sandisk Technologies Llc Enhanced channel mobility three-dimensional memory structure and method of making thereof
US9478495B1 (en) 2015-10-26 2016-10-25 Sandisk Technologies Llc Three dimensional memory device containing aluminum source contact via structure and method of making thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3091754A (en) * 1958-05-08 1963-05-28 Nazare Edgar Henri Electric memory device
US3245051A (en) * 1960-11-16 1966-04-05 John H Robb Information storage matrices

Also Published As

Publication number Publication date
DE1954966B2 (de) 1975-01-09
US3629863A (en) 1971-12-21
DE1954966A1 (de) 1970-05-06
GB1295453A (enExample) 1972-11-08
CH513570A (de) 1971-09-30
NL6916593A (enExample) 1970-05-08
BE741169A (enExample) 1970-04-16
JPS5545988B1 (enExample) 1980-11-20
FR2032272A1 (enExample) 1970-11-27

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Legal Events

Date Code Title Description
SH Request for examination between 03.10.1968 and 22.04.1971
C3 Grant after two publication steps (3rd publication)
E77 Valid patent as to the heymanns-index 1977