DE112011105972T5 - III-V layers for N-type and P-type MOS source / drain contacts - Google Patents

Abstract

Technologies for the formation of transistor components are disclosed which have a reduced parasitic contact resistance compared to conventional components. In some exemplary embodiments, these technologies may be used to implement the contacts of MOS transistors of a CMOS device, with an intermediate III-V semiconductor material layer between the p-type and n-type source / drain regions and their associated metal contacts is provided in order to significantly reduce the contact resistance. The intermediate III-V semiconductor material layer can have a small band gap (for example less than 0.5 eV) and / or be doped in some other way in order to provide the required conductivity. These technologies can be applied to a wide variety of transistor architectures (e.g., planar transistors, finned transistors, and nanowire transistors), including strained and unstressed channel structures.

Description

BACKGROUND

The increased performance of circuit components including transistors, diodes, resistors, capacitors, and other passive and active electronic components formed on a semiconductor substrate is typically a significant factor in the design, manufacture, and operation of such devices. For example, in the development and fabrication or formation of metal oxide semiconductor (MOS) transistor semiconductor devices, such as those used in a complementary metal-oxide semiconductor (CMOS), it is often desirable to minimize the parasitic resistance associated with the contacts, which may also be external Resistance "Rext" is known. A reduced Rext allows a higher current with the same transistor geometry.

BRIEF DESCRIPTION OF THE FIGURES

The 1A FIG. 12 shows a method of forming a low contact resistance transistor structure according to an embodiment of the present invention. FIG.

The 1B FIG. 12 shows a method of forming a low contact resistance transistor structure according to another embodiment of the present invention. FIG.

The 2A to 2F illustrate structures that are formed when the method according to 1A is executed, according to an embodiment of the present invention.

The 3A to 3C illustrate alternative structures that are formed when the method according to 1B is carried out according to another embodiment of the present invention.

The 4A Figures 1-E are each a perspective view of a non-planar transistor architecture constructed in accordance with an embodiment of the present invention.

The 5 FIG. 12 illustrates a computer system implemented with one or more transistor structures in accordance with an exemplary embodiment of the present invention.

As can be appreciated, the figures are not necessarily drawn to scale, or intended to limit the claimed invention to the particular arrangements shown. For example, although some figures generally show straight lines, right angles, and smooth surfaces, in actual implementation, a transistor structure may have less perfect, straight lines and right angles, with some elements having a surface topology or otherwise unsmooth surface, as appropriate given limitations of the processing equipment and technologies used. In short, the figures are merely illustrative of exemplary structures.

Technologies for the formation of transistor devices are disclosed which have a reduced parasitic contact resistance compared to conventional devices. These technologies may, for example, be implemented at the point in the semiconductor processing operation where conventional contact processing would provide silicide directly on a silicon source / drain region using a standard contact stack, such as a sequence of metals on silicon (Si), silicon Germanium (SiGe) or germanium (Ge) source / drain regions. In some example embodiments, these technologies may be used to form the contacts of MOS transistors of a CMOS device, with an inter III-V semiconductor material layer between the p-type and n-type source / drain regions and their respective contact metals are provided to substantially reduce the contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (for example, less than 0.5 eV) and / or be doped to have the desired conductivity. These technologies can be applied to a variety of transistor architectures (eg, planar, ridge, and nanowire transistors), including strained and unstressed channel structures.

General overview

As described above, in the transistor, increased control current can be achieved by reducing the component resistance. The contact resistance is a component of the total resistance of a component. A typical transistor contact stack includes, for example, a silicon or SiGe source / drain layer, a silicide germanide layer, a titanium nitride adhesion layer, and a tungsten contact / plug. Silicides and germanides of metals such as nickel, platinum, titanium, cobalt, etc., can be formed on the source / drain regions prior to deposition of the tungsten plug. In such arrangements, the contact resistance is comparatively high and ultimately limited by the silicon or SiGe valence band alignment to the pinning level in the metal. In practice, typical approaches to this include Forming contacts basically alloys with band gaps between 0.5-1.5 eV or more. While some of these approaches may be suitable for the n-type transistor structures, they are unsuitable for p-type transistor structures.

Accordingly, according to one embodiment of the present invention, an intermediate III-V semiconductor material layer is deposited after the source / drain formation, but before the metal contact deposition. It should be noted that the same intermediate III-V semiconductor material layer can be deposited over both the p-type and n-type source / drain regions. In some embodiments, the III-V material layer is selected to have a narrow band gap, such as indium antimonide (InSb) or other related compounds with bandgaps below 0.5 eV, including various combinations of aluminum (Al), gallium (Ga), Indium (In), phosphorus (P), arsenic (As) and / or antimony (Sb). Such narrow bandgap III-V material layers may be used, for example, to provide MOS transistor source / drain regions, such as p-type and n-type Si or SiGe alloys, and Ge source / drain Areas to provide good contact properties. In other embodiments, any bandgap III-V materials may be deposited and doped, thereby raising their conductivity to a level comparable to that of III-V narrow bandgap materials, or otherwise acceptable for the given application conductivity levels.

Note that in some embodiments, the III-V semiconductor material may remain undoped, especially for III-V materials with bandgaps less than 0.5 eV, since thermal carrier formation in low-band-gap materials is sufficient even at room temperature, to achieve a high conductivity. In other embodiments where doping is used, such as those using arbitrary bandgap III-V materials, doping can be performed in a variety of ways, including with the aid of in-situ and / or or ex-situ doping technologies. Some of these embodiments involve the use of III-V materials that have sufficiently high doping levels of a column IV dopant such as carbon, silicon, germanium, or zinc. At very high doping levels (for example, with a substitution concentration greater than 1E18 atoms / cm ^3), these amphoteric dopants add carriers in both the valence and the conduction band added, making the carrier concentration is increased for both types of charge carriers. In these cases, the doping is carried out in-situ. In other embodiments, an intrinsic III-V material layer is deposited, followed by an ex-situ doping process, some of ion implantation or diffusion doping to provide the required conductivity (eg, conductivity with values of, for example, 100 to 500 S / cm ³ ). , In some exemplary cases, the III-V material layer may be doped such that the p-type regions have a first doping scheme and the n-type regions have a second doping scheme. For example, the n-type source / drain regions may be doped with, for example, silicon, germanium, tellurium, and the p-type source / drain regions with zinc or cadmium. As can be seen in the light of the disclosure, such embodiments with multiple doping schemes basically include additional structuring steps.

It is further noted that the III-V material layer can be used to enhance contact resistance in any number of transistor structures as well as other configurations, including planar structures, raised source / drain structures, nonplanar structures (US Pat. for example in nanowire transistors and ripple transistors such as double-gate and triple-gate transistor structures) as well as in stressed and unstressed channel structures. Moreover, the transistor structures may include source and drain tip regions configured to, for example, reduce the overall resistance of the transistor while enhancing the short channel effect (SCE), as sometimes envisioned. A variety of patterned elements may be used in conjunction with a previously described III-V semiconductor material layer.

The transistor structure may include p-type source / drain regions, n-type source / drain regions, or both n-type and p-type source / drain regions. In some example embodiments, the transistor structure comprises doped-implanted source / drain regions or epitaxial (or polycrystalline) exchange source / drain regions of silicon, SiGe alloys, or nominally pure germanium layers (eg, those with less than 10% silicon) in a MOS. Structure. In any such embodiment, according to one embodiment of the present invention, a layer or cap of III-V semiconductor material may be formed directly over the source / drain regions. The III-V material layer can also be formed directly over other parts of the transistor structure. For example, over PolyGates and / or ground contact areas, or over other such areas where low contact resistance is required, if desired.

Studies (for example, scanning electron microscopy and / or compositional analyzes) have shown that a structural composition formed according to one embodiment of the present invention will have an additional III-V semiconductor material layer comprising, for example, Al, Ga, In, P, As and / or compositions. or Sb (besides any dopants which raise the conductivity to an acceptable level, if necessary) and form a contact resistance that is less than the contact resistance of devices formed with conventional silicide and germanite contact processes. It should be appreciated that any number of semiconductor devices or circuits where there is a need for high performance contacts can benefit from the low resistance contact technology described herein.

Therefore, the transistor structures formed in accordance with embodiments of the present invention offer an improvement over conventional structures in terms of lower contact resistance. Various process changes may arise in the light of the disclosure. For example, the III-V semiconductor material may be deposited on the source / drain regions before depositing a dielectric layer over the source / drain layer. Alternatively, the III-V semiconductor material may be deposited on the source / drain regions after a dielectric layer has been deposited over the source / drain layer regions and after contact trenches have been etched into the source / drain layer.

Methodology and structure

The 1A FIG. 12 shows a method of forming a low contact resistance transistor structure according to an embodiment of the present invention. FIG. The 2A to 2F illustrate example structures that are formed when the method is performed according to some embodiments.

The exemplary method includes forming 102 one or more gate stacks on a semiconductor substrate on which a MOS device can be formed. The MOS device may include NMOS or PMOS transistors, or both NMOS and PMOS transistors (for example, CMOS devices). The 2A shows by way of example a resulting structure, which in this case comprises both NMOS and PMOS transistors mounted on the same substrate 300 and formed by a shallow trench isolation (STI) are separated from each other. Other suitable types of isolation between p-type and n-type regions may also be used. As can be seen, each gate stack is formed over a channel region of a transistor and includes a gate dielectric layer 302 , a gate electrode 304 , an optional hard mask 306 , as well as spacers 310 are formed adjacent to the gate stack.

The gate dielectric 302 For example, it may be any suitable oxide, such as silicon dioxide (SiO ₂ ), or a high-k gate dielectric material. Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium-silica, lanthana, lanthanum-alumina, zirconia, zirconia-silica, tantala, titania, barium-strontium-titania, barium-titania, strontium-titania, yttria, alumina, Lead scandium titanium oxide and lead zinc niobate. In some embodiments, a healing process may be applied to the gate dielectric layer 302 to improve their quality when using a high k material. In some particular exemplary embodiments, the gate dielectric layer 302 having a high k-value, a thickness between 5 Å to about 100 Å (for example, 10 Å). In other embodiments, the gate dielectric layer 302 the thickness of a monolayer of oxide material. Basically, the thickness of the gate dielectric should be 302 be sufficient to the gate electrode 304 electrically isolate from the source and drain contacts. In some embodiments, additional processing steps may be applied to the gate dielectric layer 302 high k value, such as a healing process, to improve the quality of the high k material.

The gate electrode material 304 For example, polysilicon, silicon nitride, silicon carbide, or a metal layer (eg, tungsten, titanium nitride, tantalum, tantalum nitride) may be used, although other suitable gate electrode materials may also be used. The gate electrode material 304 , which may be a sacrificial material that may later be removed for an exchange metal gate (RMG) process, in some embodiments has a thickness between 10 Å and 500 Å (e.g., 100 Å).

The optional gate hard mask layer 306 can be used to provide certain advantages or applications during processing, such as the gate electrode 304 to protect against subsequent etching and / or ion implantation processes. The hard mask layer 306 can be formed using typical hard mask materials, such as silicon dioxide, silicon nitride, and / or other conventional nonconductive materials.

The gate stack may be as usual, or using a suitable special technology (for example, with a conventional patterning process, to etch away portions of the gate electrode and the gate dielectric layer to form the gate stack, as shown in FIG 2A is shown) are formed. Both the gate dielectric material 302 as well as the gate electrode material 304 For example, it can be formed using conventional deposition processes such as chemical vapor deposition (CVD), atomic layer shutdown (ALD), spin-on deposition (SOD), or physical vapor deposition (PVD). Alternative deposition technologies may also be used, for example, the materials of the gate dielectric 302 and the gate electrode are thermally grown. As will be appreciated in the light of the disclosure, any number of other suitable materials, geometries, and formation processes may be used to practice an embodiment of the present invention, with the aim of providing a transistor device or low contact resistance structure, as described herein is.

The spacers 310 For example, they can be formed using conventional materials such as silicon oxide, silicon nitrite or other suitable spacer materials. The width of the spacers 310 can basically be selected based on the design requirements of the transistor to be formed. However, according to some embodiments, the width of the spacers is subject 310 not the design constraints on the formation of the source and drain epi peaks, provided that there is a sufficiently high Bohr doped germanium content in the source / drain tip region.

Any number of suitable substrates can be used to form the substrate 300 implement, including solid substrates, semiconductor non-conductor substrates (XOI, where X is a semiconductor material such as silicon, germanium or germanium-enriched silicon) and multilayer structures, including those substrates on which ribs or nono wires are formed before a subsequent gate patterning process. In some particular examples, the substrate is 300 a solid germanium, silicon or SiGe substrate or a germanium, silicon or SiGe on oxide substrate. Although a few exemplary materials are described that make up the substrate 300 may be formed, any material which may constitute a basis for a low contact resistance semiconductor device is intended to fall within the scope of the claimed invention.

Next with respect to the 1A sets the method after forming one or more gate stacks with setting 104 the source / drain regions of the transistor structure away. The source / drain regions can be implemented with any number of suitable methods and configurations. For example, source / drain regions may be implanted, etched and epi-filled, grown, be silicon, germanium or SiGe alloys, p-type and / or n-type, and may be planar ribbed or have a wire-shaped diffusion region. For example, in some such examples, the source and drain regions may be formed using either an implantation / diffusion process or an etching / deposition process. In the previous process, dopants such as aluminum, antimony, phosphorus or arsenic may be incorporated into the substrate 300 ion-implanted to form the source and drain regions. The ion implantation process is typically followed by an annealing process which can activate and also cause the dopants to penetrate the substrate 300 diffuse. In the latter process, the substrate 300 first etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be performed to fill the wells with a silicon alloy such as silicon germanium or silicon carbide, thereby forming the source and drain regions. In some embodiments, the epitaxially deposited silicon alloy may be doped in-situ or ex-situ with dopants such as Bohr, arsenic or phosphorus.

In the in the 2A - 2F The embodiment shown was the substrate 300 etched to provide depressions as well as tip areas which define the gate dielectric 302 subvert. The recesses and tip areas were filled to provide the source / drain regions as well as the optional tip regions. In accordance with some particular example embodiments in which the substrate 300 is a bulk silicon substrate or a silicon on non-conductor (SOI) substrate, the source and drain wells are filled adjacent to their respective tip regions with in-situ doped silicon, SiGe, or germanium, thereby reducing the source and drain Be formed areas (next to their corresponding epi-peaks). Any number of source / drain layer configurations may be used. With regard to the materials (for example doped or undoped Si, Ge, SiGe), the dopants (for example Bohr, arsenic or phosphorus) and the geometries (the thickness of the source / drain layer can be between 50 and 500 nm, for example for example, to provide aligned or raised source / drain regions).

As will be appreciated in the light of the disclosure, any number of other transistor elements may be implemented in conjunction with one embodiment of the present invention. For example, the channel may be strained or unstressed, and the source / drain regions may or may not include peak regions formed in the region between the corresponding source / drain region and the channel region. In this sense, it is not of particular relevance to the various embodiments of the present invention whether a transistor structure has strained or relaxed channels, or source / drain tip regions, or no source / drain tip regions, such embodiments are not intended to be confined to any particular structural elements. Rather, this number of transistor structures and types and, in particular, such structures having both n-type and p-type source / drain transistor regions should be subject to the application of a III-V material layer having a band gap and / or a Such layer, which is otherwise doped, will benefit over the source / drain region as previously described. Basically, no doping is necessary at room temperature if the bandgap is small enough (although doping may be used if desired). In a particular example case, InSb serves both p- and n-type source / drain regions without any doping. For larger band gap III-V materials (> 0.5 eV), doping may be used to provide the desired conductivity.

Next with respect to the 1A For example, after the source / drain regions have been set, the process of this exemplary embodiment sets with deposition 106 a non-conductor layer 322 continued. The 2 B shows a dielectric layer 322 , which with the hard mask 306 the gate stack is aligned, but this is not essential. The nonconductor may be formed in various ways. In some embodiments, the dielectric layer becomes 322 formed with the aid of SiO ₂ or other low-k non-conductive materials. In principle, the dielectric constant of the layer material 322 be selected as needed. In some embodiments, the dielectric layer 322 comprise a liner (e.g., silicon nitrite) followed by one or more layers of SiO ₂ , or any combination of nitrite, oxide, oxynitrite, carbide, oxy carbide, or other suitable non-conductor materials. The non-conductor layer 322 which is referred to as an interlayer dielectric (ILD) can be planarized in a conventional manner (for example by means of the planarization process following the deposition, such as by means of chemical mechanical planarization, or CMP). Other exemplary nonconductive materials used for the formation of the layer 322 For example, carbon doped oxide (CDO), organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane or organonosilicate glass can be used. In some example configurations, the dielectric layer 322 Include pores or other imperfections to further lower their dielectric constant.

As will be appreciated in the light of the disclosure and provided in accordance with some embodiments of the present invention using a replacement metal gate process (RMG), the method may further include removing the gate stack (including the gate dielectric layer 302 high k value, the sacrificial gate electrode 304 and the hard mask layer 306 ) using a conventional etching process. In some such cases, only the victims become gods 304 and the hardmask layer 306 away. If the gate dielectric layer 302 is removed, the method may continue with the deposition of a new gate dielectric layer into the trench opening. Any suitable gate dielectric materials, such as those described above, may be used, such as hafnium oxide. The same deposition methods can also be used. For example, the exchange of the gate dielectric layer may be used to overcome any damage that the original gate dielectric layer has suffered during the application of the dry and wet etch processes and / or a low k dielectric material or a high k sacrificial material or to replace any other required dielectric material. In such RMG processes, the method may further comprise depositing the gate electrode layer into the trench and over the gate dielectric layer. Conventional deposition processes can be used to form the replacement gate electrode, such as CVD, ALD and PVD. The gate electrode layer may comprise, for example, a p-type workfunction metal, for example ruthenium, palladium, platinum, cobalt, nickel and conductive metal oxides, for example ruthenium oxide. In some example configurations, two or more metal gate electrode layers may be deposited. For example, a workfunction metal may be deposited in the gate trench, followed by a suitable metallic gate electrode fill metal, such as aluminum or silver. The 2 B' shows an exemplary gate structure, which is through an optional RMG process which gives an exchange gate electrode layer 326 over an exchange gate dielectric layer 324 includes. In yet other embodiments, such RMG processes may be performed later in the process (eg, after step 114 ) so that the replacement gate materials are not further processing according to the steps 108 to 114 get abandoned.

Next will be referring to 1A continues the process after providing the dielectric layer 322 (as well as any tube contact formation RMG process) with the etch 108 to form the source / drain contact trench. Any suitable dry and / or wet etching process can be used for this purpose. The 2C FIG. 12 shows the source / drain contact trench after the etching is completed, according to an exemplary embodiment. FIG.

The process continues with the deposition 110 a III-V semiconductor material layer on the source / drain regions of the transistor structure. The 2D shows the III-V material layer 317 over both the n-type and p-type source / drain regions, according to an example embodiment. Deposition may be non-selective, with any excess III-V deposited subsequently from the surface of the nonconductor 322 (and, if necessary, from the gate stacks). In other embodiments, the deposition may be selectively performed with the III-V material deposition performed only on the source / drain regions (or a subset thereof). For example, in some embodiments, the deposition is 110 selective, in that the process comprises masking the p-type regions or the n-type regions followed by selective deposition to achieve that the deposition occurs exclusively in one or the other of the regions (e.g. Example in which the p-type regions receive a III-V material composition having a first doping scheme, and wherein the n-type regions receive a III-V material composition having a second doping scheme). Alternatively, the deposition 110 by means of a single composition of undoped III-IV material on all source / drain regions, followed by subsequent masking and doping to optimize the contact resistance to the doping type of the underlying source / drain material. Alternatively, the deposition 110 of a single composition of undoped III-IV material on all source / drain regions, with the undoped III-IV material having a band gap of less than 0.5 eV (for example, a bandgap of In _x Ga _1-x As = 0.427 eV, where x equals 0.9). In some cases, with such a small band gap, the band gap is less than 0.4 eV (for example, the band gap of InAs = 0.36 eV). In still other such cases, the bandgap is less than 0.3 eV. In yet other such cases, the bandgap is less than 0.2 eV (for example, the band gap of InSb = 0.17 eV). In still other such cases, the band gap is within a range, for example, between 0.1 eV and 0.4 eV, or between 0.1 eV and 0.25 eV, or between 0.25 eV and 0.5 eV, or between 0.15 eV and 0.35 eV. It should be noted, however, that the III-V materials should not be limited to those having a band gap of less than 0.5 eV. This is because the III-V material can be deposited by, for example, in-situ doping, diffusion doping, or implant doping, so that it is tuned to the doping type of the underlying source / drain material.

In some example embodiments, the III-V material layer becomes 317 epitaxially deposited. The thickness of the III-V material layer 317 may range between, for example, 50 to 250 Å, in accordance with some particular example embodiments, although other embodiments may have other layer thicknesses, as will be apparent to those skilled in the art in light of the disclosure. In some embodiments, a CVD process or other suitable deposition technology may be used 108 or otherwise forming the III-V material layer 317 be used. For example, the deposition 308 by CVD, thermally accelerated CVD (RT-CVD), low pressure CVD (LP-CVD), or ultra high vacuum CVD (UHV-CVD), or gas source molecular beam epitaxy (GSMBE) using III-V material compositions, such as Al compounds , Ga, In, P, As, Sb and / or precursors thereof. In a particular exemplary embodiment, the III-V material layer becomes 317 produced using undoped indium antimonide (InSb). In other embodiments, the III-V material layer becomes 317 using GaAs doped with Ge, prepared to have a Ge-exchange concentration of 1E19 atoms / cm ³ or more to provide, resulting in a resistivity of about 5E-3 ohm-cm (or a corresponding conductivity of about 200 mho / cm) leads. In some such embodiments, a carrier gas may be used, such as hydrogen, nitrogen, or a noble gas (eg, a precursor is diluted with a carrier gas to a concentration of 1-20%). In some example cases, an arsenic precursor material such as arsine or TBA, a gallium precursor material such as TMG and / or an indium precursor material such as TMI may be used. Further, an etching gas such as an hydrogen-based gas such as hydrogen fluoride (HCL), chlorine (CL) or Hydrogen bromide (HBR) are present. The base deposition of the III-V semiconductor material layer 317 is possible over a wide range of process parameters, for example, using a deposition temperature between 300 ° C and 700 ° C (for example, 400-500 ° C), at a process pressure of, for example, 1 Torr to 760 Torr. Both the etching gas and the carrier gas may have a flow rate between 10 and 300 SCCM (typically, however, a flow rate of not more than 100 SCCM is necessary, although some other embodiments may benefit from higher flow rates). In a particular exemplary embodiment, the deposition 110 performed at a flow rate between 100 and 1000 SCCM. For in situ doping of germanium, for example, dilute german or digerman may be used (for example, the german may be diluted at a concentration of 10% in H ₂ , at a flow rate between 10 and 100 SCCM).

One skilled in the art will recognize, in light of the disclosure, that the selectivity with which the III-V material layer 317 is deposited, can be varied as needed. In some cases, the III-V material layer becomes 317 for example, deposited only on the source / drain regions or a portion of the source / drain regions (rather than across the entire structure). Any masking-structuring technology can be further used to define sub-areas on which the layer 317 is selectively deposited. In addition, other embodiments may be different from the coverage of the layer 317 benefit, such as exposed poly gate areas or exposed ground contact areas. As can further be seen from the disclosure, the III-V material layer 317 can be used to realize much lower contact resistance in the source and drain regions (as well as in other areas where low contact resistance is desirable, such as in ground contact regions), as provided in some exemplary embodiments.

The process then begins with the deposition 112 a contact resistance reducing metal and a healing step, whereupon the deposition 114 the source / drain contact plug takes place. It should be noted that in such embodiments no silicide or germanite is present. Rather, any reaction takes place between the III-V material 317 and the metallic contact resistance reducing layer 325 instead of. The 3E shows the contact resistance reduction metals 325 which in some embodiments comprise silver, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum or nickel-aluminum and / or other such resistance-reducing metals or alloys. Other embodiments may further include additional layers, such as adhesive layers between the layer 317 and the layer 325 if desired. The 2F shows the contact plug metal 329 which includes aluminum or tungsten in some embodiments, although any other suitable conductive contact material or conductive contact alloy may be used, such as silver, nickel-platinum or nickel-aluminum or other alloys of nickel and aluminum or titanium, using conventional deposition technologies , For example, transistors may have a source / drain region based on a III-V material layer 317 at the interface between the source / drain regions and the contact resistance reducing metal 325 Resistance values of less than 100 ohm-um, and in some cases even less than 90 ohm-um, in some cases even less than 80 ohm-um and in some cases less than 75 ohm-um or even less ,

The 1B FIG. 12 shows a method of forming a low contact resistance transistor structure according to another embodiment of the present invention. FIG. The 3A to 3C illustrate alternative example structures that are formed. Basically, this method is similar to the method described with respect to 1A and 2A -F has been described, except that the deposition of the III-V material layer 317 on the source / drain regions prior to deposition of the nonconductor 322 is carried out. This is in 1B shown by the germanium material deposition 110 after determining the source / drain region 104 and before the non-conductor separation 106 is relocated. The resulting structure after dielectric separation 106 is in 3A shown. It should be noted that in this exemplary embodiment, the III-V material layer 317 completely covers each of the illustrated source / drain regions, rather than just the portion exposed by the contact trench (as most clearly shown in FIG 2D is shown). The 3B indicates the resulting structure after the contact trenches 108 etched, in 3C the resulting structure after the deposition of the contact resistance reduction metal 325 as well as the metal contact plug 329 in the steps 112 and or 114 is done. It should be recognized that the preceding relevant discussion with respect to similar parts of the exemplary method, with reference to the 1A has been described in the present case accordingly applies.

Non-planar configuration

A non-planar architecture may be implemented using, for example, FinFETs or Nanowire configurations are implemented. A FinFET is a transistor constructed around a thin strip of semiconductor material (this is basically called a fin). The transistor includes the node of a standard field effect transistor (FET), including a gate, a gate dielectric, a source region and a drain region. The conductive channel of the device remains on / within the outer side (s) of the fin below the gate dielectric. In particular, current flows along both sidewalls within the fin (the sides extending at right angles to the substrate surface) as well as along the top of the fin (the side extending parallel to the substrate surface). Since the conductive channel of such configurations is disposed substantially along the three different outer planar portions of the fin, such FinFET design is sometimes referred to as a triple gate FinFET. Other types of FinFET configurations are also known. For example, so-called double-gate FinFETs, in which the conductive channel is basically arranged only along the two side walls of the company (but not along the top of the fin).

A nanowire transistor (sometimes referred to as a gate-all-around FinFET) is very similar, but instead of a fin, it uses a nanowire (for example, a silicon or a SiGe or a Ge nanowire) Gate material basically surrounds the channel area on all sides. For example, depending on the particular design, nanowire transistors have four effective gates.

The 4A - 4E 12 each show a perspective view of an exemplary non-planar architecture formed in accordance with one embodiment of the present invention. In particular, the show 4A Each a perspective view of a FinFET transistor structure, and the 4C -E show exemplary nanowire channel transistor structures. Each of the figures will be discussed below.

As can be seen, the exemplary non-planar configuration shown in FIG 4A is shown performed by means of triple-gate components, each of which is a substrate 600 comprising a semiconductor body or a company 660 which is different from the substrate 600 through the isolation area 620 extends through. A gate electrode 640 is over three surfaces of the company 660 trained to train three gates. A hard mask 690 is on top of the gate electrode 640 educated. Gate spacers 670 . 680 are on opposite side walls of the gate electrode 640 educated. A p-type source region has the epitaxial region 631a on which is on a recessed source interface 650 as well as on a fin side wall 660 is formed, wherein a drain region of the epitaxial region 631a which is on a recessed source interface 650 as well as on the opposite side of the fin 660 (not shown) is formed. In addition, an n-type source region has the epitaxial region 631e on which is on a recessed source interface 650 as well as on a fin side wall 660 is formed, wherein a drain region of the epitaxial region 631b which is on a recessed source interface 650 as well as on the opposite side of the fin 660 (not shown) is formed. A III-V material topcoat 641 is above the source / drain regions 631a and 631b deposited. It should be noted that the III-V material topcoat 641 may be provided in the recessed (tip) region, in other embodiments being provided only over the source / drain regions (and not in the recessed regions). In one embodiment, the isolation areas are 620 Shallow trench isolation (STI) regions formed using conventional techniques, such as by etching the substrate 600 to form trenches, and then depositing an oxide material on the trenches to form the STI regions. The insulator areas 620 may be made of any suitable dielectric / non-conductive material, such as SiO ₂ .

The previous discussion with respect to the substrate 300 is equally applicable in the case described here (for example, the substrate 600 a silicon substrate or an XOI substrate, such as an SOI substrate, or a multilayer substrate). As can be seen in the light of the disclosure, conventional processing and formation technologies can be used to fabricate the FinFET transistor structure. According to an exemplary embodiment of the present invention, the structure of the source / drain regions 631a and 631b as well as the cover layer 641 however, for example using an in-situ doped silicon or SiGe (also for 631a and 631b ) covered with a III-V material layer (for 641 ). As will be further appreciated, an alternative to the triple-gate configuration is in a dual-gate architecture which includes a dielectric / insulator layer on top of the fin 660 includes. It should also be noted that the exemplary shape of the source / drain regions 631 (a and b), which are in 4a is not intended to limit the claimed invention to any particular source / drain or formation processes, and other source / drain shapes (both p and n) are obvious in the light of the disclosure (for example, round, square, and square) or rectangular p and n source / drain regions can also be implemented).

It is to be recognized that the source / drain areas 631 (a and b), which are in 4A have been formed using a replacement process (for example, etching, epitaxial deposition, etc.). However, in other embodiments, the source / drain regions 631 Part of the Finn 660 be made of the material of the substrate 600 self made as it is best in 4B is shown. Although only a source / drain area 631 5, a plurality of such regions may be implemented in similar fashion (including both n-type and p-type S / D regions). A III-V material topcoat 641 is above the source / drain regions 631 in a similar way as with respect to the 4A described, deposited. The beyond, with respect to the 4A cited discussion is equally applicable in the present case, as the skilled person will readily recognize.

Another alternative is the nanowire channel architecture, which, for example, a pedestal of substrate material 600 may comprise, on which a nanowire 660 grown (for example, silicon or SiGe) or otherwise provided, as best in 4C is shown. Similar to the fin structure that in 4B is shown, includes the nanowire 660 Source / drain regions 631 (with only one shown, but several such regions may be provided, including both p-type and n-type regions, as previously explained). Like the fin structure, the source / drain regions can 631 from the substrate material 600 be formed (from which also the nanowires are made), or from one or more replacement materials (for example, silicon or SiGe). The III-V material 641 can be, for example, all source / drain areas 631 of the nanowire 660 be provided around, or only at a portion of the nanowire 660 (for example, everywhere except the share on the podium). The 4D illustrates a nanowire configuration that includes multiple nanowires 660 (in this case, there are two). As can be seen, a nanowire becomes 660 in a depression of the substrate 600 provided, the other in the III-V material layer 641 swims. The corresponding source / drain regions 631 are shown with vertical hatching and may be p-type and / or n-type source / drain regions. The 4E also illustrates a nanowire configuration which includes multiple nanowires 660 wherein, in the example case, the non-active material 632 is not removed during the nanowire formation process between the individual nanowires, which may be carried out using various conventional technologies and will be recognized by those skilled in the art in light of the disclosure. It is thus a nanowire 660 in a depression of the substrate 600 provided, wherein the other nanowire 660 effectively on the top of the material 632 is attached. It should be noted that the nanowires 660 through the channel are active, this being the material 632 is not. The III-V material layer 641 is added to all other exposed surfaces of the nanowire 660 provided around. The corresponding source / drain regions 631 are shown with vertical hatching and may be p-type and / or n-type source / drain regions.

example systems

The 5 illustrates a computer system 1000 implemented with one or more transistor structures constructed in accordance with an exemplary embodiment of the present invention. As can be seen, is in the computer system 1000 a motherboard 1002 contain. The motherboard 1002 may include a plurality of components, including but not limited to a processor 1004 and at least one communication chip 1006 , both of which are physically and electrically connected to the motherboard 1002 connected or otherwise integrated into this. It will be appreciated that the motherboard 1002 for example, any printed circuit board, either a motherboard or a daughterboard mounted on a motherboard or the only board of the system 1000 is, etc. Depending on the specific application, the computer system 1000 include one or more components that are physically or electrically connected to the motherboard 1002 are connected. These other components may include volatile memory (e.g., DRAM), nonvolatile memory (e.g., ROM), graphics processor, digital signal processor, cryptoprocessor, chipset, display, touchscreen display, touchscreen controller, battery, and the like Audio codec, a video codec, a power amplifier, a global positioning system (also GPS), a compass, an accelerometer, a gyroscope, a speaker, a camera and a device for mass storage (such as a hard disk, a Compaktdisc (CD), a Digital Versatile Disc (DVD), etc.), but they are not limited to these. These transistor structures may be used, for example, to implement an onboard processor cache or memory array. In some embodiments, different functions may be integrated into one or more chips (for example, it should be noted that the communication chip 1006 Part of the processor 1004 or otherwise integrated in them).

The communication chip 1006 enables wireless communication for the transfer of data to and from the computer system 1000 , The term "wireless" and its derivatives can be used to describe circuits, components, systems, methods, technologies, communication channels, etc., which communicate data through the use of modulated electromagnetic radiation through a non-solid medium. This term is not intended to imply that the associated devices themselves do not contain wires, although in some embodiments this may be the case. The communication chip 1006 may use any wireless standard or wireless protocol, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA + , HSUPA +, EDGE, GSM, GPRS, DCMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocol identified as 3G, 4G, 5G, and beyond. The computer system 1000 can be a variety of communication chips 1006 include. For example, a first communication chip 1006 be designed for near field communication, such as WiFi and Bluetooth and a second communication chip 1006 can be designed for wide area wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1004 of the computer system 1000 includes an integrated circuit chip which is internal to the processor 1004 is packed. In some embodiments of the present invention, the integrated circuit chip includes an on-board memory circuit implemented with one or more CMOS transistor structures as described herein, the term "processor" may refer to any device or part of a device that does For example, electronic data is processed from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory.

The communication chip 1006 may also be an integrated circuit chip, which is within the communication chip 106 is packed. According to some example embodiments, the integrated circuit chip of the communication chip includes one or more devices implemented with one or more of the transistor structures described herein (eg, an on-chip processor or memory). As can be seen in the light of the disclosure, a multi-standard wireless capability can be incorporated directly into the processor 1004 integrated (for example, by the functionality of any chip 1006 in the processor 1004 is integrated instead of providing separate communication chips). In addition, the processor can 1004 a chipset having such a wireless capability. In short, any conceivable number of processors 1004 and / or communication chips 1006 be used. Likewise, each chip or chip set may have multiple integrated functions.

In various embodiments, the computer system 1000 a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop comupter, a server, a printer, a scanner, a monitor, a set-top Box, an entertainment control unit, a digital camera, a portable music player or a digital video recorder. In other embodiments, the system 1000 any other electronic device that processes data or requires transistor devices of the type described above with low contact resistance (for example, CMOS devices having both p-type and n-type devices).

Various embodiments are conceivable and the features described herein may be combined in any conceivable composition. An exemplary embodiment of the present invention forms a semiconductor integrated circuit. The integrated circuit includes a substrate having a plurality of channel regions and a gate electrode over each channel region, wherein a gate dielectric layer is provided between each gate electrode and a corresponding channel region. The integrated circuit further includes p-type source / drain regions in the substrate and adjacent to a corresponding channel region, and n-type source / drain regions in the substrate and adjacent to a corresponding channel region. The integrated circuit further comprises a III-V semiconductor material layer on at least a portion of the p-type source / drain regions and a portion of the n-type source / drain regions. The integrated circuit further includes metal contact on the III-V semiconductor material layer. In some cases, the III-V semiconductor material layer is undoped. In some example cases, the III-V semiconductor material layer has a band gap of less than 0.5 eV. In other example cases, the III-V semiconductor material layer has a band gap of less than 0.2 eV. In some cases, the III-V semiconductor material layer is doped. In such cases, the III-V semiconductor material layer has a doping scheme which is the same for both the p-type and n-type source / drain regions. In other such cases, the III-V semiconductor material layer has a first doping scheme for the p-type source / drain regions and a second doping scheme for the n-type source / drain regions. The III-V semiconductor material layer may be doped, for example with one or more amphoteric dopants (C, Si, Ge and / or Sn). In such a case, the III-V semiconductor material layer is doped with one or more amphoteric dopants, with an exchange concentration of 1E18 atoms / cm ³ . The component can be implemented, for example, by means of a planar transistor architecture or with a non-planar transistor architecture. In such a case, the non-planar transistor architecture has at least one FinFET transistor and / or one nanowire transistor. In some cases, the p-type and n-type soure / drain regions include silicon or germanium or an alloy thereof. Another embodiment of the present invention provides an electronic component that includes a printed circuit board having one or more integrated circuits that have been described in various ways in this paragraph. In such a case, the other or the plurality of integrated circuits has at least one communication chip and / or one processor. The device may be, for example, a computer.

Other embodiments of the present invention provide a device comprising a silicon-containing substrate having a plurality of channel regions, and a gate electrode over each channel region, wherein a gate dielectric layer is provided between each gate electrode and / or a corresponding channel region , The device further includes p-type source / drain regions in the substrate and adjacent a corresponding channel region, the p-type source / drain regions comprising silicon, germanium, or an alloy thereof, and wherein n-type source / Drain regions in the substrate and adjacent to a corresponding channel region, wherein the n-type source / drain regions silicon, germanium or an alloy thereof. The device further comprises a III-V semiconductor material layer on at least a portion of the p-type source / drain regions and on a portion of the n-type source / drain regions, and a metal contact on the III-V Semiconductor material layer for each of the p-type and n-type source / drain regions. According to a particular exemplary embodiment, a III-V material deposition of InSb on Si, a SiGe alloy and Ge source / drain regions is predicted by simulation in order to counteract the conductivity as low as possible a barrier. Other suitable III-V material layers will be apparent to those skilled in the art in light of the disclosure. In some cases, the III-V semiconductor material layer is undoped. In some cases, the III-V semiconductor material layer has a band gap of less than 0.5 eV. In some cases, the III-V semiconductor material layer is doped. In some such cases, the III-V semiconductor material layer has a doping scheme which is the same for the p-type and n-type source / drain regions. In other such cases, the III-V semiconductor material layer has a first doping scheme for the p-type source / drain regions and a second doping scheme for the n-type source / drain regions. In some cases, the III-V semiconductor material layer is doped with one or more amphoteric dopant such as Ge (z. B. exchange with a concentration greater than 1E18 atoms / cm ^3).

Another embodiment of the present invention provides a method of forming a semiconductor device. The method includes providing a substrate having a plurality of channel regions, and providing a gate electrode above each channel region, wherein a gate dielectric layer is provided between the gate electrode and a corresponding channel region. The method further includes providing p-type source / drain regions in the substrate and adjacent to a corresponding channel region, and providing n-type source / drain regions in the substrate and adjacent to a corresponding channel region. The method further comprises providing a III-V semiconductor material layer on at least a portion of the p-type source / drain regions and a portion of the n-type source / drain regions. The method further comprises providing a metal contact on the III-V semiconductor material layer.

The foregoing description of the embodiments of the invention has been presented for purposes of illustration and description. This is not intended to be exhaustive or to limit the invention to the exact embodiments illustrated. Many different variations and variations are conceivable in light of the revelation. It is intended that the scope of the invention be limited not by the precise description, but rather by the appended claims.

Claims (25)

A semiconductor integrated circuit comprising: a substrate having a plurality of channel regions; a gate electrode above each channel region, wherein a gate dielectric layer is provided between each gate electrode and a corresponding channel region; p-type source / drain regions in the substrate and adjacent to a respective channel region; n-type source / drain regions in the substrate and adjacent to a respective channel region; a III-V semiconductor material layer on at least a portion of the p-type source / drain regions and on a portion of the n-type source / drain regions; and a metal contact on the III-V semiconductor material layer. An integrated circuit according to claim 1, wherein the III-V semiconductor material layer is undoped. An integrated circuit according to claim 1 or 2, wherein the III-V semiconductor material layer has a band gap of less than 0.5 eV. An integrated circuit according to any one of the preceding claims, wherein the III-V semiconductor material layer has a band gap of less than 0.2 eV. An integrated circuit according to claim 1, wherein said III-V semiconductor material layer is doped. The integrated circuit of claim 5, wherein the III-V semiconductor material layer has a doping scheme that is the same for both the p-type and n-type source / drain regions. The integrated circuit of claim 5, wherein the III-V semiconductor material layer has a first doping scheme for the p-type source / drain regions and a second doping scheme for the n-type source / drain regions. An integrated circuit according to any one of claims 5 to 7, wherein the III-V half-fiber material layer is doped with one or more amphoteric dopants. The integrated circuit of claim 8, wherein the III-V semiconductor material layer is doped with one or more amphoteric dopants at an exchange concentration of greater than 1E18 atoms / cm ³ . An integrated circuit according to any one of the preceding claims, wherein the device is implemented with a planar transistor architecture. An integrated circuit according to any one of the preceding claims, wherein the device is implemented with a non-planar transistor architecture. The integrated circuit of claim 11, wherein the non-planar transistor architecture comprises FinFET transistors and / or nanowire transistors. An integrated circuit as claimed in any one of the preceding claims, wherein the p-type and n-type source / drain regions comprise silicon, germanium or an alloy thereof. An electronic component comprising a printed circuit board having one or more integrated circuits according to any one of the preceding claims. The electrical component of claim 14, wherein the one or more integrated circuits comprise at least one communication chip and / or a processor. An electronic component according to claim 14 or 15, wherein the component is a computer. Component comprising: a silicon-containing substrate having a plurality of channel regions; a gate electrode above each channel region, wherein a gate dielectric layer is provided between each gate electrode and a corresponding channel region; p-type source / drain regions, in the substrate and adjacent to a respective channel region, the p-type source / drain regions comprising silicon, germanium, or an alloy; n-type source / drain regions, in the substrate and adjacent to a respective channel region, the n-type source / drain regions comprising silicon, germanium, or an alloy thereof; a III-V semiconductor material layer on at least a portion of the p-source / drain regions and a portion of the n-type source / drain regions; and a metal contact on the III-V semiconductor material layer for both the p-type and n-type source / drain regions. The device of claim 17, wherein the III-V semiconductor material layer is undoped. The device of claim 17, wherein the III-V semiconductor material layer is doped. The device of claim 19, wherein the III-V semiconductor material layer has a doping scheme that is the same for both the p-type and n-type source / drain regions. The device of claim 19, wherein the III-V semiconductor material layer has a first doping scheme for the p-type source / drain regions and a second doping scheme for the n-type source / drain regions. A device according to any of claims 19 to 21, wherein the III-V semiconductor material layer is doped with one or more amphoteric dopants. The device of claim 22, wherein the III-V semiconductor material layer is doped with one or more amphoteric dopants at an exchange concentration of greater than 1E18 atoms / cm ³ . A device according to any one of claims 17 to 23, wherein the III-V semiconductor material layer has a bandgap of less than 0.5 eV. A method of forming a semiconductor device, comprising: Providing a substrate having a plurality of channel regions; Providing a gate electrode above each channel region, providing a gate dielectric layer between each gate electrode and a corresponding channel region; Providing p-type source / drain regions in the substrate and adjacent to a corresponding channel region; Providing n-type source / drain regions in the substrate and adjacent to a corresponding channel region; Providing a III-V semiconductor material layer on at least a portion of the p-type source / drain regions and a portion of the n-type source / drain regions; and Providing a metal contact on the III-V semiconductor material layer.

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