KR102352659B1 - Low Damage Self-Aligned Amphoteric FINFET Tip Doping - Google Patents

Abstract

A monolithic finFET includes multiple carrier channels in a first group III-V compound semiconductor material disposed on a second group III-V compound semiconductor. While a mask, such as a sacrificial gate stack, covers the channel region, a source of amphoteric dopant is deposited over the exposed fin sidewalls and diffuses into the first III-V compound semiconductor material. The amphoteric dopant is preferentially activated as a donor in the first group III-V material and as an acceptor in the second group III-V material, having a pn junction between the first and second group III-V materials. Provides transistor tip doping. A lateral spacer is deposited to cover the tip portion of the pin. Source/drain regions in regions of the fin not covered by the mask or spacer electrically couple to the channel through the tip region. The channel mask is replaced by a gate stack.

Description

Low Damage Self-Aligned Amphoteric FINFET Tip Doping

Efforts to extend Moore's Law for integrated circuits (ICs) include the development of transistors using group III-V compound semiconductor materials (eg, InP, InGaAs, InAs). Although these non-silicon material systems have been used to fabricate metal oxide semiconductor field effect transistors (MOSFETs) and other types of high mobility transistors (HEMTs), the devices use III-V materials for the desired conductivity types. and performance limitations associated with difficulty in doping to activation levels. For example, doping by ion implantation processes customary in the fabrication of silicon-based FETs causes detrimental damage to group III-V compound semiconductor materials that do not readily anneal out.

Group III-V transistor architectures with active dopants accurately positioned relative to the channel region are therefore advantageous with techniques to avoid damage to the group III-V semiconductor material(s).

The subject matter described herein is illustrated by way of example and not limitation in the accompanying drawings. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, for clarity, the dimensions of some elements may be exaggerated relative to others. Moreover, where considered appropriate, reference labels have been repeated between the figures to indicate corresponding or analogous elements.
1 is a plan view of a III-V finFET including active dopants in a lightly-doped region of a fin structure, in accordance with some embodiments;
2A is a cross-sectional view through the length of a channel region and a lightly doped region of the III-V finFET shown in FIG. 1A , in accordance with some embodiments;
2B is a cross-sectional view through a fin width within a lightly doped region of the III-V finFET shown in FIG. 1A , in accordance with some embodiments;
FIG. 2C is a cross-sectional view through a fin width in a channel region of the III-V finFET shown in FIG. 1A , in accordance with some embodiments;
2D is a cross-sectional view through the length of the channel region, lightly doped region, and source/drain regions of the III-V finFET shown in FIG. 1A , in accordance with some embodiments;
3 is a cross-sectional view through the length of a channel region, lightly doped region, and source/drain regions of a III-V finFET, in accordance with some alternative embodiments;
4 is a flow diagram illustrating a method of fabricating a group III-V finFET with lightly doped regions, in accordance with some embodiments;
5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J, and 5K show that the method illustrated in FIG. 4 may be performed, in accordance with some embodiments. a cross-sectional view through the length of the channel region, lightly doped regions, and source/drain regions of a III-V finFET as shown when;
6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 6I, 6J, and 6K show that the method illustrated in FIG. 4 may be performed, in accordance with some embodiments. a cross-sectional view through the width of the fin structure in the lightly doped region of a III-V finFET as shown when;
7 illustrates a mobile computing platform and data server machine using a SoC comprising a plurality of III-V finFETs comprising active dopants in a lightly doped region of a fin structure, in accordance with embodiments of the present invention; ;
8 is a functional block diagram of an electronic computing device, in accordance with one embodiment of the present invention.

One or more embodiments are described with reference to the accompanying drawings. While specific configurations and arrangements have been shown and discussed in detail, it will be understood that this is by way of example only. Those skilled in the art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the present description. It will be apparent to one of ordinary skill in the art that the techniques and/or arrangements described herein may be used in a variety of other systems and applications other than those specifically described herein.

DETAILED DESCRIPTION In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and illustrate exemplary embodiments. Moreover, it will be appreciated that other embodiments may be utilized and structural and/or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references, eg, above, below, top, bottom, may be used merely to facilitate description of features in the drawings. Accordingly, the following detailed description should not be construed in a limiting sense, but the scope of the claimed subject matter is limited only by the appended claims and their equivalents.

In the description that follows, numerous details are set forth. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known methods and devices have been shown in block diagram form rather than in detail in order to avoid obscuring the present invention. Reference throughout this specification to “an embodiment” or “an embodiment” or “some embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is at least one of the present invention. means to be included in the examples of Thus, the appearances of phrases such as “in an embodiment” or “in one embodiment” or “some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Moreover, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment wherever specific features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in this description and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term “and/or,” as used herein, refers to and encompasses all possible combinations of one or more of the listed related items.

The terms “coupled” and “connected”, along with their derivatives, may be used herein to describe functional or structural relationships between components. It will be appreciated that these terms are not intended as synonyms for each other. Rather, in certain embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" means that two or more elements are in physical or electrical contact with each other directly or indirectly (with other intervening elements between them) and/or that two or more elements are in physical or electrical contact (e.g., cause and may be used to indicate that they are cooperating or interacting with each other (as in an outcome relationship).

The terms “above,” “below,” “between,” and “on,” as used herein, refer to one component relative to other components or materials when such physical relationships are notable. or the relative position of the material. For example, with respect to materials, one material or material disposed above or below another may be in direct contact or may have one or more intervening materials. Moreover, two materials or one material disposed between the materials may be in direct contact with the two layers, or may have one or more intervening layers. Alternatively, a first material or material “on” a second material is in direct contact with the second material. Similar distinctions should be made with respect to component assemblies.

As used throughout this description and in the claims, a list of items linked by the terms “at least one of” or “one or more of” may mean any combination of the listed items. For example, the phrase “at least one of A, B, or C” means A; B; C; A and B; A and C; B and C; or A, B, and C.

The inventors have found that for FETs using III-V compound semiconductor material, it is often difficult to achieve low device resistance and avoid significant short channel effects (SCEs). For the highest carrier mobility, the transistor channel region is advantageously doped as lightly as possible (eg ideally not doped). However, the source/drain regions are advantageously doped as heavily as possible for low external resistance. Even when both of these conditions are met, the difficulty in controlling the group III-V material doping between the channel region and the source/drain regions is one factor contributing to the observed limitations in device performance metrics. .

In silicon devices, many advanced ion implants have been implemented to control dopant profiles between the channel region and the source/drain as well as below the channel region. For example, high-angle, low energy (HALO) ion implantation is often used to reduce _{transistor off-state leakage current I off} by introducing p-type dopants underneath the n-type channel. Well controlled ion implantation is also often used to lightly dope tip regions in so-called “underlapped” gate architectures. In an underwrapped gate, heavily doped source/drain regions are used to minimize the transistor on-state resistance (R _on ) associated with the underlap while improving the off-state leakage current I _{off .} It is separated from the gate electrode stack by an intervening lateral spacet of semiconducting material lightly doped with a conductive type. However, these ion implantation techniques, at least for the reason that conventional implantation of an ionic dopant species causes damage to group III-V compound semiconductor materials that do not readily anneal out, into group III-V material systems. not easily transferred Implanted dopants may also not activate or diffuse in a manner dependent on silicon device architectures.

In some embodiments, the non-silicon finFET is a non-planar, monocrystalline Group III-V semiconductor material device region disposed over a heterogeneous monocrystalline III-V semiconductor material (eg, a sub-fin region). (eg, a fin channel region). While a mask, such as a sacrificial gate stack, protects the channel region, a source of dopant is deposited over the exposed fin surfaces and diffuses into at least the III-V compound semiconductor fin material. In some embodiments, the dopant is an amphoteric dopant that is preferentially activated as an electron donor in the III-V fin material. Introducing this dopant into the tip region of the fin adjacent to the fin channel region can thereby provide light doping of the same conductivity type as the more heavily doped source/drain regions. In further embodiments, the amphoteric dopant introduced into the sub-fin is preferentially activated as an electron acceptor in this second group III-V material, thereby being disposed below the n-type tip region. Provide or maintain a lightly doped p-type sub-tip region. This complementary doping of the sub-tip region _{may reduce off-state leakage I off} and/or improve transistor SCE in a manner similar to p-pocket implants in silicon NMOS devices. have. The difference in amphoterism between the different group III-V materials of the fin and sub-fin is thereby used to control the vertical positioning of the tip and sub-tip regions. Precise control of the lateral positioning of the tip and sub-tip regions can further be achieved by masking the channel region during low damage, surface-based amphoteric doping of both the tip and sub-tip. Precise control of the lateral dimensions of the tip and sub-tip regions is achieved by subsequently placing a self-aligned lateral spacer adjacent the channel mask to cover both the tip and/or sub-tip regions during source/drain formation. It can be further achieved by forming. Thus, in some embodiments, the source/drain regions of a completed III-V finFET are, at least in part, a lightly doped tip region having sub-channel leakage control provided via a complementary doped sub-tip region. electrically coupled to the channel through

1A is a plan view of a non-planar III-V MOS transistor 101 disposed over a first region of a substrate 105 and surrounded by an isolation material 180 . In some embodiments, the substrate 105 is silicon (Si), which is advantageous for monolithic integration of the transistor 101 with conventional silicon-channeled MOSFETs. Transistor 101 may then be an NMOS device and the silicon MOSFET may be a PMOS device, enabling higher performance and/or higher density monolithic CMOS integrated circuits. The crystallographic orientation of the substantially monocrystalline substrate 105 is, in exemplary embodiments, (100), (111), or (110). However, other crystallographic orientations are also possible. For example, the substrate working surface may be tilted at 2 to 10° with respect to [110], for example to facilitate nucleation of crystalline heteroepitaxial material. It can be miscut or offcut. Other substrate embodiments are also possible. For example, the substrate 105 may be any of silicon carbide (SiC), sapphire, a group III-V compound semiconductor (eg, GaAs), silicon on insulator (SOI), germanium (Ge), or silicon-germanium (SiGe). may be of

The isolation material 180 can be any material suitable to provide electrical isolation between transistors. In some demonstrative embodiments, the isolation material 180 is silicon dioxide. Other materials known to be suitable for that purpose may also be used, including low-k materials (eg, having a relative dielectric constant less than 2.5). Although embodiments are not limited in this respect, other exemplary isolation materials include carbon-doped oxides (CDOs), siloxane derivatives and polymeric dielectrics (eg, benzocyclobutene, porous methyl silsesquioxane).

In exemplary embodiments, transistor 101 is a first III-V compound semiconductor material disposed on a “sub-fin” of a second III-V compound semiconductor material, as further described below. group III-V semiconductor heterojunction fin (“hetero-fin”) structure 103 further comprising a “fin” of A gate stack 170 is disposed over the channel region of the hetero-fin structure 103 . _{The gate stack 170 is associated with a non-zero gate length L g} , which may vary depending on the implementation, but in some embodiments is 50 nm or less (eg, 20 nm, 10 nm, etc.). A source/drain contact metallization 150 is laterally spaced from the gate stack 170 to make electrical contact with underlying heavily-doped group III-V compound semiconductor source/drain regions.

A lightly doped hetero-fin region 130 disposed between the channel region and the source/drain regions is associated with a _{non-zero lateral spacing L 1 .} The lateral spacing L ₁ may also vary depending on the implementation, but in some embodiments is 10 nm or less (eg, 5 nm). Hetero-fin region 130 is doped with a dopant to a ^{level lower (eg, atoms/cm 3} ) than the level of adjacent source/drain regions. In some demonstrative embodiments, the hetero-fin region 130 has a dopant level ^{of 10 11} - 10 ^{15 /cm3.} In some advantageous embodiments, hetero-fin region 130 is doped with a dopant that is substantially absent from the source/drain regions. In some further embodiments, the hetero-fin region 130 is doped with a dopant to a level higher than the level of the adjacent channel region. In some advantageous embodiments, the hetero-fin region 130 is doped with a dopant that is substantially absent from the adjacent channel region.

FIG. 2A illustrates a cross-sectional view through the length of the group III-V transistor 101 along the plane A-A' indicated in FIG. 1 . The length along the A-A′ plane includes the lightly doped hetero-fin region 130 and a portion of the hetero-fin 103 disposed below the gate stack 170 , in accordance with some embodiments. As further illustrated in FIG. 2A , the hetero-fin 103 connects the fin 120 of the first III-V compound semiconductor disposed on the sub-fin 110 of the second III-V compound semiconductor. include The two III-V materials of different composition may have any band resulting in at least one of a conduction band offset and a valence band offset between the fin 120 and the sub-fin 110 . A heterojunction 135 is formed at their interface associated with the gap difference.

In some embodiments, sub-fin 110 and fin 120 each have a first sub-lattice of at least one element from group III of the periodic table (eg, Al, Ga, In, etc.) and the periodic table It is a single crystal having a second sublattice of at least one element of group V (eg, N, P, As, Sb, etc.). Each of the sub-fins 110 and 120 is a binary, ternary, or quaternary comprising two, three, or even four elements of groups III and V of the periodic table, respectively. It may be a (quaternary) group III-V compound semiconductor. Since fin 120 is the device layer of transistor 101, it advantageously has high carrier (eg, electron) mobility, such as, but not limited to, InGaAs, InP, InSb, GaAs, and InAs. It is a group III-V material. In some exemplary InGaAs fin embodiments, the mole fraction of In is between 0.2 and 0.8. In some advantageous embodiments _{, the channel region of fin 120 associated with the effective channel length L eff} is an endogenous III-V material and is not intentionally doped with any electrically active impurity. Sub-fin 110 is advantageously significant for fin materials, such as, but not limited to, GaAs, InP, GaSb, GaAsSb, GaP, InAlAs, GaAsSb, AlAs, AlP, AlSb, and AlGaAs (e.g., It is a III-V material with a conductive) band offset. In some embodiments, fin 120 and sub-fin 110 are of complementary impurity types. For example, if fin 120 provides an electron majority carrier channel, sub-fin 110 may be doped with p-type impurities, such as Mg and Be.

In some embodiments, at least one of a fin tip region and a sub-tip region of a sub-fin region in the heterojunction fin is doped with an electrically active dopant. The hetero-pin region 130 indicated by a broken line in FIG. 2A includes a sub-tip region 133 of the sub-fin 110 , and a tip region 134 of the fin 120 . The tip region 134 is disposed at both ends of the channel region. The tip region 134 is further disposed below the lateral spacers 171 . In some embodiments where the channel region is intrinsic (ie, no intentional doping) and the source/drain is a regrown material, tip region 134 is the only extrinsically doped portion of fin 120 . . As noted above, the dopant levels in the fin tip regions (and/or sub-tip regions) are significantly lower than the source/drain impurity level. The light dopant level of the fin tip region can vary by many orders of magnitude. In some demonstrative embodiments, the fin tip regions have dopant levels of ^{10 11} - 10 ^{15 /cm3.} Effective activation efficiencies can also be very wide, for example between 10% and 100%.

In exemplary embodiments, tip region 134 is exogenously doped with one or more amphoteric dopants 136 . An amphoteric dopant comprises an atom that can occupy either a lattice site in a Group III sub-lattice or a lattice site in a Group IV sub-lattice. When the amphoteric dopant occupies the group III sub-lattice, the amphoteric dopant will function as a donor, making the group III-V material N-type. When the amphoteric dopant instead occupies the group IV sub-lattice, the amphoteric dopant will function as an acceptor, making the group III-V material more P-type. In some demonstrative embodiments, the amphoteric dopants 136 are Si. Alternative amphoteric dopant embodiments include Ge, Sn, Te, Se, O, and C. In some further embodiments, amphoteric dopants 136 include more than one amphoteric dopant (eg, two or more of Si and Ge, Si and Sn, Si and Te, Si and Se, or amphoteric dopants). any other combination of amphoteric dopants). In some exemplary embodiments where the channel region of the fin 120 is endogenous, the only extrinsic dopants present in the tip region 134 are the amphoteric dopants 136 . In other embodiments where the channel region of the fin 120 is exogenously doped, eg, with an n-type dopant, the tip region 134 may be doped with both amphoteric dopants 136 and a channel dopant. have.

In some embodiments, sub-tip region 133 is exogenously doped with one or more impurity elements. As illustrated in FIG. 2A , the sub-tip region 133 is disposed directly below the tip region 134 . In embodiments where the sub-fin 110 is doped complementary to the fin 120 , the doping of the tip region 134 preferably does not counter-dope the sub-tip region 133 . does not In embodiments where sub-fin 110 is not complementary to fin 120 doped (eg, sub-fin 110 is endogenous), doping of tip region 134 is preferably also Do not make sub-tip region 133 of the same conductivity type as tip region 134 . In an advantageous embodiment, both the tip region 134 and the sub-tip region 133 include amphoteric dopants 136 . In some such embodiments, both tip region 134 and sub-tip region 133 are doped with the same level or concentration of amphoteric dopants 136 . As described further below, the same amphoteric doping levels between the tip region 134 and the sub-tip region 133 represent the process used to introduce the amphoteric dopants 136 .

In some embodiments, the amphoteric dopants 136 are preferentially activated as a first impurity type in the fin 120 and preferentially as a complementary impurity type in the sub-fin 110 . This different amphotericity is used to precisely control the vertical (z) limits of tip region 134 and/or sub-tip region 133 to coincide with heterojunction 135 in transistor 101 . Therefore, in FIG. 2a , doping the entire hetero-pin region 130 in the dashed box spanning the _{z-height H 1} is a sub-tip region with a z-height _{of only H 2 below the heterojunction 135 (} 133) and at the same time providing a tip region 134 _{above the heterojunction 135 with a z-height of only H 1} -H _{2 .} For example, by introducing the amphoteric dopants 136 using well developed self-aligned fabrication techniques, the amphoteric dopants 136 can be further precisely controlled in the _{lateral dimension L 1 .} Thus, the different amphotericity may allow for relatively non-selective influx of amphoteric dopants into the hetero-fin 103 , some of which may advantageously cause little group III-V lattice damage.

In one advantageous embodiment where the fin 120 comprises a group III-V material with high electron mobility, the hetero-fin region 130 is formed with n-type donors (solid dots (solid dots) within the tip region 134 ). Amphoteric dopants 136 preferentially activated as p-type acceptors (illustrated as holes) within sub-tip region 133 and as exemplified by solid dots). doped with The p-type doping of the sub-tip region 133 can improve the performance of the transistor 101 in ways similar to HALO or pocket implants in silicon-channel type devices, for example, I _off and It can reduce SCE. Likewise, n-type doping of tip region 134 may improve the performance of transistor 101 in ways similar to tip implants in silicon-channel type devices, eg, may reduce _{R ext .} can

Control over whether the amphoteric dopants are eventually activated as one type or another is the amphoteric dopant concentration, the intrinsic lattice composition, the presence of other (co)impurities in the lattice; and amphoteric dopant activation conditions. In some embodiments, the amphoteric dopant concentration is different (eg, higher in fin 120 ) between fin 120 and sub-fin 110 , thus driving complementary activation. However, even in an embodiment in which the amphoteric doping levels in the tip region 134 and the sub-tip region 133 are the same, the effective conductivity type of the activated dopants is nevertheless, for example, sub-tip region 133 . Complementarity may be driven through differences in the intrinsic lattice compositions of fin 110 and fin 120 . Adding ternary and quaternary sublattices to one or the other of fin 120 and sub-fin 110 can drive advantageous amphoteric differences between the two. For example, a larger influx of Group III elements may thermodynamically favor incorporation of a smaller amphoteric dopant into the Group III sites, and vice versa. In an embodiment where fin 120 is, for example, InGaAs, silicon impurities may eventually occupy more group III sites than group V sites, resulting in effective n-type doping. this can be obtained. However, for example, silicon impurities introduced into the GaAs sub-fin 110 may preferentially occupy more group V sites, and as a result, effective p-type doping may be obtained. have.

2B illustrates a cross-sectional view through the hetero-fin width along the BB′ plane indicated in FIG. 1A , in accordance with some embodiments. The BB′ plane passes through the hetero-fin region 130 of the finFET 101 . As illustrated, along the fin z-height H ₁ , amphoteric dopants 136 are present throughout the _{hetero-fin width W 1 .} Although the width W ₁ may vary depending on the implementation, in exemplary embodiments it is less than 20 nm, advantageously less than 10 nm. In some embodiments, as further illustrated in FIG. 2B , the amphoteric doped portion of hetero-fin 103 is the portion that extends above sub-fin isolation 115 . _{In other words, the entire fin z-height H 1} , measured from the top surface of the sub-fin isolation 115 , is doped with amphoteric dopants 136 . Alternatively, the amphoteric dopants 136 are substantially free of the portions of the sub-fin 110 embedded in the sub-fin isolation 115 . Sub-pin isolation 115 may be any amorphous material suitable to provide electrical isolation between adjacent sub-pins. In some demonstrative embodiments, the sub-fin isolation 115 is silicon dioxide. Other known dielectric materials may also be used, including low-k materials. Although embodiments are not limited in this respect, other exemplary materials include carbon doped oxides (CDOs), siloxane derivatives, and the like.

FIG. 2C illustrates a cross-sectional view through the hetero-fin width along the C-C′ plane indicated in FIG. 1A , in accordance with some embodiments. The C-C' plane passes through the channel region of the III-V finFET 101 . As illustrated, the gate stack 170 includes a gate dielectric material 172 and a gate electrode material 173 . Although any known gate stack materials may be used, in one exemplary embodiment, a high-k material (eg, having a bulk relative dielectric constant of 9 or greater) is Used with a gate metal that has a work function suitable for its composition. In the exemplary embodiments illustrated by FIG. 2C , amphoteric dopants are not present in both the channel region of the fin 120 and the sub-channel region of the fin 110 .

2D illustrates a cross-sectional view through the length of a channel region, a tip region, and source/drain regions of a III-V finFET 101 , in accordance with some embodiments. FIG. 2D extends the field of view beyond that illustrated in FIG. 2A to further illustrate portions of lightly doped sub-fin 110 and fin 120 for heteroepitaxial source/drain 140 . In some embodiments, heteroepitaxial source/drain 140 is group III-V with different lattice components to provide an advantageously low band gap that facilitates low resistance with contact metallization 150 . compound semiconductors. The heteroepitaxially raised source/drain material 140 may be any material suitable for ohmic contact to the fin 120 , such as, but not limited to, InAs. In some embodiments, the source/drain material 140 is single-crystalline. The heteroepitaxially raised source/drain material 140 is advantageously heavily doped (eg, n-type in InAs embodiments).

In the exemplary embodiment illustrated in FIG. 2D , a lightly doped hetero-fin region such that the channel region of transistor 101 is electrically coupled to source/drain 140 via tip region 134 ( FIG. 2A ). 130 forms an interface with the heteroepitaxially raised source/drain 140 . As further illustrated in FIG. 2D , the heteroepitaxially raised source/drain 140 forms a first heterojunction with the fin 120 and a second heterojunction with the sub-fin 110 . In some demonstrative embodiments, heteroepitaxial source/drain 140 does not have any amphoteric dopants, which means that source/drain 140 is located on both sides of fin 120 and/or sub-fin 110 . It indicates that it was formed after sex doping. However, within the lightly doped hetero-fin region 130 along the first source/drain heterojunction, the amphoteric dopants preferentially be of the same conductivity type (eg, n-type) as the source/drain 140 . is activated In the sub-source/drain region 132 along the second heterojunction (indicated by the small dashed boxes in FIG. 2D ), the amphoteric dopants interact with the source/drain 140 and It is preferentially activated with a complementary conductive type (eg, p-type). In some embodiments, the amphoteric dopant in the sub-source/drain region 132 is the same as the amphoteric dopant in the hetero-fin region 130 . In further embodiments, the amphoteric dopant concentration in the sub-source/drain region 132 is the same as the amphoteric dopant concentration in the hetero-fin region 130 . This same dopant concentration indicates that both regions 130 and 132 were doped simultaneously, as further described below for some embodiments.

3 illustrates a cross-sectional view through the length of a channel region, a tip region, and source/drain regions of a III-V finFET 301 , in accordance with some alternative embodiments. In the embodiments illustrated by FIG. 3 , the source/drain regions are not fully regrown as in finFET 101 . Instead, fin 120 includes heavily doped source/drain ends 138 . The heavily doped source/drain ends 138 contain the same group III-V material as other regions of the fin 120 (eg, a channel region or lightly doped tip region, etc.), but with a greater impurity level. doped with In some demonstrative embodiments, the doped source/drain ends 138 do not have any amphoteric dopants, which means that the source/drain region 138 has a fin 120 and/or sub-fin 110 . indicates that it was formed after amphoteric doping of As further illustrated in FIG. 3 , the doped source/drain ends 138 form a heterojunction with the sub-fin 110 . Within the sub-source/drain region 132 along this heterojunction, the amphoteric dopants are preferentially activated with a conductivity type (eg, p-type) complementary to the source/drain ends 138 . In some embodiments, the amphoteric dopant in the sub-source/drain region 132 is the same as the amphoteric dopant in the hetero-fin region 130 . In further embodiments, the amphoteric dopant concentration in the sub-source/drain region 132 is the same as the amphoteric dopant concentration in the hetero-fin region 130 . This same dopant concentration indicates that both regions 130 and 132 were doped simultaneously, as further described below for some embodiments.

III-V finFETs according to the above architectures may be fabricated by various methods applying various techniques and processing chamber configurations. 4 is a flow diagram illustrating an exemplary method 401 of fabricating a finFET having lightly doped hetero-fin regions, in accordance with some embodiments. 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J, and 5K are shown when method 401 is performed, in accordance with some embodiments. Cross-sectional views along the DD′ plane of the finFET 101 are illustrated. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 6I, 6J, and 6K show that the method illustrated in FIG. 4 may be performed, in accordance with some embodiments. Cross-sectional views taken along the BB′ plane of the finFET 101 are illustrated.

Referring first to FIG. 4 , method 401 begins at operation 410 in which a group III-V heterojunction pin is fabricated. In some embodiments, numerous islands of group III-V material are epitaxially grown over a substrate having a plurality of seeding surface regions. In some such embodiments, in order to practice aspect ratio trapping (ART) and to achieve acceptable crystal quality in the heteroepitaxial fin material, the seeding surface areas are separated by high aspect ratio sidewalls. surrounded. The ART technique is an example of local additive heteroepitaxial fin fabrication, which can advantageously reduce the effects of thermal mismatch across various heterojunctions. In alternative embodiments, a conventional subtractive technique in which a blanket III-V film stack is grown over the entire processing surface of the substrate or transferred to the substrate. This can be used. The blanket film stack is then similarly etched into fin structures according to subsequent operations of method 401 .

5A and 6A , upon completion of operation 410 , a hetero-fin 103 is disposed on the substrate 105 , at least a portion of the fin 120 surrounds extends beyond the sub-pin isolation 115 by the z-height H _{1 .} In some embodiments, the z-height H ₁ is defined by recess etching a predetermined amount of sub-fin isolation material 115 from around the hetero-fin 103 . As further illustrated in FIG. 6A , the z-height H ₁ may vary depending on the extent of the recess etch, possibly exposing the sidewalls of the sub-fin 110 by the z-height H _{2 .} In alternative embodiments, a stop layer may be used (not shown) to ensure that the top surface of the sub-pin isolation 115 is flush with the heterojunction 135 .

4, the method 401 continues at operation 420 in which a channel mask is patterned to protect the portion of the hetero-fin that becomes the FET channel region. Although any known masking technique and material(s) may be used in operation 420 , in some embodiments, the channel mask may be replaced in a “gate-last” finFET manufacturing flow until replaced. It is a gate mandrel maintained through the processes of These embodiments are advantageously compatible with silicon-channel type finFET fabrication, allowing PMOS transistors to be fabricated simultaneously in different regions of the substrate (not shown). In the exemplary embodiment illustrated in FIGS. 5B and 6B , a sacrificial gate 570 is formed over a portion of the hetero-fin 103 . Any known sacrificial gate structure and fabrication techniques form a sacrificial gate 570 on at least two opposing sidewalls of the fin 120 , further removing any exposed sidewall portions of the sub-fin 110 . Covering and landing on sub-pin isolation 115 may be used in operation 420 . The sacrificial gate 570 may include any stripe of sacrificial gate 570 extending above the channel region of the fin 120 as well as any of the sub-fins 110 extending above the sub-fin isolation 115 . is patterned into a sub-channel region of Other portions of the hetero-pin 103 are exposed. In some embodiments, the sub-fin isolation 115 may be further recessed (not shown) to expose an additional portion of the sub-fin 110 underneath the sacrificial gate 570 . This recess may be anisotropic to retain the underlying sub-fin isolation 115 self-aligned to the sacrificial gate 570, or the sub-fin isolation 115 and the undercut sacrificial gate ( The undercut sacrificial gate 570 may be isotropic to laterally etch.

Returning to FIG. 4 , method 401 continues at operation 430 in which surfaces of the hetero-fin not protected by the channel mask or sub-fin isolation 115 are exposed to a dopant media. As described above, the dopant, in some embodiments, is an amphoteric dopant (eg, Si), such as any of those listed elsewhere herein. The fin surfaces exposed to the dopant medium are thus self-aligned to the channel mask (eg, sacrificial gate). After dopant exposure, in operation 440 a dopant is diffused into the hetero-fin. The diffused dopant location can be controlled with hetero-fin regions within a diffusion length from the surface in contact with the dopant medium.

The exposure to the dopant medium in operation 430 can take a variety of forms, but is advantageous via surface-based techniques that cause little lattice damage in the hetero-fin. One such technique involves the deposition of a solid thin film containing a mobile dopant. Alternatives include wetting the fin surfaces with a liquid agent comprising a dopant moiety or exposing the fin surfaces to a gaseous agent comprising dopant moieties. . Ultra low energy plasma surface treatments may also be practiced. For example, hetero-fin surfaces may be exposed to a plasma of a dopant while the substrate is maintained at a low plasma bias voltage. Any of these known techniques for applying to a material surface dopants compatible with the Group III-V hetero-fin materials and amphoteric dopants described herein can be used without limitation. For liquid and gaseous agents, dopant moieties can react with the sidewall (and top) surfaces of the hetero-pin, eg, dangling bonds and/or hydrogen bonds. can be combined to form a dopant monolayer on the fin surfaces. For liquid application of dopants, impurities are dissolved in a solvent. As an example, in a Se doped embodiment, Group III-V hetero-fin material surfaces may be exposed to an aqueous solution of _{seleno-DL-methionine (C 5} H ₁₁ N0 _{2 Se).}

In some embodiments, promote solid-state in-diffusion of the dopant into the hetero-fin volume and/or delay dopant outgassing or sublimation from the hetero-fin surface. To do so, a capping material layer may be deposited over either the dopant medium (eg, doped thin film) or surface-bound dopant moieties prior to dopant diffusion. Dopant diffusion may be driven/controlled by any known technique, such as but not limited to rapid thermal processing (RTP). After dopant diffusion/activation, any capping material may be stripped to again expose surfaces not protected by the channel mask in preparation for subsequent processing.

In the exemplary embodiment, illustrated in FIGS. 5C and 6C , a thin film 520 doped with a dopant to be transferred to the surface of the hetero-fin is deposited on the exposed surfaces of the hetero-fin 103 , such that the sacrificial gate (570) is further covered. In some embodiments, an organometallic source, oxygen source, and silicon hydrate (eg, silane) are reacted by plasma discharge to form a doped oxide layer. The oxide coated substrate is then heated to drive impurities from the oxide into the semiconductor. Exemplary doped thin films that may be used include: selenium-doped oxide, tellurium-doped oxide, or carbon doped oxide. Other exemplary embodiments include non-stoichiometric silicon-rich silicon nitride films. As further illustrated in FIG. 6D , dopants diffuse from thin film 520 into regions of hetero-fin 103 proximate to all surfaces in contact with doped thin film 520 . As a doped thin film 520 is deposited over all exposed fin surfaces, the dopants only need to diffuse from each fin sidewall by approximately one-half the fin width. For example, if the fin width W ₁ is less than 10 nm, the dopants need only be diffused by less than 5 nm to occupy the grating sites across the fin width. Dopants applied to the fin surface can thus diffuse to be substantially uniform within the fin volume. Once activated, the amphoteric differences ensure that any doped portion of the sub-pin 110 retains the pn junction located at the heterojunction 135 .

4 , operations 430 and 440 may be repeated as many times as necessary to achieve a desired dopant concentration as a function of at least dopant concentration in the dopant medium, dopant mobility, and dopant activation efficiency. After lightly doping the III-V fin, the method 401 continues at operation 450 by fabricating the lateral spacers around the channel mask. Any conventional self-aligning lateral spacer process operates 450 to form a protective structure over the lightly doped tip region and/or sub-tip region and laterally standoff from the channel mask for subsequent processing. ) can be used in For example, a dielectric (eg, silicon dioxide and/or silicon nitride) may be blanket deposited conformally over the hetero-fin and over the channel mask. An anisotropic etch is then used to remove the dielectric except at the edge of the topography. In exemplary embodiments further illustrated in FIGS. 5E and 6E , a lateral spacer 171 is formed adjacent the sacrificial gate 570 . Due to the proximity of the fin tip region to the sacrificial gate 570 (because it is self-aligned), the lateral spacers 171 extend above the lightly doped fin tip region. A lateral spacer 171 is also formed adjacent to the sidewalls of the fin 120 as well as any exposed sidewalls of the sub-fin 110 .

In some embodiments of method 401 ( FIG. 4 ), fin surface doping may be repeated after operation 450 to further increase the amount of amphoteric dopant in the now self-aligned region in the lateral spacer 171 . have. Alternatively, a different (amphoteric) dopant may be introduced via surface doping operation 430 performed after operation 450 . In still other embodiments, the lateral spacer formation operation 450 may be re-ordered relative to the surface doping operation 430 such that the operations 430 and 440 are performed only after the lateral spacer is formed. In such embodiments, one may rely on lateral diffusion of amphoteric dopants to dope the tip and sub-tip regions in a self-aligned manner to the lateral spacer.

Upon completion of the light doping of the hetero-fin, method 401 proceeds to operation 460 in which source/drain regions are formed. In some embodiments, operation 460 includes etching at least the ends of fin 120 and epi-doped group III-V semiconductor from seeding surfaces of fin 120 and/or sub-fin 110 . It involves taxially regrowth. Any known epitaxial source/drain regrowth technique may be used. 5F and 6F , to the sub-fin 110 to remove ends of the fin 120 that are not protected by the sacrificial gate 570 or lateral spacer 171 . A selective etch is performed on the fins 120 for the fins 120 . This source/drain recess etch may undercut the lateral spacers 171 by some predetermined amount, but at least some lightly doped tip portions 134 remain. Dopants introduced into the sub-fin 110 also remain. As further illustrated in FIGS. 5G and 6G , for example, by any of metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE), crystalline hetero Epitaxial source/drain 140 is then grown. The material (eg, InAs or other group III-V material) may be heavily in-situ doped (eg, n-type). In exemplary embodiments, the source/drain regrowth does not use amphoteric dopants.

In alternative embodiments, no source/drain recess etch is performed at operation 460 , instead the source/drain end portions of the fin 120 are subjected to any known technique, including ion implantation. highly doped by In some of these embodiments, the source/drain doping again does not use amphoteric dopants. A raised source/drain may grow over the source/drain end portions of the fin 120 . For example, any of the heteroepitaxial techniques described above can be used to form narrow band gap raised source/drain material. This epitaxial material may further serve as a source of dopants that diffuse into the source/drain end portions of the fin 120 . In exemplary embodiments, the raised source/drain does not use amphoteric dopants.

Returning to FIG. 4 , the method 401 continues at operation 470 where the channel mask is replaced with a permanent gate stack. Method 401 is then substantially completed with any suitable contact metallization and backend processing performed in operation 480 . In the exemplary embodiment further illustrated in FIGS. 5H and 6H , finFET isolation 180 is deposited and planarized to expose the top of sacrificial gate 570 . As further shown in FIGS. 5I and 6I , the sacrificial gate 570 is selectively removed relative to the isolation 180 , such that the channel region of the fin 120 (and possibly the sub-channel region of the fin 110 ) ) is exposed. A permanent gate stack including a gate dielectric 172 and a gate electrode 173 is formed over at least two sidewalls of the fin structures, as shown in FIGS. 5J and 6J . Although any known gate stack materials can be used, in one exemplary embodiment, a high-k dielectric material is used with a metal gate electrode having a workfunction suitable for the group III-V composition of fin 120 . . 5K and 6K, the source/drain contact metallization 150 is formed by any known technique, and the finFET 101 is substantially the same as introduced in FIGS. 1A-1D.

7 is a heteroepitaxial Group III-V n-type transistor having lightly doped tip and/or sub-tip regions, doped with an amphoteric dopant, eg, as described elsewhere herein. It illustrates a mobile computing platform and data server machine using an SoC that includes Server machine 706 may include any number of, for example, placed within a rack, including packaged monolithic SoC 750 , and networked together for electronic data processing, in an exemplary embodiment. It may be any commercial server including high performance computing platforms. The mobile computing platform 705 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transfer, and the like. For example, the mobile computing platform 705 may be any of a tablet, smartphone, laptop computer, etc., and may be a display screen (eg, capacitive, inductive, resistive, or optical touchscreen), chip level, or package level. may include an integrated system 710 , and a battery 715 .

The packaged monolithic SoC 750 , whether deployed within the integrated system 710 illustrated in expanded view 720 , or as a stand-alone packaged chip within the server machine 706 . ) is, for example, at least one heteroepitaxial group III-V n-type having lightly doped tip and/or sub-tip regions, doped with an amphoteric dopant, as described elsewhere herein. a memory block (eg, RAM) including transistors, a processor block (eg, microprocessor, multicore microprocessor, graphics processor, etc.). The monolithic SoC 750 includes (eg, digital baseband) including a power management integrated circuit (PMIC) 730, a wideband RF (wireless) transmitter and/or receiver (TX/RX), and an analog front The end module further includes a power amplifier on the transmit path and a low noise amplifier on the receive path) a board, substrate, or interconnect with one or more of an RF (radio) integrated circuit (RFIC) 725 , and a controller 735 . It may be further coupled to an interposer 760 .

Functionally, PMIC 730 can perform battery power regulation, DC-DC conversion, etc., and thus has an input coupled to battery 715 and an output that provides a current supply to other functional modules. As further illustrated, in an exemplary embodiment, the RFIC 725 is a Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+ , HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols designated as 3G, 4G, 4G and more, including but not limited to including an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols. In alternative implementations, each of these board level modules may be integrated on separate ICs or integrated within the monolithic SoC 750 .

8 is a functional block diagram of an electronic computing device, according to an embodiment of the present invention. Computing device 800 may be found within platform 705 or server machine 706 , for example. Device 800 is, for example, as described elsewhere herein, at least one heteroepitaxial group III-V having lightly doped tip and/or sub-tip regions, doped with an amphoteric dopant. It further includes a motherboard 802 hosting a number of components, such as, but not limited to, a processor 804 (eg, an application processor), which may further include n-type transistors. The processor 804 may be physically and/or electrically coupled to the motherboard 802 . In some examples, the processor 804 includes an integrated circuit die packaged within the processor 804 . Generally, the term "processor" or "microprocessor" refers to a process that processes electronic data from registers and/or memory and converts the electronic data into other electronic data that may be further stored in registers and/or memory. It may refer to any device or part of a device.

In various examples, one or more communication chips 806 may also be physically and/or electrically coupled to the motherboard 802 . In further implementations, the communication chips 806 may be part of the processor 804 . Depending on its applications, computing device 800 may include other components that may or may not be physically and electrically coupled to motherboard 802 . These other components include volatile memory (eg DRAM), non-volatile memory (eg ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, touchscreen display, touchscreen controller, battery, audio codec , video codecs, power amplifiers, global positioning system (GPS) devices, compass, accelerometer, gyroscope, speaker, camera, and (hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile (DVD) disk) and the like)).

The communication chips 806 may enable wireless communication for the transfer of data to and from the computing device 800 . The term “wireless” and its derivatives refers to circuits, devices, systems, methods, techniques, communication channels capable of transmitting data using modulated electromagnetic radiation through a non-solid medium. It can be used to describe etc. Although this term does not imply that the related devices do not include any wires, in some embodiments the related devices may not. The communication chips 806 may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device 800 may include a plurality of communication chips 806 . For example, a first communication chip may be dedicated to short range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to GPS, EDGE, GPRS, CDMA, WiMAX, LTE , Ev-DO, and the like, may be dedicated to long range wireless communications.

Although certain features described herein have been described with reference to various implementations, this description should not be construed in a limiting sense. Accordingly, various modifications of the implementations described herein, as well as other implementations apparent to those skilled in the art to which this disclosure pertains, are considered to fall within the spirit and scope of this disclosure.

It will be appreciated that the present invention is not limited to the embodiments so described, but may be practiced with modifications and variations without departing from the scope of the appended claims. For example, the above embodiments may include certain combinations of features as further provided below.

In one or more first embodiments, the monolithic transistor comprises a III-V heterostructure disposed on a substrate, wherein the heterostructure is a first III-V compound semiconductor disposed on a second III-V compound semiconductor material. Contains - Including materials. The transistor further includes a gate stack disposed over the channel region of the first III-V compound semiconductor material. The transistor has a pair of source/drain regions electrically coupled to opposite ends of the channel region through a tip region in a group III-V compound semiconductor material, the tip region being an amphoteric dopant contains - additionally includes.

In at least some of the first embodiments, the majority charge carrier in the channel region is an electron, and the amphoteric dopant is a donor in the group III-V compound semiconductor material and the second III In the -V compound semiconductor material, it is preferentially activated as an acceptor.

In at least some of the first embodiments, a sub-tip region of the second III-V compound semiconductor material comprises the same concentration of an amphoteric dopant as the tip region, wherein the amphoteric dopant reinforces the pn junction at the heterojunction of the first and second group III-V materials.

In at least some of the first embodiments, the first III-V material is selected from the group consisting of InGaAs, InAs, GaAs, InP, and InSb.

In at least some of the first embodiments, the second III-V material is selected from the group consisting of InP, AlSb, GaSb, GaAlSb, GaAsSb, InAlAs, GaAs, and AlGaAs.

In at least some of the first embodiments, the amphoteric dopant is selected from the group consisting of Ge, Si, C, Sn, Te, Se, O.

In at least some of the first embodiments, the first III-V material comprises two or more of In, Ga, and As, and the amphoteric dopant is Si.

In at least some of the first embodiments, the pair of source/drain regions are in contact with the tip region and the second III-V compound semiconductor material and are sub-source/drain of the second III-V compound semiconductor material. and a third group III-V compound semiconductor in contact with the sub-source/drain region, the sub-source/drain region also comprising an amphoteric dopant.

In at least some of the first embodiments immediately above, the sub-source/drain region comprises the same concentration of an amphoteric dopant as the tip region, wherein the amphoteric dopant comprises a third and second III-V material reinforce pn junctions in their heterojunctions.

In one or more second embodiments, a CMOS integrated circuit (IC) includes a silicon substrate, an n-type III-V-channel type fin field effect transistor (finFET) disposed over a first region of the substrate. The III-V FET further includes a III-V heterostructure fin disposed on the substrate. The heterostructure fin includes a fin of a first n-type III-V compound semiconductor material disposed on a sub-fin of the p-type III-V compound semiconductor material. A group III-V FET includes a gate stack disposed over a channel region of the fin, and a second n-type III-V compound semiconductor material electrically coupled to opposite ends of the channel region through a tip region of the fin. further comprising a pair of source/drain regions, the tip region comprising an amphoteric dopant, the tip region disposed on a sub-tip region of the sub-fin also comprising an amphoteric dopant. The CMOS IC further includes a p-type silicon-channeled FET disposed over the second region of the substrate.

In at least some of the second embodiments, the amphoteric dopant is at least one of Si, C, Ge, Sn, Te, Se, and O, as a donor in the tip region and suppression in the sub-tip region. It is preferentially activated as a receptor, and the tip region and the sub-tip region contain the same concentration of amphoteric dopant.

In at least some of the second embodiments, the second n-type group III-V compound semiconductor material is in contact with a sub-source/drain region of the second group III-V compound semiconductor material, and the sub-source/drain region The drain region also contains the same concentration of amphoteric dopant as the tip region.

In one or more third embodiments, a method of fabricating a III-V-channel type fin field effect transistor (finFET) comprises forming a III-V heterostructure fin disposed on a substrate, wherein the heterostructure fin is a p- consisting of an n-type III-V compound semiconductor material disposed on the sub-fin of the type III-V compound semiconductor material. The method includes forming a mask over a channel region of the fin. The method includes contacting the exposed surfaces of the fin and sub-fin with a dopant media comprising an amphoteric dopant. The method further includes thermally diffusing an amphoteric dopant from the dopant medium into the fins and sub-fins. The method includes placing a lateral spacer adjacent the mask to cover a tip portion of the fin and a sub-tip portion of the sub-fin, both comprising an amphoteric dopant. It further comprises the step of forming. The method further includes forming source and drain regions at the ends of the fin not covered by the mask or lateral spacer. The method further includes replacing the mask with a gate stack. The method further includes forming contact metallization in the source and drain regions.

In at least some of the third embodiments, contacting the exposed surfaces of the fin and sub-fin to the dopant medium comprises a dopant source film comprising an amphoteric dopant in mobile form. ), over the sidewall surfaces of the fin, and capping the dopant source film with a second film. The method further includes stripping off the dopant source film and the capping film selectively to the III-V heterostructure fin after thermally diffusing the amphoteric dopant.

In at least some of the third embodiments, contacting the exposed surfaces of the fin and sub-fin to the dopant medium comprises an amphoteric dopant in a mobile form above sidewall surfaces of the fin and sub-fin. The method further includes depositing a dopant source film, and depositing a capping film over the dopant source film. The method further comprises stripping off the capping film selectively to the III-V heterostructure fin after thermally diffusing the amphoteric dopant.

In at least some of the third embodiments, contacting the exposed surfaces of the fin and sub-fin to the dopant medium comprises the fin and sub-fin with a liquid comprising amphoteric dopant moieties. wetting the sidewall surfaces of the , and depositing a capping film over the amphoteric dopant moieties bound to the sidewall surfaces. The method further comprises stripping the capping film from the III-V heterostructure fin after thermally diffusing the amphoteric dopant.

In at least some of the third embodiments, forming the III-V heterostructure fin comprises sidewalls of the n-type III-V compound semiconductor material and the p-type III-V compound semiconductor material. and recessing an amorphous isolation material from around the sidewalls of the heterostructure fin to expose at least a portion.

In at least some of the third embodiments, forming the source and drain regions comprises recess etching an n-type group III-V compound semiconductor material not covered by a mask or lateral spacer, and both and epitaxially growing a narrow band gap n-type III-V compound semiconductor material further comprising a donor dopant other than the sexual dopant.

In at least some of the third embodiments, the n-type Group III-V material comprises two or more of In, Ga, and As, and the amphoteric dopant is Si.

In at least some of the third embodiments, the method includes contacting exposed surfaces of the fin and sub-fin not covered by a mask or lateral spacer with a dopant medium comprising an amphoteric dopant, and a source; and thermally diffusing the amphoteric dopant from the dopant medium into the fin and sub-fin prior to forming the drain regions.

However, the above embodiments are not limited in this respect, and in various implementations, the above embodiments may implement only a subset of these features, implement a different order of these features, or implement different combinations of these features. and/or implementing additional features other than those explicitly recited. Accordingly, the scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which these claims qualify.

Claims (20)

A transistor structure comprising:
a III-V heterostructure disposed on the substrate, the heterostructure comprising a first III-V compound semiconductor material in contact with a second III-V compound semiconductor material;
a gate stack disposed over a channel region of said first III-V compound semiconductor material, said gate stack comprising a gate electrode separated from said channel region by a gate dielectric; and
a pair of source/drain regions electrically coupled to opposite ends of the channel region through a tip region in the first III-V compound semiconductor material, the tip region being the second III-V region contacting a sub-tip region of a group compound semiconductor material, said tip region and said sub-tip region both comprising an amphoteric dopant, said amphoteric dopant comprising said first III -activated as a donor in the group V compound semiconductor material and as an acceptor in the second group III-V compound semiconductor material. According to claim 1,
A majority charge carrier in the channel region is an electron,
wherein the second III-V compound semiconductor material has a p-type conductivity. 2. The method of claim 1, wherein the sub-tip region of the second III-V compound semiconductor material comprises the same concentration of the amphoteric dopant as the tip region, the amphoteric dopant comprising the first and second III- A transistor structure for reinforcing a pn junction in a heterojunction of group V compound semiconductor materials. The transistor structure of claim 1 , wherein the first III-V material is selected from the group consisting of InGaAs, InAs, GaAs, InP, and InSb. 5. The transistor structure of claim 4, wherein the second group III-V material is selected from the group consisting of AlSb, InP, GaSb, GaAlSb, GaAsSb, InAlAs, GaAs, and AlGaAs. The transistor structure of claim 1 , wherein the amphoteric dopant is selected from the group consisting of Si, C, Ge, Sn, Te, Se, and O. According to claim 1,
the first III-V material comprises at least two of In, Ga, and As;
wherein the amphoteric dopant is Si or C. According to claim 1,
The pair of source/drain regions is in contact with the tip region and is in contact with a sub-source/drain region of the second III-V compound semiconductor material below the source or drain region. further comprising a group III-V compound semiconductor material comprising:
and the sub-source/drain regions also include the amphoteric dopant. 9. The method of claim 8, wherein the sub-source/drain region comprises the same concentration of the amphoteric dopant as the tip region, the amphoteric dopant between the source and the sub-source region, or between the drain and the reinforcing a pn junction at the heterojunction of the third and second group III-V compound semiconductor materials between sub-drain regions. A CMOS integrated circuit (IC) comprising:
silicon substrate;
an n-type III-V-channel fin field effect transistor (finFET) structure disposed over a first region of the substrate, the n-type III-V-channel finFET structure comprising:
a group III-V heterostructure fin disposed on the substrate, the heterostructure fin being a first n-type group III-V contacting sub-fin of a p-type group III-V compound semiconductor material comprising fins of compound semiconductor material;
a gate stack disposed over a channel region of the fin of the first n-type III-V compound semiconductor material, the gate stack including a gate electrode separated from the channel region by a gate dielectric; and
a pair comprising a second n-type III-V compound semiconductor material electrically coupled to opposite ends of the channel region through a tip region of the fin of the first n-type III-V compound semiconductor material source/drain regions of - wherein the tip region comprises an amphoteric dopant and the tip region is disposed on a sub-tip region of the sub-fin also comprising the amphoteric dopant, the amphoteric dopant comprising the activated as a donor in the first n-type III-V compound semiconductor material and as an acceptor in the p-type III-V compound semiconductor material; and
and a p-type silicon-channeled FET disposed over a second region of the substrate. 11. The method of claim 10,
The amphoteric dopant is at least one of Si, C, Ge, Sn, Te, Se, and O;
wherein the tip region and the sub-tip region contain the same concentration of the amphoteric dopant. 11. The method of claim 10, wherein the second n-type group III-V compound semiconductor material is in contact with sub-source/drain regions of the p-type group III-V compound semiconductor material;
wherein the sub-source/drain region also includes the same concentration of the amphoteric dopant as the tip region. A method for manufacturing a III-V-channel type fin field effect transistor (finFET), comprising:
forming a group III-V heterostructure fin disposed on a substrate, wherein the heterostructure fin is formed of an n-type group III-V compound semiconductor material in contact with a sub-fin of the p-type group III-V compound semiconductor material. with pins -;
forming a mask over the channel region of the fin of the n-type III-V compound semiconductor material;
contacting the exposed surfaces of the fin and the sub-fin of the n-type group III-V compound semiconductor material not covered by the mask with a dopant media comprising an amphoteric dopant - the both sides a sex dopant is activated as a donor in the n-type III-V compound semiconductor material and as an acceptor in the p-type III-V compound semiconductor material;
thermally diffusing the amphoteric dopant from the dopant medium into the fin and sub-fin of the n-type Group III-V compound semiconductor material;
a tip portion of the fin and a sub-tip portion of the sub-fin, both comprising the amphoteric dopant, of the n-type group III-V compound semiconductor material. self-alignedly forming a lateral spacer adjacent to the mask;
self-aligning source and drain regions at the ends of the fin of the n-type group III-V compound semiconductor material not covered by the mask or lateral spacer; and
replacing the mask with a gate stack, the gate stack comprising a gate electrode separated from the channel region by a gate dielectric;
A method comprising 14. The method of claim 13, wherein contacting the exposed surfaces of the fin and the sub-fin of the n-type group III-V compound semiconductor material to the dopant medium comprises:
depositing a dopant source film comprising the amphoteric dopant in mobile form over sidewall surfaces of the fin of the n-type Group III-V compound semiconductor material; and
further comprising capping the dopant source film with a second film;
The method further comprises stripping off the dopant source film and the capping film selectively with respect to the III-V heterostructure fin after thermally diffusing the amphoteric dopant. How to. 14. The method of claim 13,
Contacting the exposed surfaces of the fin and the sub-fin of the n-type Group III-V compound semiconductor material to the dopant medium comprises:
depositing a dopant source film comprising said amphoteric dopant in mobile form over sidewall surfaces of said fin and said sub-fin of said n-type group III-V compound semiconductor material; and
further comprising depositing a capping film over the dopant source film;
wherein the method further comprises stripping off the capping film selectively to the III-V heterostructure fin after thermally diffusing the amphoteric dopant. 14. The method of claim 13,
Contacting the exposed surfaces of the fin and the sub-fin of the n-type Group III-V compound semiconductor material to the dopant medium comprises:
wetting sidewall surfaces of the fin and sub-fin of the n-type Group III-V compound semiconductor material with a liquid comprising amphoteric dopant moieties; and
further comprising depositing a capping film over the amphoteric dopant moieties bound to the sidewall surfaces;
wherein the method further comprises stripping the capping film from the group III-V heterostructure fin after thermally diffusing the amphoteric dopant. 14. The method of claim 13, wherein forming the group III-V heterostructure fin comprises:
an amorphous isolation material from around the sidewalls of the heterostructure fin to expose sidewalls of the n-type group III-V compound semiconductor material and at least a portion of the p-type group III-V compound semiconductor material Further comprising the step of recessing the method. 14. The method of claim 13, wherein forming the source and drain regions in a self-aligned manner comprises:
recess etching the n-type group III-V compound semiconductor material not covered by the mask or lateral spacers; and
and epitaxially growing a narrow band gap n-type Group III-V compound semiconductor material further comprising a donor dopant other than the amphoteric dopant. 14. The method of claim 13,
the n-type group III-V material comprises at least two of In, Ga, and As;
wherein the amphoteric dopant is Si or C. 14. The dopant medium of claim 13, wherein the exposed surfaces of the fin and the sub-fin of the n-type group III-V compound semiconductor material not covered by the mask or the lateral spacers are covered with the amphoteric dopant. and thermally diffusing the amphoteric dopant from the dopant medium into the fin and sub-fin of the n-type Group III-V compound semiconductor material prior to forming the source and drain regions. further comprising a method.

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