DE112008001473B4 - Zwischenspeicherung eines Mikrocodierungsemulationsspeichers - Google Patents

Zwischenspeicherung eines Mikrocodierungsemulationsspeichers Download PDF

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Publication number
DE112008001473B4
DE112008001473B4 DE112008001473.6T DE112008001473T DE112008001473B4 DE 112008001473 B4 DE112008001473 B4 DE 112008001473B4 DE 112008001473 T DE112008001473 T DE 112008001473T DE 112008001473 B4 DE112008001473 B4 DE 112008001473B4
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Prior art keywords
area
cache memory
level
cache
microcoding
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DE112008001473.6T
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German (de)
English (en)
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DE112008001473T5 (de
Inventor
Gary Lauterbach
Bruce R. Holloway
Michael Gerard Butler
Sean Lie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MAGNUSON RESEARCH LLC, WILMINGTON, US
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Advanced Micro Devices Inc
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Publication of DE112008001473T5 publication Critical patent/DE112008001473T5/de
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE112008001473.6T 2007-05-29 2008-05-28 Zwischenspeicherung eines Mikrocodierungsemulationsspeichers Active DE112008001473B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/754,589 US7734873B2 (en) 2007-05-29 2007-05-29 Caching of microcode emulation memory
US11/754,589 2007-05-29
PCT/US2008/006746 WO2008153799A1 (en) 2007-05-29 2008-05-28 Caching of microcode emulation memory

Publications (2)

Publication Number Publication Date
DE112008001473T5 DE112008001473T5 (de) 2010-07-01
DE112008001473B4 true DE112008001473B4 (de) 2021-08-26

Family

ID=39708011

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112008001473.6T Active DE112008001473B4 (de) 2007-05-29 2008-05-28 Zwischenspeicherung eines Mikrocodierungsemulationsspeichers

Country Status (8)

Country Link
US (1) US7734873B2 (enExample)
JP (1) JP5496085B2 (enExample)
KR (1) KR101503865B1 (enExample)
CN (1) CN101707881B (enExample)
DE (1) DE112008001473B4 (enExample)
GB (1) GB2462556B (enExample)
TW (1) TWI457826B (enExample)
WO (1) WO2008153799A1 (enExample)

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US8296528B2 (en) * 2008-11-03 2012-10-23 Intel Corporation Methods and systems for microcode patching
US20120017039A1 (en) * 2010-07-16 2012-01-19 Plx Technology, Inc. Caching using virtual memory
US9529729B2 (en) * 2010-11-16 2016-12-27 International Business Machines Corporation Location of memory management translations in an emulated processor
US9251093B2 (en) 2011-05-19 2016-02-02 International Business Machines Corporation Managing the translation look-aside buffer (TLB) of an emulated machine
CN106469020B (zh) * 2015-08-19 2019-08-09 旺宏电子股份有限公司 高速缓存元件与控制方法及其应用系统
US10884751B2 (en) 2018-07-13 2021-01-05 Advanced Micro Devices, Inc. Method and apparatus for virtualizing the micro-op cache
US11016763B2 (en) 2019-03-08 2021-05-25 Advanced Micro Devices, Inc. Implementing a micro-operation cache with compaction
US11720360B2 (en) 2020-09-11 2023-08-08 Apple Inc. DSB operation with excluded region
CN119025052B (zh) * 2024-10-29 2025-02-28 上海芯力基半导体有限公司 一种处理器及其内存读取方法

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US5905997A (en) 1994-04-29 1999-05-18 Amd Inc. Set-associative cache memory utilizing a single bank of physical memory
WO1999060480A1 (en) 1998-05-15 1999-11-25 Richard Rubinstein Shared, reconfigurable cache memory execution subsystem

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JPH0738175B2 (ja) * 1987-10-20 1995-04-26 富士通株式会社 仮想記憶装置のデータ保護検査方法
US5278973A (en) * 1989-03-27 1994-01-11 Unisys Corporation Dual operating system computer
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US5826052A (en) * 1994-04-29 1998-10-20 Advanced Micro Devices, Inc. Method and apparatus for concurrent access to multiple physical caches
JP3177117B2 (ja) * 1994-05-11 2001-06-18 インターナショナル・ビジネス・マシーンズ・コーポレ−ション 複数のノード内の制御コードを更新する方法および装置
JPH07311752A (ja) * 1994-05-11 1995-11-28 Internatl Business Mach Corp <Ibm> 分散データ処理システム及び初期プログラムロード方法
US5926642A (en) 1995-10-06 1999-07-20 Advanced Micro Devices, Inc. RISC86 instruction set
US5864689A (en) * 1995-12-05 1999-01-26 Advanced Micro Devices, Inc. Microprocessor configured to selectively invoke a microcode DSP function or a program subroutine in response to a target address value of branch instruction
US5950012A (en) * 1996-03-08 1999-09-07 Texas Instruments Incorporated Single chip microprocessor circuits, systems, and methods for self-loading patch micro-operation codes and patch microinstruction codes
US5796972A (en) * 1997-01-14 1998-08-18 Unisys Corporation Method and apparatus for performing microcode paging during instruction execution in an instruction processor
US6141740A (en) * 1997-03-03 2000-10-31 Advanced Micro Devices, Inc. Apparatus and method for microcode patching for generating a next address
US5889978A (en) * 1997-04-18 1999-03-30 Intel Corporation Emulation of interrupt control mechanism in a multiprocessor system
JP2000194602A (ja) * 1998-12-28 2000-07-14 Nec Corp 情報処理装置、マイクロプロセッサ及び外部キャッシュメモリの制御方法
US6745306B1 (en) * 1999-07-29 2004-06-01 Microsoft Corporation Method and system for restricting the load of physical address translations of virtual addresses
US6457100B1 (en) * 1999-09-15 2002-09-24 International Business Machines Corporation Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls
US6397301B1 (en) * 1999-12-29 2002-05-28 Intel Corporation Preventing access to secure area of a cache
US6643800B1 (en) * 2000-02-02 2003-11-04 Hewlett-Packard Development Company, L.P. Method and apparatus for testing microarchitectural features by using tests written in microcode
US6804772B2 (en) * 2000-06-12 2004-10-12 Broadcom Corporation Dynamic field patchable microarchitecture
EP1182570A3 (en) * 2000-08-21 2004-08-04 Texas Instruments Incorporated TLB with resource ID field
US6754765B1 (en) * 2001-05-14 2004-06-22 Integrated Memory Logic, Inc. Flash memory controller with updateable microcode
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US7797492B2 (en) * 2004-02-20 2010-09-14 Anoop Mukker Method and apparatus for dedicating cache entries to certain streams for performance optimization
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Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US5905997A (en) 1994-04-29 1999-05-18 Amd Inc. Set-associative cache memory utilizing a single bank of physical memory
WO1999060480A1 (en) 1998-05-15 1999-11-25 Richard Rubinstein Shared, reconfigurable cache memory execution subsystem

Also Published As

Publication number Publication date
US20080301364A1 (en) 2008-12-04
GB2462556B (en) 2012-05-30
GB0920954D0 (en) 2010-01-13
KR101503865B1 (ko) 2015-03-24
WO2008153799A1 (en) 2008-12-18
TWI457826B (zh) 2014-10-21
CN101707881A (zh) 2010-05-12
CN101707881B (zh) 2016-06-15
KR20100022483A (ko) 2010-03-02
US7734873B2 (en) 2010-06-08
TW200905555A (en) 2009-02-01
GB2462556A (en) 2010-02-17
JP2010529534A (ja) 2010-08-26
DE112008001473T5 (de) 2010-07-01
JP5496085B2 (ja) 2014-05-21

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R081 Change of applicant/patentee

Owner name: ONESTA IP, LLC (N.D.GES.D.STAATES DELAWARE), W, US

Free format text: FORMER OWNER: ADVANCED MICRO DEVICES, INC., SUNNYVALE, CALIF., US

Owner name: MAGNUSON RESEARCH LLC, WILMINGTON, US

Free format text: FORMER OWNER: ADVANCED MICRO DEVICES, INC., SUNNYVALE, CALIF., US

R082 Change of representative

Representative=s name: PETERREINS SCHLEY PATENT- UND RECHTSANWAELTE P, DE

Representative=s name: BARDEHLE PAGENBERG PARTNERSCHAFT MBB PATENTANW, DE

R081 Change of applicant/patentee

Owner name: MAGNUSON RESEARCH LLC, WILMINGTON, US

Free format text: FORMER OWNER: ONESTA IP, LLC (N.D.GES.D.STAATES DELAWARE), WAYNE, PA, US

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Representative=s name: BARDEHLE PAGENBERG PARTNERSCHAFT MBB PATENTANW, DE