KR101503865B1 - 마이크로코드 에뮬레이션 메모리의 캐싱 - Google Patents

마이크로코드 에뮬레이션 메모리의 캐싱 Download PDF

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KR101503865B1
KR101503865B1 KR1020097026820A KR20097026820A KR101503865B1 KR 101503865 B1 KR101503865 B1 KR 101503865B1 KR 1020097026820 A KR1020097026820 A KR 1020097026820A KR 20097026820 A KR20097026820 A KR 20097026820A KR 101503865 B1 KR101503865 B1 KR 101503865B1
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cache
level
microcode
instructions
instruction
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KR20100022483A (ko
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게리 라우터바흐
브루스 알. 홀로웨이
마이클 제라드 버틀러
션 리에
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020097026820A 2007-05-29 2008-05-28 마이크로코드 에뮬레이션 메모리의 캐싱 Expired - Fee Related KR101503865B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/754,589 US7734873B2 (en) 2007-05-29 2007-05-29 Caching of microcode emulation memory
US11/754,589 2007-05-29
PCT/US2008/006746 WO2008153799A1 (en) 2007-05-29 2008-05-28 Caching of microcode emulation memory

Publications (2)

Publication Number Publication Date
KR20100022483A KR20100022483A (ko) 2010-03-02
KR101503865B1 true KR101503865B1 (ko) 2015-03-24

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KR1020097026820A Expired - Fee Related KR101503865B1 (ko) 2007-05-29 2008-05-28 마이크로코드 에뮬레이션 메모리의 캐싱

Country Status (8)

Country Link
US (1) US7734873B2 (enExample)
JP (1) JP5496085B2 (enExample)
KR (1) KR101503865B1 (enExample)
CN (1) CN101707881B (enExample)
DE (1) DE112008001473B4 (enExample)
GB (1) GB2462556B (enExample)
TW (1) TWI457826B (enExample)
WO (1) WO2008153799A1 (enExample)

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US8296528B2 (en) * 2008-11-03 2012-10-23 Intel Corporation Methods and systems for microcode patching
US20120017039A1 (en) * 2010-07-16 2012-01-19 Plx Technology, Inc. Caching using virtual memory
US9529729B2 (en) * 2010-11-16 2016-12-27 International Business Machines Corporation Location of memory management translations in an emulated processor
WO2012156850A1 (en) * 2011-05-19 2012-11-22 International Business Machines Corporation Managing the translation look-aside buffer (tlb) of an emulated machine
CN106469020B (zh) * 2015-08-19 2019-08-09 旺宏电子股份有限公司 高速缓存元件与控制方法及其应用系统
US10884751B2 (en) 2018-07-13 2021-01-05 Advanced Micro Devices, Inc. Method and apparatus for virtualizing the micro-op cache
US11016763B2 (en) 2019-03-08 2021-05-25 Advanced Micro Devices, Inc. Implementing a micro-operation cache with compaction
US11720360B2 (en) 2020-09-11 2023-08-08 Apple Inc. DSB operation with excluded region
CN119025052B (zh) * 2024-10-29 2025-02-28 上海芯力基半导体有限公司 一种处理器及其内存读取方法

Citations (1)

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US5826052A (en) * 1994-04-29 1998-10-20 Advanced Micro Devices, Inc. Method and apparatus for concurrent access to multiple physical caches

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JPH07311752A (ja) 1994-05-11 1995-11-28 Internatl Business Mach Corp <Ibm> 分散データ処理システム及び初期プログラムロード方法
JP3177117B2 (ja) 1994-05-11 2001-06-18 インターナショナル・ビジネス・マシーンズ・コーポレ−ション 複数のノード内の制御コードを更新する方法および装置
US5926642A (en) 1995-10-06 1999-07-20 Advanced Micro Devices, Inc. RISC86 instruction set
US5864689A (en) 1995-12-05 1999-01-26 Advanced Micro Devices, Inc. Microprocessor configured to selectively invoke a microcode DSP function or a program subroutine in response to a target address value of branch instruction
US5950012A (en) * 1996-03-08 1999-09-07 Texas Instruments Incorporated Single chip microprocessor circuits, systems, and methods for self-loading patch micro-operation codes and patch microinstruction codes
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Also Published As

Publication number Publication date
WO2008153799A1 (en) 2008-12-18
GB2462556A (en) 2010-02-17
CN101707881B (zh) 2016-06-15
TW200905555A (en) 2009-02-01
KR20100022483A (ko) 2010-03-02
JP5496085B2 (ja) 2014-05-21
DE112008001473T5 (de) 2010-07-01
US20080301364A1 (en) 2008-12-04
GB0920954D0 (en) 2010-01-13
TWI457826B (zh) 2014-10-21
CN101707881A (zh) 2010-05-12
DE112008001473B4 (de) 2021-08-26
US7734873B2 (en) 2010-06-08
JP2010529534A (ja) 2010-08-26
GB2462556B (en) 2012-05-30

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