DE102020108092B4 - Halbleitervorrichtungen mit Dummy-Kanalstrukturen in Durchgangsverdrahtungsregion - Google Patents

Halbleitervorrichtungen mit Dummy-Kanalstrukturen in Durchgangsverdrahtungsregion

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Publication number
DE102020108092B4
DE102020108092B4 DE102020108092.1A DE102020108092A DE102020108092B4 DE 102020108092 B4 DE102020108092 B4 DE 102020108092B4 DE 102020108092 A DE102020108092 A DE 102020108092A DE 102020108092 B4 DE102020108092 B4 DE 102020108092B4
Authority
DE
Germany
Prior art keywords
region
channel structures
substrate
dch
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE102020108092.1A
Other languages
German (de)
English (en)
Other versions
DE102020108092A1 (de
Inventor
Joowon Park
Woongseop Lee
Eiwhan Jung
Jisung Cheon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102020108092A1 publication Critical patent/DE102020108092A1/de
Application granted granted Critical
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Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE102020108092.1A 2019-08-20 2020-03-24 Halbleitervorrichtungen mit Dummy-Kanalstrukturen in Durchgangsverdrahtungsregion Active DE102020108092B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020190101591A KR102729073B1 (ko) 2019-08-20 2019-08-20 반도체 장치
KR10-2019-0101591 2019-08-20

Publications (2)

Publication Number Publication Date
DE102020108092A1 DE102020108092A1 (de) 2021-02-25
DE102020108092B4 true DE102020108092B4 (de) 2026-08-06

Family

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Family Applications (1)

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DE102020108092.1A Active DE102020108092B4 (de) 2019-08-20 2020-03-24 Halbleitervorrichtungen mit Dummy-Kanalstrukturen in Durchgangsverdrahtungsregion

Country Status (6)

Country Link
US (2) US11398495B2 (enExample)
JP (1) JP7631652B2 (enExample)
KR (1) KR102729073B1 (enExample)
CN (1) CN112420713B (enExample)
DE (1) DE102020108092B4 (enExample)
SG (1) SG10202003704XA (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102790612B1 (ko) * 2020-06-23 2025-04-08 삼성전자주식회사 반도체 장치
KR102942729B1 (ko) * 2021-05-21 2026-03-24 삼성전자주식회사 반도체 장치 및 이를 포함하는 전자 시스템
KR102969218B1 (ko) 2021-06-01 2026-05-22 삼성전자주식회사 반도체 장치 및 이를 포함하는 전자 시스템
US12094814B2 (en) * 2021-06-17 2024-09-17 Macronix International Co., Ltd. Memory device and flash memory device with improved support for staircase regions
KR102972910B1 (ko) * 2021-07-07 2026-06-05 삼성전자주식회사 3차원 반도체 메모리 장치 및 이를 포함하는 전자 시스템
KR102942720B1 (ko) * 2021-08-23 2026-03-23 삼성전자주식회사 3차원 반도체 메모리 장치 및 이를 포함하는 전자 시스템
KR20230038368A (ko) 2021-09-10 2023-03-20 삼성전자주식회사 반도체 장치 및 이를 포함하는 전자 시스템
JP2023044480A (ja) 2021-09-17 2023-03-30 キオクシア株式会社 半導体装置およびその製造方法
JP7755474B2 (ja) * 2021-12-10 2025-10-16 キオクシア株式会社 半導体装置およびその製造方法
US12615827B2 (en) * 2022-04-04 2026-04-28 Micron Technology, Inc. Memory circuitry comprising strings of memory cells
KR20240017514A (ko) 2022-08-01 2024-02-08 에스케이하이닉스 주식회사 반도체 장치의 제조 방법
KR20240030107A (ko) * 2022-08-29 2024-03-07 삼성전자주식회사 반도체 장치 및 이를 포함하는 전자 시스템
JP2024044126A (ja) * 2022-09-20 2024-04-02 キオクシア株式会社 半導体記憶装置および半導体装置の製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170179026A1 (en) 2015-12-22 2017-06-22 Sandisk Technologies Llc Through-memory-level via structures for a three-dimensional memory device
US20170352678A1 (en) 2016-06-07 2017-12-07 Sandisk Technologies Llc Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof
US20170358593A1 (en) 2016-06-08 2017-12-14 Sandisk Technologies Llc Within-array through-memory-level via structures and method of making thereof
US20170373084A1 (en) 2016-06-27 2017-12-28 Samsung Electronics Co., Ltd. Memory device having vertical structure
US20180047744A1 (en) 2016-08-12 2018-02-15 Toshiba Memory Corporation Semiconductor memory device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101303574B1 (ko) 2011-06-10 2013-09-09 정영교 데이터 구조로부터 표를 생성하는 방법 및 하나 이상의 셀에서 표를 생성하는 방법
US20150371925A1 (en) 2014-06-20 2015-12-24 Intel Corporation Through array routing for non-volatile memory
KR102378820B1 (ko) * 2015-08-07 2022-03-28 삼성전자주식회사 메모리 장치
US10269620B2 (en) 2016-02-16 2019-04-23 Sandisk Technologies Llc Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof
KR102634947B1 (ko) * 2016-08-18 2024-02-07 삼성전자주식회사 수직형 메모리 장치 및 그 제조 방법
KR102609348B1 (ko) * 2016-10-26 2023-12-06 삼성전자주식회사 반도체 장치 및 그 제조 방법
WO2018161836A1 (en) 2017-03-08 2018-09-13 Yangtze Memory Technologies Co., Ltd. Through array contact structure of three-dimensional memory device
JP2018157103A (ja) 2017-03-17 2018-10-04 東芝メモリ株式会社 記憶措置
KR102344862B1 (ko) 2017-05-17 2021-12-29 삼성전자주식회사 수직형 반도체 소자
KR102385566B1 (ko) * 2017-08-30 2022-04-12 삼성전자주식회사 수직형 메모리 장치
JP6980518B2 (ja) * 2017-12-27 2021-12-15 キオクシア株式会社 半導体記憶装置
WO2020073262A1 (en) 2018-10-11 2020-04-16 Yangtze Memory Technologies Co., Ltd. Vertical memory devices
KR102824041B1 (ko) * 2020-02-19 2025-06-23 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치의 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170179026A1 (en) 2015-12-22 2017-06-22 Sandisk Technologies Llc Through-memory-level via structures for a three-dimensional memory device
US20170352678A1 (en) 2016-06-07 2017-12-07 Sandisk Technologies Llc Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof
US20170358593A1 (en) 2016-06-08 2017-12-14 Sandisk Technologies Llc Within-array through-memory-level via structures and method of making thereof
US20170373084A1 (en) 2016-06-27 2017-12-28 Samsung Electronics Co., Ltd. Memory device having vertical structure
US20180047744A1 (en) 2016-08-12 2018-02-15 Toshiba Memory Corporation Semiconductor memory device

Also Published As

Publication number Publication date
US12507410B2 (en) 2025-12-23
CN112420713B (zh) 2025-04-29
US20210057444A1 (en) 2021-02-25
DE102020108092A1 (de) 2021-02-25
US20220328522A1 (en) 2022-10-13
KR102729073B1 (ko) 2024-11-14
US11398495B2 (en) 2022-07-26
CN112420713A (zh) 2021-02-26
KR20210022797A (ko) 2021-03-04
JP2021034720A (ja) 2021-03-01
JP7631652B2 (ja) 2025-02-19
SG10202003704XA (en) 2021-03-30

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