JP7631652B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
JP7631652B2
JP7631652B2 JP2020112564A JP2020112564A JP7631652B2 JP 7631652 B2 JP7631652 B2 JP 7631652B2 JP 2020112564 A JP2020112564 A JP 2020112564A JP 2020112564 A JP2020112564 A JP 2020112564A JP 7631652 B2 JP7631652 B2 JP 7631652B2
Authority
JP
Japan
Prior art keywords
region
channel structure
semiconductor device
substrate
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2020112564A
Other languages
English (en)
Japanese (ja)
Other versions
JP2021034720A5 (enExample
JP2021034720A (ja
Inventor
株院 朴
雄燮 李
義完 鄭
志成 千
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2021034720A publication Critical patent/JP2021034720A/ja
Publication of JP2021034720A5 publication Critical patent/JP2021034720A5/ja
Application granted granted Critical
Publication of JP7631652B2 publication Critical patent/JP7631652B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2020112564A 2019-08-20 2020-06-30 半導体装置 Active JP7631652B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2019-0101591 2019-08-20
KR1020190101591A KR102729073B1 (ko) 2019-08-20 2019-08-20 반도체 장치

Publications (3)

Publication Number Publication Date
JP2021034720A JP2021034720A (ja) 2021-03-01
JP2021034720A5 JP2021034720A5 (enExample) 2023-07-04
JP7631652B2 true JP7631652B2 (ja) 2025-02-19

Family

ID=74495874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020112564A Active JP7631652B2 (ja) 2019-08-20 2020-06-30 半導体装置

Country Status (6)

Country Link
US (2) US11398495B2 (enExample)
JP (1) JP7631652B2 (enExample)
KR (1) KR102729073B1 (enExample)
CN (1) CN112420713B (enExample)
DE (1) DE102020108092A1 (enExample)
SG (1) SG10202003704XA (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102790612B1 (ko) * 2020-06-23 2025-04-08 삼성전자주식회사 반도체 장치
KR20220162471A (ko) 2021-06-01 2022-12-08 삼성전자주식회사 반도체 장치 및 이를 포함하는 전자 시스템
US12094814B2 (en) * 2021-06-17 2024-09-17 Macronix International Co., Ltd. Memory device and flash memory device with improved support for staircase regions
KR20230008958A (ko) * 2021-07-07 2023-01-17 삼성전자주식회사 3차원 반도체 메모리 장치 및 이를 포함하는 전자 시스템
KR20230028975A (ko) * 2021-08-23 2023-03-03 삼성전자주식회사 3차원 반도체 메모리 장치 및 이를 포함하는 전자 시스템
KR20230038368A (ko) 2021-09-10 2023-03-20 삼성전자주식회사 반도체 장치 및 이를 포함하는 전자 시스템
JP2023044480A (ja) 2021-09-17 2023-03-30 キオクシア株式会社 半導体装置およびその製造方法
JP7755474B2 (ja) * 2021-12-10 2025-10-16 キオクシア株式会社 半導体装置およびその製造方法
KR20240030107A (ko) * 2022-08-29 2024-03-07 삼성전자주식회사 반도체 장치 및 이를 포함하는 전자 시스템

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170040337A1 (en) 2015-08-07 2017-02-09 Jong Won Kim Vertical memory devices having dummy channel regions
US20180114794A1 (en) 2016-10-26 2018-04-26 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
WO2018161836A1 (en) 2017-03-08 2018-09-13 Yangtze Memory Technologies Co., Ltd. Through array contact structure of three-dimensional memory device
JP2019117894A (ja) 2017-12-27 2019-07-18 東芝メモリ株式会社 半導体記憶装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101303574B1 (ko) 2011-06-10 2013-09-09 정영교 데이터 구조로부터 표를 생성하는 방법 및 하나 이상의 셀에서 표를 생성하는 방법
US20150371925A1 (en) 2014-06-20 2015-12-24 Intel Corporation Through array routing for non-volatile memory
US10381371B2 (en) * 2015-12-22 2019-08-13 Sandisk Technologies Llc Through-memory-level via structures for a three-dimensional memory device
US10269620B2 (en) 2016-02-16 2019-04-23 Sandisk Technologies Llc Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof
US10256248B2 (en) 2016-06-07 2019-04-09 Sandisk Technologies Llc Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof
US10249640B2 (en) 2016-06-08 2019-04-02 Sandisk Technologies Llc Within-array through-memory-level via structures and method of making thereof
KR20180001296A (ko) 2016-06-27 2018-01-04 삼성전자주식회사 수직형 구조를 가지는 메모리 장치
US10276585B2 (en) 2016-08-12 2019-04-30 Toshiba Memory Corporation Semiconductor memory device
KR102634947B1 (ko) * 2016-08-18 2024-02-07 삼성전자주식회사 수직형 메모리 장치 및 그 제조 방법
JP2018157103A (ja) 2017-03-17 2018-10-04 東芝メモリ株式会社 記憶措置
KR102824041B1 (ko) * 2020-02-19 2025-06-23 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치의 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170040337A1 (en) 2015-08-07 2017-02-09 Jong Won Kim Vertical memory devices having dummy channel regions
US20180114794A1 (en) 2016-10-26 2018-04-26 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
WO2018161836A1 (en) 2017-03-08 2018-09-13 Yangtze Memory Technologies Co., Ltd. Through array contact structure of three-dimensional memory device
JP2019117894A (ja) 2017-12-27 2019-07-18 東芝メモリ株式会社 半導体記憶装置

Also Published As

Publication number Publication date
SG10202003704XA (en) 2021-03-30
KR20210022797A (ko) 2021-03-04
US20210057444A1 (en) 2021-02-25
US20220328522A1 (en) 2022-10-13
CN112420713A (zh) 2021-02-26
CN112420713B (zh) 2025-04-29
DE102020108092A1 (de) 2021-02-25
US11398495B2 (en) 2022-07-26
KR102729073B1 (ko) 2024-11-14
JP2021034720A (ja) 2021-03-01

Similar Documents

Publication Publication Date Title
JP7631652B2 (ja) 半導体装置
US10672781B2 (en) Semiconductor device
US11444098B2 (en) Vertical non-volatile memory devices and methods of programming the same
US12268004B2 (en) Semiconductor devices with string select channel layer
US20190319038A1 (en) Semiconductor devices
US11557603B2 (en) Semiconductor devices
CN110808248A (zh) 包括贯穿布线区域的半导体器件
KR102450571B1 (ko) 반도체 장치
CN108573979A (zh) 半导体器件
KR20190140253A (ko) 반도체 장치 및 반도체 장치의 제조 방법
KR20190092808A (ko) 반도체 장치
KR102839997B1 (ko) 반도체 소자
JP7680120B2 (ja) 半導体装置
US11930641B2 (en) Semiconductor devices
US9871055B1 (en) Vertical-type memory device
US12114497B2 (en) Semiconductor devices
CN110473874B (zh) 半导体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230626

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20230626

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20240711

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20240716

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20241010

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20250107

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20250117

R150 Certificate of patent or registration of utility model

Ref document number: 7631652

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150