DE102014222203B3 - Check for marginal damage - Google Patents

Abstract

A power semiconductor device (1) is described. The semiconductor component (1) comprises a semiconductor body (11), wherein the semiconductor body (11) comprises an active semiconductor region (111) and an edge semiconductor region (112) surrounding the active semiconductor region (111), the active semiconductor region (111) having an active surface region (11). 121) and the edge semiconductor region (112) has an edge surface region (122). The semiconductor device (1) further comprises a test structure (13) for non-contact testing of the edge semiconductor region (112), the test structure (13) comprising an electrically conductive path (131) disposed on the edge surface region (122), and wherein the test structure (13) is adapted to extract energy from a spaced generated radio frequency electromagnetic test field (5).

Description

The present description relates to embodiments of power semiconductor devices, methods of manufacturing a power semiconductor device, devices for non-contact testing of a power semiconductor device, and methods of contactless testing of a power semiconductor device. For example, the present description relates to embodiments of IGBTs, MOSFETs, diodes, and the like, as well as to embodiments of methods of making and testing such devices and embodiments of devices for testing such devices. More particularly, the present description relates to embodiments of a power semiconductor device having means for allowing contactless testing of an edge semiconductor region of the power semiconductor device

BACKGROUND

Many functions in modem devices used in the automotive, consumer, or industrial fields, such as the conversion of electrical energy and the driving of an electric motor or an electric machine, are based on semiconductor devices. For example, insulated gate bipolar transistors and metal oxide semiconductor field effect transistors and diodes have been used in a variety of applications including, but not limited to, switches in power supply devices and power converters.

Damage to the edge semiconductor region (also referred to as a chip edge structure or termination structure) of such a semiconductor device used in one of these exemplified applications can result in functional impairments of the semiconductor device itself or possibly malfunction or failure of the system in which the semiconductor device in question is used lead.

Therefore, it may be desirable to prevent semiconductor devices having damage in the chip edge structure from being delivered to the market.

In this connection, it is known that a semiconductor device is subjected to an optical screening before it is shipped, so that it is possible to detect damage to the chip edge structure or the termination structure of the semiconductor device, ie, that it is possible to cause damage in the semiconductor device To detect edge semiconductor region of the semiconductor devices.

However, such optical screening is a rather complex task requiring high-priced, software-based inspection tools to enable automatic detection of damage in the edge semiconductor area.

From the CA 2 409 435 A1 For example, a method for contactless testing of logic integrated circuits is known.

DESCRIPTION

It is a technical object to provide means that allow a little complex verification of a peripheral semiconductor region of a semiconductor device.

The subjects of the two independent claims 1 and 18 are proposed.

According to one embodiment, a power semiconductor device is provided. The power semiconductor component comprises a semiconductor body, wherein the semiconductor body comprises an active semiconductor region and an edge semiconductor region surrounding the active semiconductor region. The active semiconductor region has an active surface area and the edge semiconductor region has an edge surface area. The power semiconductor device further includes a test structure for contactless testing of the edge semiconductor region. The test structure includes an electrically conductive path disposed on the edge surface region, the test structure configured to extract energy from a spaced-generated radio frequency electromagnetic test field.

According to a further embodiment, a method for producing a power semiconductor component is proposed. The method comprises producing a semiconductor body, wherein the semiconductor body comprises an active semiconductor region and an edge semiconductor region surrounding the active semiconductor region, and wherein the active semiconductor region has an active surface region and the edge semiconductor region has an edge surface region. The method further comprises generating a front side metallization on the active surface area, wherein the front side metallization comprises a front side metallization material. Further, the method comprises producing, on the edge surface area, a test structure for non-contact testing of the edge semiconductor region, such that the test structure is configured to extract energy from a spaced generated radio frequency electromagnetic test field. The step of producing the test structure includes creating an electrically conductive path on the edge surface area, wherein the electrically conductive path includes the same front side metallization material as the front side metallization.

An apparatus for contactless testing of an edge semiconductor region of a power semiconductor device is provided. The apparatus includes a generator configured to generate a radio frequency electromagnetic test field spaced from the power semiconductor device and direct the generated radio frequency electromagnetic test field to a test structure of the power semiconductor device. The apparatus also includes a test signal detector configured to detect a test signal that has been produced by the test structure in response to energy that extracted the test structure from the radio frequency electromagnetic test field.

Furthermore, a method for contactless testing of an edge semiconductor region of a power semiconductor component is presented. The method includes generating a radio frequency electromagnetic test field apart from the power semiconductor device and directing the generated radio frequency electromagnetic test field to a test structure of the power semiconductor device. Further, the method includes detecting a test signal that has been produced by the test structure in response to energy that extracted the test structure from the radio frequency electromagnetic test field.

The test structure is configured to produce a test signal in response to the extracted energy, wherein the produced test signal is configured to be detected by the test signal detector spaced from the power semiconductor device. The electrically conductive path surrounds the active surface area.

In the context of the present description, the power semiconductor component is also referred to simply as "semiconductor component" for short.

Due to the test structure that may be at least partially disposed on the edge surface area of the edge semiconductor region of the semiconductor device and / or included at least partially in the edge semiconductor region, damage in the edge semiconductor region (also referred to as a chip edge structure or termination structure) may be easily detected by directing said electromagnetic radio frequency test field onto the test structure.

Since the test structure is mechanically coupled to the edge semiconductor region, mechanical damage, such as fractures, fractures, crevices / cracks, craters, holes, and the like, which may or may not be included in the edge semiconductor region, may affect the layout of the test structure. Thus, the amount of energy that the test structure extracts from the spaced generated radio frequency electromagnetic test field may depend on whether the edge semiconductor region has mechanical damage or not. In other words, the amount of energy extracted from the spaced-generated radio frequency electromagnetic test field may be substantially different depending on whether the edge semiconductor region has mechanical damage or not.

Therefore, the test structure of the semiconductor device allows a less complex non-contact testing of the semiconductor device. The semiconductor device can be easily inspected before it is delivered to the market. In addition, the semiconductor device can be inspected even if it is already installed in an inverter system or used in another application.

Features of further embodiments are given in the dependent claims. The features of the further embodiments and the features of the embodiments described above may be combined to form further embodiments, as far as the said features are not expressly described as alternative to each other.

Other features and advantages will become apparent to those skilled in the art upon review of the following detailed description and upon review of the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The parts shown in the figures are not necessarily to scale; rather, the emphasis is on presenting principles of the invention. Further, like reference characters designate corresponding parts in the figures. In the figures show:

1A schematically a portion of a horizontal cross section of a semiconductor device according to one or more embodiments;

1B schematically a portion of a vertical cross-section of a semiconductor device according to one or more embodiments;

2A schematically a perspective plan view of a portion of a semiconductor device according to one or more embodiments;

2 B schematically a perspective side view of a part of a vertical Cross section of a semiconductor device according to one or more embodiments;

3 schematically an equivalent circuit of a test structure of a semiconductor device according to one or more embodiments;

4 2 schematically illustrates a block diagram of a device for contactless testing of a semiconductor device according to one or more embodiments;

5 1 schematically illustrates a circuit of a device for contactless testing of a semiconductor device according to one or more embodiments;

6 1 schematically illustrates a flowchart of a method of fabricating a semiconductor device according to one or more embodiments;

7 2 schematically illustrates a flowchart of a method of fabricating a semiconductor device according to one or more embodiments.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, in which by way of example certain embodiments are shown in accordance with which the invention may be practiced.

In this context, directional terms, such as "top", "bottom", "below", "front", "rear", "rear", "downstream", "upstream", etc., may be used with respect to the orientation of those described Drawings are used. However, because portions of the embodiments can be positioned in a variety of different orientations, this directional terminology is used for illustrative purposes only.

Reference will now be made in detail to a variety of embodiments, one or more of which are illustrated in the drawings. Each example is given for illustrative purposes. Drawings are not to scale and are for illustration purposes only. For the sake of clarity, the same elements or manufacturing steps in the different drawings are given the same reference numerals, unless otherwise stated.

The term "horizontal" as used in the present specification is intended to describe an orientation that is substantially parallel to a horizontal surface of a semiconductor substrate or a semiconductor body region. This can be, for example, the surface of a wafer or chip.

The term "vertical" as used in the present description is intended to describe an orientation which is arranged substantially perpendicular to the horizontal surface, ie parallel to the normal of the surface of the semiconductor substrate or of the semiconductor body region.

In the present specification, the first conductivity type denotes p-type doping, while the second conductivity type denotes n-type doping. Alternatively, the semiconductor devices may be formed with inverted doping so that the first conductivity type may be n-type doping and the second conductivity type may be p-type doping.

The embodiments discussed in the present specification relate to monolithically integrated power semiconductor devices having an IGBT, an RC-IGBT, a diode or a MOSFET structure.

The term "power semiconductor device" as used in the present specification is intended to refer to a single-chip semiconductor device that has high voltage blocking and switching capability and / or high current carrying and switching capability. In other words, the power semiconductor devices are high Currents, typically in the ampere range, for example up to a few hundred amperes, and / or for high voltages, typically over 200 V, still more typically 600 V and more, for example 5000 V and above are suitable for such power semiconductor devices Energy supply equipment and power converters are used.

In the context of the present specification, terms such as "in ohmic contact,""in electrical contact,""in ohmic connection," and "electrically connected" mean that between regions, sections, regions or portions of a semiconductor device or between different terminals of one or more semiconductor devices a plurality of devices or between a terminal or a metallization or an electrode and a part or region of a semiconductor device is a low-resistance electrical connection or a low-resistance current path. In the context of the present description, moreover, the term "in contact" is intended to indicate that there is a direct physical connection between two elements of the subject semiconductor device; For example, that is a transition between two elements that are in Contact each other, no intermediate elements or the like included.

1A schematically shows a section of a horizontal cross section of a semiconductor device 1 according to one or more embodiments. Corresponding to 1A , show the 1B schematically a section of a vertical cross section of the semiconductor device 1 according to one or more embodiments.

The semiconductor device 1 comprises a semiconductor body 11 , wherein the semiconductor body 11 an active semiconductor region 111 and an edge semiconductor region 112 includes. The edge semiconductor area 112 surrounds the active semiconductor region 111 and thus may be referred to as a chip edge structure or as a chip termination structure of the semiconductor device 1 to be viewed as. As further in the 1B is shown, the edge surface area 122 through a surrounding edge 123 be completed and the edge semiconductor area 112 can by surrounding sidewalls 113 to be finished.

The semiconductor device 1 can be designed to carry a load current, in particular by means of said active semiconductor region 111 , In other words, one of the semiconductor device 1 guided load current largely at least parts of the active semiconductor region 111 traverse and the semiconductor device 1 may be constructed such that the load current is substantially not the edge semiconductor region 112 crosses.

The active semiconductor area 111 has an active surface area 121 on and the edge semiconductor area 112 a marginal surface area 122 , In accordance with the embodiments described in the 1A and the 1B surrounds the edge surface area 122 completely the active surface area 121 , For example, on the active surface area 121 a front side metallization of a load contact structure (in the 1A -B not shown), wherein the front side metallization may be formed for feeding the load current into the semiconductor body 11 , in particular in the active semiconductor region 111 ,

The semiconductor device 1 includes a test structure 13 for contactless testing of the edge semiconductor region 112 , In particular, the test structure 13 be designed to inspect the semiconductor device 1 with regard to mechanical damage occurring in the peripheral semiconductor region 112 may or may not be present.

The test structure 13 includes an electrically conductive path 131 that on the edge surface area 122 is arranged. In particular, the electrically conductive path 131 in contact with the peripheral semiconductor region 112 , The test structure 13 is configured to extract energy from a spaced generated radio frequency electromagnetic test field 5 ,

The electromagnetic radio frequency test field 5 , hereinafter also referred to as "RF test field", may be spaced from the semiconductor device 1 be generated, for example, at a distance of a few centimeters or meters. For these purposes, an RF test field generator may be provided, which will be described in more detail below. As will be described in more detail below, the RF test field generator may include one or more excitation means for generating the RF test field 5 include. For some applications, it may be expedient to place at least one of these excitation means in the vicinity of the electrically conductive path 131 to be positioned, for example, at a distance of several 100 microns.

As the electrically conductive path 131 on the edge surface area 122 is arranged, is the test structure 13 mechanically to the edge semiconductor region 112 coupled. In particular, the test structure 13 at least partially an integral part of the semiconductor device 1 , in particular of said semiconductor region 112 form. Therefore, the mechanical property of the edge semiconductor region 112 the nature of the test structure 13 in particular, the layout of the electrically conductive path 131 , For example, a mechanical damage of the edge semiconductor region 112 the electrically conductive path 131 damage the path 131 has a high ohmic resistance, for example, due to an interruption of the path 131 which may have been caused by the mechanical damage.

The electrically conductive path 131 can be a closed or an almost closed path that defines the active surface area 121 at least once completely or almost completely surrounds. For example, the electrically conductive path 131 have such a course that the electrically conductive path 131 the active surface area 121 surrounds more than once, for example twice or thrice or even more frequently.

Should the edge semiconductor area 112 For example, have one or more mechanical damage, such as fractures, fractures, cracks, craters, holes and the like, so the energy generated by the test structure 13 has been extracted from the RF test field, for example, down to about zero. But if the edge semiconductor area 112 has no mechanical damage, the extracted energy can deviate significantly from zero. Therefore, the test structure 13 a little complex contactless testing of the edge semiconductor region 112 enable.

To test if the semiconductor device 1 mechanical damage within the peripheral semiconductor region 112 or not, it may be sufficient to have a physical parameter of the test structure 13 , For example, an inductance of the electrically conductive path 131 to measure, for example by means of the RF test field 5 ,

In particular, the test structure 13 configured to produce a test signal in dependence on the extracted energy such that the produced test signal is configured to be fed by a test signal detector (in the 1A -B not shown), that of the semiconductor device 1 spaced apart to be detected.

For example, that of the test structure 13 produced detectable test signal to be a light signal. For these purposes, the test structure 13 a diode (not shown), wherein the diode is electrically connected to the electrically conductive path 131 is coupled and adapted to convert the from the RF test field 5 extracted energy into a detectable light signal. For example, the presence of the light signal may be indicative of the absence of mechanical damage in the edge semiconductor region 112 may be indicative of the presence of mechanical damage in the edge semiconductor region 112 , According to another embodiment, a high light intensity or color of the light signal may be indicative of the absence of mechanical damage in the edge semiconductor region 112 and a little intense light signal or other color of the light signal may be indicative of the presence of mechanical damage in the edge semiconductor region 112 be.

According to another embodiment, that of the test structure 13 produced detectable test signal on generating heat through the test structure 13 ie, on a power dissipation depending on the one from the RF test field 5 extracted energy. For example, the test structure 13 configured to convert said extracted energy into resistive losses that may be detected, for example by means of a test signal detector comprising a thermal infrared detector. For example, high ohmic losses, ie a large temperature difference of the test structure 13 , indicative of the absence of mechanical damage in the edge semiconductor region 112 be, and low or no ohmic losses, so a low temperature difference of the test structure 13 , may / may be indicative of the presence of mechanical damage in the edge semiconductor region 112 ,

Further examples of a test signal and other ways to inspect the semiconductor edge region are shown below. As a result, mechanical damages in the peripheral semiconductor region 112 result in that the test structure 13 is no longer designed to extract energy from the RF test field 5 , for example, that the test structure 13 is no longer designed to convert the extracted energy into a detectable test signal. This can be a little complex and less costly inspection of the semiconductor device 1 guarantee.

For example, the detectable test signal may be the extracted energy as such. For example, the amount of the RF test field 5 extracted energy, with a high amount of extracted energy indicative of the absence of mechanical damage in the peripheral semiconductor region 112 and wherein a low amount of extracted energy is indicative of the presence of mechanical damage in the edge semiconductor region 112 can be.

Like in the 1A shown, the electrically conductive path 131 be a closed path. A closed conductive electrical path 131 can be advantageously used to generate said detectable test signal, for example for generating said resistive losses.

At this point, it should be recalled that the electrically conductive path 131 a diode (not shown) may be electrically coupled to a diode to generate said light signal, said diode may be formed by a simple suitable pn junction.

2A schematically shows a perspective view of a semiconductor device 1 according to one or more embodiments. Corresponding to the 2A show the 2 B a schematic perspective side view of a section of a vertical cross section of the semiconductor device 1 according to one or more embodiments. The basic nature of the semiconductor device 1 that in the 2A -B corresponds essentially corresponds to the nature, as in the 1A -B is shown. Accordingly, the semiconductor device comprises said semiconductor body 11 , the marginal semiconductor area 112 and the active semiconductor region 111 includes. For example, the semiconductor body is largely an n ^- region.

The active semiconductor area 111 indicates the active surface area 121 on, and the edge semiconductor area 112 indicates the edge surface area 122 on, with the test structure 13 at least partially on the edge surface area 122 is arranged.

In the 2A -B is the active surface area 121 such that it faces the edge surface area 122 is arranged slightly elevated. However, it should be understood that this slightly increased arrangement of the active surface area 121 is not necessary to testing the edge semiconductor region 112 perform.

On the active surface area 121 may be a first load contact structure 14 be arranged, which is a front side metallization 141 may include. The first load contact structure 14 is in the 2A -B shown only schematically. The first load contact structure 14 may be configured to inject a load current into the semiconductor device 1 , in particular in the active semiconductor region 111 , In other words, one of the semiconductor device traverses 1 guided load current, in particular the active semiconductor region 111 and essentially not the edge semiconductor region 112 ,

For example, the test structure 13 electrically from the first load contact structure 14 isolated. At this point it should also be understood that the test structure 13 should not be used to the load current in the semiconductor body 11 feed.

The test structure 13 in the 2A -B illustrated semiconductor device 1 includes said electrically conductive path 131 which is not completely closed but is almost closed. Between a first end 131-1 the electrically conductive path 131 and a second end 131-2 is a small gap.

The test structure 13 further includes a capacitor 133 which electrically connects to the electrically conductive path 131 is coupled. In particular, the capacitor includes 133 a first electrode 131-1 that is electrically connected to the first end 131-1 of the electrically conductive path 131 is connected, and a second electrode 133-2 that is electrically connected to the second end 131-2 the electrically conductive path 131 connected is.

Like in the 2A is shown, the electrically conductive path 131 , the first electrode 133-1 , as well as the second electrode 133-2 on the edge surface area 122 be arranged and each the entire active surface area 121 completely surrounded. For example, the electrically conductive path 131 , the first electrode 1333-1 and the second electrode 133-2 form a monolithic component on the edge surface area 122 is arranged. In other words, the first electrode 133-1 , the second electrode 133-2 and the electrically conductive path 131 be formed by a single electrically conductive path, wherein such a single electrically conductive path, the active surface area 121 completely surrounded. In addition, such a single electrically conductive path may comprise sections which are arranged substantially parallel to one another and spaced apart from one another and which have mutually complementary directions of progression.

The capacitor 133 may have a capacity and the electrically conductive path 131 may have an inductance, so the test structure 13 has at least one resonant frequency, which is defined by the inductance of the electrically conductive path 131 and the capacitance of the capacitor 133 ,

For example, the RF test field 5 provided with a frequency range, said resonant frequency of the test structure 13 includes. So can the test structure 13 from the RF test field 5 Extract energy. Such extraction of energy may be detected by a corresponding test signal detector, which will be described in more detail below.

For example, the presence of mechanical damage in the edge semiconductor region 112 to a detuning of the test structure 13 lead, so the test structure 13 has a significantly different resonant frequency or no resonant frequency due to the damage in the edge semiconductor region 112 , Should in the edge semiconductor area 112 however, no mechanical damage is present, the test structure remains 13 tuned and extracted energy from the RF test field 5 if the RF test field 5 is provided with a frequency range including the resonant frequency.

In another embodiment, both the first end 131-1 and the second end 131-2 electrically spaced from one another, electrically to a bulk region of the semiconductor device 1 be coupled. In such an embodiment, the test structure 13 convert the extracted energy into resistive losses. Said bulk region may be part of the peripheral semiconductor region 112 be. In addition, the test structure 13 then, for example, have no pn junction or be coupled to no pn junction. In another embodiment, the electrically conductive path 131 comprise a diode or to a diode (in 2A not shown) for generating said light signal to be electrically coupled, wherein the diode may be formed by a suitable pn junction. For example, the first end 131-1 to an n-region (or to a p-region) of the edge semiconductor region 112 be coupled, and the second end 141-2 may be to a p-region (or to an n-region) of the edge semiconductor region 112 be coupled.

Now considering in particular the 2 B , so may the semiconductor device 1 also an insulator 132 include, for example, a dielectric, for example, an oxide, wherein the insulator 132 the electrically conductive path 131 electrically from the edge semiconductor region 112 isolated. In particular, the electrically conductive path 131 by means of the insulator 132 mechanically to the edge semiconductor region 112 be coupled.

The test structure 13 can continue digging 133-3 in the peripheral semiconductor region 112 is arranged. The ditch 133-3 may comprise charge carriers of a first conductivity type. For example, the ditch 133-3 essentially a p-region.

In particular, as in the 2 B pictured, the trench can 133-3 and / or the insulator 132 an integral part of the edge semiconductor region 112 form. In addition, the electrodes can 133-1 and 133-2 and / or the electrically conductive path 131 in contact with the edge surface area 122 , Therefore, mechanical damage within the peripheral semiconductor region 112 the test structure 13 detune, so the test structure 13 then is no longer trained to extract energy, for example, so that the test structure 13 has a significantly altered resonant frequency.

In the event that the test structure 13 Energy from the RF test field 5 extracted, one can be between the electrodes 133-1 and 133-2 electric field generated in the trench upon extraction 133-3 extend. In other words, the test structure 13 at least a portion of the extracted energy into said electric field between the electrodes 133-1 133-2 which generates electric field in the edge semiconductor region 112 protrudes, in particular at least partially through the trench 133-3 ,

The ditch 133-3 can be a first zone 133-31 and a second zone 133-32 include, both zones 133-3 and 133-32 Contain charge carriers of a second conductivity type. For example, the two zones are 133-31 and 133-32 essentially around n ⁺ regions. The first zone 133-31 can with the first electrode 133-1 in contact, and the second zone 133-32 can from the first zone 133-31 be arranged separately and in contact with the second electrode 133-2 of the capacitor 133 , So the test structure can 13 two pn junctions, with a first pn junction passing through a transition between the first zone 133-31 and the ditch 133-3 is formed, and wherein a second pn junction by a transition between the second zone 133-32 and the ditch 133-3 is trained. Thus, the nature of the capacitor 133 as they are in the 2A and 2 B is shown to represent a varactor structure. Alternatively, the capacitor 133 be formed by a thin gate oxide between the electrodes 133-1 and 133-2 is positioned.

3 schematically shows an equivalent circuit of the test structure 13 as they are in the 2A and 2 B is shown. Accordingly, the test structure includes 13 the electrically conductive path 131 which has an inductance and which is therefore shown as a coil. The capacitor 133 is to the electrically conductive path 131 connected in parallel, the first electrode 133-1 electrically with the first end 131-1 connected, and the second electrode 133-2 electrically with the second end 131-2 of the electrically conductive path 131 connected is. In addition, this extends between the two electrodes 133-1 and 133-2 generated electric field in the trench 133-3 , which is within the edge semiconductor region 112 is arranged. The first pn junction, passing through a transition between the first zone 133-31 and the ditch 133-3 is formed, is as a first diode 134 represented, and the second pn junction, by a transition between the second zone 133-32 and the ditch 133-3 is formed, is as a second diode 135 shown.

Both the anode 134-1 of the first pn junction (diode) 134 as well as the anode 135-1 of the second pn junction (diode) 135 are therefore through the trench 133-3 comprising the charge carrier of the first conductivity type is formed. The cathode 134-2 of the first pn junction (diode) 134 is formed by the first zone 133-31 comprising charge carriers of the second conductivity type and electrically connected to the first electrode 131-1 of the capacitor 133 connected is. Accordingly, the cathode 135-2 of the second pn junction (diode) 135 through the second zone 133-32 formed, the charge carriers of the second conductivity type comprises and those with the second electrode 133-2 of the capacitor 133 connected is. So the two are PN transition 134 and 135 antiserially switched to each other.

4 schematically shows a block diagram of a device 3 for contactless testing of a peripheral semiconductor region of a semiconductor device 1 according to one or more embodiments. Around keeping it simple is the semiconductor device 1 that in the 4 is shown, similar to the embodiment of the 1A shown. However, it should be understood that the semiconductor device 1 which is to be tested, could have a different nature, for example, a nature, as exemplified in 2A and 2 B is shown. What the semiconductor device 1 As far as the device is concerned 3 Thus, reference may be made to the above, and in particular to the description concerning the 1A and 1B ,

The device 3 includes a generator 31 and a test signal detector 32 that can be operatively linked to each other. The generator 31 is designed to generate the RF test field 5 spaced from the semiconductor device 1 and for directing the generated RF test field 5 on the test structure 13 of the semiconductor device 1 ,

For example, the device can 3 and the semiconductor device 1 be spaced from each other. In particular, an exact positioning of the semiconductor device is 1 not necessary to the semiconductor device 1 to test. It should only be ensured that the RF test field 5 from the test structure 13 is received, so the test structure 13 from the RF test field 5 Can extract energy.

As explained in detail above, the test structure is 13 of the semiconductor device 1 configured to generate a test signal in dependence on the extracted energy, so that the test signal from the test signal detector 32 the device 3 can be detected. Various examples of such a detectable test signal have already been given above. For example, the test signal may be substantiated by the amount of energy extracted itself. Thus, the test signal detector 32 be configured to detect that a certain amount of energy of the generated RF test field 5 from the test structure 13 has been extracted. In another embodiment, that of the test structure 13 generated test signal to a light signal. For these purposes, as explained above, the test structure 13 comprise a diode configured to convert the extracted energy into a light signal. Thus, the test signal detector 32 be configured to detect such a light signal. In another embodiment, the test structure 13 be designed to convert the extracted energy into ohmic losses, thus producing heat (power dissipation). So the test signal detector can 32 be configured to detect a change in temperature of the semiconductor device 1 , For example, such detection may be based on thermal infrared detection.

For example, a high amount of extracted energy, such as a strong light signal or a significant temperature difference of the semiconductor device 1 indicative of the absence of mechanical damage in the peripheral semiconductor region 112 of the semiconductor device 1 , Should the test structure 13 however, essentially no energy from the RF test field 5 extract, for example, if the test structure produces only a weak light signal or no light signal, or if the semiconductor device 1 has no significant temperature difference after passing the RF test field 5 This may be indicative of the presence of mechanical damage within the edge semiconductor region 112 be. This is because the mechanical damage within the peripheral semiconductor region 112 also the test structure 13 can damage, so the test structure 13 then no longer trained, energy from the RF test field 5 to extract, as it has been explained in more detail above.

More generally speaking, the semiconductor device can 1 be designed to be operated at a frequency of a few kHz to a few 100 kHz. Such an operating frequency is typical of power semiconductor devices as mentioned above. As an example, a power IGBT may be operated at a switching frequency of up to several 100 kHz. For example, the generator provides 31 the RF test field 5 with a frequency at least twice as high as the operating frequency for which the semiconductor device 1 is trained. For example, this indicates from the generator 31 generated RF test field 5 a frequency in the range of several MHz. In one embodiment, the test structure is 13 only trained energy from the RF test field 5 to extract if the frequency of the RF test field 5 is a multiple of the operating frequency range for which the semiconductor device 1 is designed.

A circuit diagram of an exemplary embodiment of the device 3 is schematic in the 5 shown. Accordingly, the generator can 31 a power circuit 311 include, wherein the power circuit 311 four switches 311-1 to 311-4 includes, which may be semiconductor transistors. The power circuit 311 of the generator 31 is the first stimulant 313 and second excitation means 314 coupled. Both the first stimulants 313 as well as the second stimulants 314 may be formed as a respective coil. In addition, the power circuit 111 to a voltage source 34 and to earth 33 be coupled. Furthermore, the generator 31 a power source 312 exhibit that between mass 33 and the switch 311-2 is coupled. The power source 312 may be a DC source, which is a balancing current provides. The power circuit 111 may be configured to provide a first electrical power signal for the first excitation means 313 and a second electrical power signal for the second excitation means 314 ,

The first stimulants 313 can be the first electrical power signal in the RF test field 5 convert. The second excitation means 314 may convert the second electrical power signal into a radio frequency electromagnetic test field, hereinafter referred to as an RF reference field.

The RF test field 5 is from the test structure 13 received, with the test structure 13 in the example shown, the capacitor 133 and the electrically conductive path 131 includes, as in the 5 shown. A distance between the electrically conductive path 131 and the first excitation means 313 , which are formed, for example, as said coil may be several 100 microns. For example, the distance is within the range of 90 μm to 900 μm.

The RF reference field is derived from a reference structure 13 ' which are part of the said device 3 can be. The reference structure 13 ' is also on Earth 33 connected. In particular, the reference structure 13 ' have a similar or identical nature as the test structure 13 , Accordingly, the reference structure 13 ' a reference path 131 ' and a reference capacitor 133 ' include, wherein the reference path 131 ' may have the same or a similar inductance as the electrically conductive path 131 , and wherein the reference capacitor 133 ' may have the same or a similar capacity as the capacitor 133 the test structure 13 ,

Consequently, the generator can 31 have an oscillator structure having an oscillator frequency different from the test structure 13 is dependent. In the schematic in the 5 The arrangement shown can be that of the test structure 13 generated test signal affect a differential voltage at outputs of the power circuit 311 is measurable. Such a differential voltage may be from the test signal detector 32 be measured, which may have a corresponding meter.

Should the test structure 13 due to mechanical damage within the edge semiconductor region 112 be detuned, so can a frequency of the test signal detector 32 detected differential voltage deviate from a frequency that would be present if the test structure 13 not due to mechanical damage within the edge semiconductor region 112 be different, so be different in frequency, in the absence of mechanical damage within the peripheral semiconductor region 112 would be generated.

7 schematically shows a flowchart of a method 4 for testing a semiconductor edge region of a semiconductor device according to one or more embodiments, for example for testing the semiconductor device 1 according to one of the 1A to 2 B illustrated embodiments. The procedure 4 includes the step 41 generating an electromagnetic radio frequency test field 5 spaced from the semiconductor device 1 and judging, as part of a second step 42 , the generated electromagnetic radio frequency test field 5 on the test structure 13 of the semiconductor device 1 , In a third step 43 becomes the test signal that comes from the test structure 13 depending on the test structure 13 from the electromagnetic radio frequency test field extracted energy has been detected detected. In summary, the procedure 4 for contactless testing of a semiconductor device 1 a method of operating the device 3 that above with respect to the 4 and 5 has been described. In that regard, reference is made to the above.

6 schematically shows a flowchart of a method 2 for producing a semiconductor component according to one or more embodiments, for example for producing the semiconductor component 1 according to one of the 1A to 2 B illustrated embodiments.

In a first step 21 becomes the semiconductor body 11 produced, wherein the semiconductor body 11 the active semiconductor region 111 and an edge semiconductor region 112 comprising the active semiconductor region 111 surrounds. As described above, the active semiconductor region 111 the active surface area 121 on, and the edge semiconductor area 112 indicates the edge surface area 122 on. For example, the semiconductor body 11 be produced such that the semiconductor body 11 Charge carrier of the second conductivity type comprises.

In a second step 22 will be on the active surface area 121 a front side metallization 141 generated, with the front side metallization 141 a front side metallization material. For example, the front side metallization 141 be formed for feeding a load current into the semiconductor body 11 , in particular in the active semiconductor region 111 ,

In a third step 23 becomes on the edge surface area 122 the test structure 13 generated. The step of generating the test structure 13 involves generating the electrical conductive path 131 on the edge surface area 122 , The electrically conductive path 131 is produced to have the same front side metallization material as the front side metallization 141 , For example, both include the electrically conductive path 131 and the front side metallization 141 at least one of the following: aluminum, an aluminum alloy, copper, gold, silver and / or another metal alloy. In another embodiment, the front side metallization material includes both in the electrically conductive path 131 as well as in the front side metallization 141 may be present, at least one of the following: nickel, highly doped polysilicon, magnesium and / or a magnesium alloy.

For example, the front side metallization 141 and the electrically conductive path 131 generated simultaneously. For example, the front side metallization 141 and the electrically conductive path 131 by using one and the same metallization device. In other words, generating the test structure 13 on the edge surface area 122 can be easily integrated into already existing semiconductor production lines, since the same metallization device can be used and / or because the electrically conductive path 131 and the front side metallization 141 may have the same front metallization material. In one embodiment, it contains the electrodes 131-1 and 131-2 comprehensive capacitor 133 also the same front side metallization material as the front side metallization 141 ,

As described above, the test structure 13 be designed to extract energy from the RF test field 5 , In the context of the present description, however, this formulation is not necessarily intended to imply that the test structure 13 must "absorb" the extracted energy, for example by converting the extracted energy into ohmic losses, into light or something similar. For example, considering the embodiment schematically illustrated in FIG 5 is shown, so the test structure 13 essentially only the capacitor 133 and the electrically conductive path 131 and thus hardly produce ohmic losses when they pass the RF test field 5 is suspended.

In the above embodiments, embodiments of semiconductor devices, semiconductor components, and semiconductor devices have been described. For example, these embodiments are based on silicon (Si). Thus, a monocrystalline semiconductor layer or monocrystalline semiconductor region, for example, the semiconductor regions 11 . 111 . 112 . 133-3 . 133-31 . 133-32 of exemplary embodiments, typically be a monocrystalline Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon may be used.

However, it should be understood that the semiconductor regions 11 . 111 . 112 . 133-3 . 133-31 . 133-32 may be formed of any semiconductor material suitable for manufacturing a semiconductor device, a semiconductor component or a semiconductor device. Examples of such materials include, but are not limited to, elemental semiconductor materials such as silicon (Si) or germanium (Ge), group IV, compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quarternary III-V, Semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (ImP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide ( InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmiumteluride (CdTe) and mercury cadmiumteluride (HgCdTe), to name but a few. The above-mentioned semiconductor materials are also referred to as homojunction semiconductor materials. When combining two different semiconductor materials, a heterojunction semiconductor material can be formed. Examples of such heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN) aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN) aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN) gallium nitride (GaN), aluminum gallium nitride (AlGaN) gallium nitride (GaN ), Indium gallium nitride (InGaN) aluminum gallium nitride (AlGaN), silicon silicon carbide (Si _x C _1-x ), and silicon-SiGe heterojunction semiconductor materials. Currently, Si, SiC, GaAs, and GaN materials are mainly used in power semiconductor applications

Spatial terms such as "below," "above," "lower," "above," "upper," etc., have been used for purposes of a simple description to describe the position of a first element relative to a second element. It is intended that these terms encompass different orientations of the corresponding device, particularly orientations in addition to or different from the orientations shown in the drawings. Furthermore, terms such as "first," "second," etc. are used to describe various elements, regions, sections, etc. Similar terms refer to similar elements throughout the description.

The terms "comprising," "including," "having," etc., as used herein, are rather vague terms that indicate the presence of said elements or features, but do not preclude other elements or features. The indefinite and definite articles are meant to include both the singular and plural unless the context clearly indicates otherwise.

LIST OF REFERENCE NUMBERS

1

Semiconductor device

11

Semiconductor body

111

Active semiconductor area

112

Edge semiconductor region

113

side walls

121

Active surface area

122

Edge surface area

123

edge

13

test structure

13 '

reference structure

131

Electrically conductive path

131-1

First end

131-2

Second end

131 '

reference path

132

insulator

133

capacitor

133 '

reference capacitor

133-1

First electrode

133-2

Second electrode

133-3

dig

133-31

First zone

133-32

Second zone

134

First pn transition

134-1

Anode of the first pn junction

134-2

Cathode of the first pn junction

135

Second pn junction

135-1

Anode of the second pn junction

135-2

Cathode of the second pn junction

14

First load contact structure

141

side metallisation

2

Method for producing a semiconductor component

21

Producing a semiconductor body

22

Generating a front side metallization

23

Produce a test structure

3

Apparatus for contactless testing of a semiconductor device

31

generator

311

Power circuit

311-1

First switch

311-2

Second switch

311-3

Third switch

311-4

Fourth switch

312

power source

313

First stimulus

314

Second stimulus

32

Test signal detector

33

Dimensions

34

voltage source

4

Method for contactless testing of a semiconductor device

41

Generating an electromagnetic radio frequency test field

42

Directing the generated radio frequency electromagnetic test field to a test structure

43

Detecting an extraction of energy

5

Electromagnetic radio frequency test field

Claims (20)

Power semiconductor component ( 1 ), comprising a semiconductor body ( 11 ), wherein the semiconductor body ( 11 ) an active semiconductor region ( 111 ) and an active semiconductor region ( 111 ) surrounding edge semiconductor region ( 112 ), wherein the active semiconductor region ( 111 ) an active surface area ( 121 ) and the edge semiconductor region ( 112 ) an edge surface area ( 122 ), the power semiconductor device ( 1 ) further comprising: a test structure ( 13 ) for contactless testing of the edge semiconductor region ( 112 ), the test structure ( 13 ) an electrically conductive path ( 131 ) located on the edge surface area ( 122 ), and wherein the test structure ( 13 ) is adapted to extract energy from a spaced generated electromagnetic radio frequency test field ( 5 ); where: - the test structure ( 13 ) is adapted to produce a test signal in dependence on the extracted energy, wherein the produced test signal is designed to be processed by a test signal detector ( 32 ) spaced from the power semiconductor device (FIG. 1 ) is arranged to be detected; and - the electrically conductive path ( 131 ) the active surface area ( 121 ) surrounds. Power semiconductor component ( 1 ) according to claim 1, wherein the power semiconductor component ( 1 ) an isolator ( 132 ), wherein the insulator ( 132 ) the electrically conductive path ( 131 ) from the edge semiconductor region ( 112 ) is electrically isolated and at least partially in the edge semiconductor region ( 112 ) is arranged. Power semiconductor component ( 1 ) according to one of the preceding claims, wherein the electrically conductive path ( 131 ) with the edge semiconductor region ( 112 ) is in contact. Power semiconductor component ( 1 ) according to any one of the preceding claims, wherein the test structure ( 13 ) at least partially an integral part of the edge semiconductor region ( 112 ). Power semiconductor component ( 1 ) according to one of the preceding claims, wherein the electrically conductive path ( 131 ) is a closed path. Power semiconductor component ( 1 ) according to any one of the preceding claims, wherein - the test structure ( 13 ) a capacitor ( 133 ), wherein the capacitor ( 133 ) has a capacitance and electrically to the electrically conductive path ( 131 ) is coupled; The electrically conductive path ( 131 ) has an inductance; - the test structure ( 13 ) has at least one resonance frequency which is determined by the inductance of the electrically conductive path ( 131 ) and the capacitance of the capacitor ( 133 ) is defined. Power semiconductor component ( 1 ) according to claim 6, wherein the capacitor ( 133 ) a first electrode ( 133-1 ) and a second electrode ( 133-2 ), wherein the first electrode ( 133-1 ) and the second electrode ( 13-2 ) on the edge surface area ( 122 ) are arranged, and wherein an electric field between the first electrode ( 133-1 ) and the second electrode ( 133-2 ) into the edge semiconductor region ( 112 ). Power semiconductor component ( 1 ) according to claim 7, wherein the electrically conductive path ( 131 ), the first electrode ( 133-1 ) and the second electrode ( 133-2 ) form a monolithic component on the edge surface area ( 122 ) is arranged. Power semiconductor component ( 1 ) according to claim 7 or 8, wherein the peripheral semiconductor region ( 112 ) a trench ( 133-3 ), the trench ( 133-3 ) Comprises charge carriers of a first conductivity type, and wherein said electric field between the first electrode ( 133-1 ) and the second electrode ( 133-2 ) in the ditch ( 133-3 ). Power semiconductor component ( 1 ) according to claim 9, wherein the trench ( 133-3 ) a first zone ( 133-31 ) and a second zone ( 133-32 ), the first zone ( 133-31 ) and the second zone ( 133-32 ) comprise both charge carriers of a second conductivity type, and wherein the first zone ( 133-31 ) is in contact with the first electrode ( 133-1 ), and wherein the second zone ( 133-32 ) is in contact with the second electrode ( 133-2 ). Power semiconductor component ( 1 ) according to one of the preceding claims, wherein the edge semiconductor region ( 112 ) at least one pn junction ( 134 ; 135 ), wherein the at least one pn junction ( 134 ; 135 ) electrically to the test structure ( 13 ) is coupled. Power semiconductor component ( 1 ) according to any one of the preceding claims, wherein the test structure ( 13 ) comprises a diode, wherein the diode is electrically connected to the electrically conductive path ( 131 ) and configured to convert the extracted energy into a detectable light signal. Power semiconductor component ( 1 ) according to one of the preceding claims, wherein the electrically conductive path has a first end ( 131-1 ) and a second end ( 131-2 ) spaced apart from each other, and wherein both the first end ( 131-1 ) as well as the second end ( 131-2 ) electrically to a bulk region of the power semiconductor device ( 1 ) are coupled. Power semiconductor component ( 1 ) according to one of the preceding claims, wherein the electrically conductive path ( 131 ) is configured to convert the extracted energy into a detectable heat signal. Power semiconductor component ( 1 ) according to one of the preceding claims, further comprising a first load contact structure ( 14 ), wherein the first load contact structure ( 14 ) on the active surface area ( 121 ) and electrically from the test structure ( 13 ), and wherein the first load contact structure ( 14 ) is designed for feeding a load current into the active semiconductor region ( 111 ). Power semiconductor component ( 1 ) according to one of the preceding claims, wherein the power semiconductor component ( 1 ) is adapted to be operated within an operating frequency range, wherein the electromagnetic radio frequency test field ( 5 ) has a frequency which is at least twice as large as a frequency from the operating frequency range. Power semiconductor component ( 1 ) according to one of the preceding claims, wherein the semiconductor body region ( 11 ) is formed of silicon carbide. Procedure ( 2 ) for producing a power semiconductor device ( 1 ), the procedure ( 2 ) comprising: - producing ( 21 ) of a semiconductor body ( 11 ), wherein the semiconductor body ( 11 ) an active semiconductor region ( 111 ) and an active semiconductor region ( 111 ) surrounding edge semiconductor region ( 112 ), wherein the active semiconductor region ( 111 ) an active surface area ( 111 ) and the edge semiconductor region ( 112 ) an edge surface area ( 122 ) having; - Produce ( 22 ) of a front side metallization ( 141 ) on the active surface area ( 121 ), wherein the front side metallization ( 141 ) comprises a front side metallization material; - on the edge surface area ( 122 ): To produce ( 23 ) of a test structure ( 13 ) for contactless testing of the edge semiconductor region ( 112 ), so that the test structure ( 13 ) is adapted to extract energy from a spaced generated electromagnetic radio frequency test field ( 5 ) and for producing a test signal in dependence on the extracted energy, the produced test signal being designed to be processed by a test signal detector ( 32 ) spaced from the power semiconductor device (FIG. 1 ) is arranged to be detected, and wherein the electrically conductive path ( 131 ) the active surface area ( 121 ), the step of producing ( 23 ) of the test structure ( 13 ) generating an electrically conductive path ( 131 ) on the edge surface area ( 12 ), and wherein the electrically conductive path ( 131 ) comprises the same front side metallization material as the front side metallization ( 14 ). Procedure ( 2 ) according to claim 18, wherein the front side metallization ( 141 ) and the electrically conductive path ( 131 ) are generated simultaneously. Procedure ( 2 ) according to claim 18 or 19, wherein the front side metallization ( 141 ) and the electrically conductive path ( 131 ) are both produced by the same metallization device.

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