CA2409435A1 - Wireless radio frequency technique design and method for testing of integrated circuits and wafers - Google Patents

Wireless radio frequency technique design and method for testing of integrated circuits and wafers Download PDF

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Publication number
CA2409435A1
CA2409435A1 CA002409435A CA2409435A CA2409435A1 CA 2409435 A1 CA2409435 A1 CA 2409435A1 CA 002409435 A CA002409435 A CA 002409435A CA 2409435 A CA2409435 A CA 2409435A CA 2409435 A1 CA2409435 A1 CA 2409435A1
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Canada
Prior art keywords
circuit
test
ring oscillator
sub
wafer
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Granted
Application number
CA002409435A
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French (fr)
Other versions
CA2409435C (en
Inventor
Brian Moore
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Scanimetrics Inc
Original Assignee
The Governors Of The University Of Alberta
Brian Moore
Scanimetrics Inc.
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Publication date
Priority claimed from CA002308820A external-priority patent/CA2308820A1/en
Application filed by The Governors Of The University Of Alberta, Brian Moore, Scanimetrics Inc. filed Critical The Governors Of The University Of Alberta
Priority to CA2409435A priority Critical patent/CA2409435C/en
Publication of CA2409435A1 publication Critical patent/CA2409435A1/en
Application granted granted Critical
Publication of CA2409435C publication Critical patent/CA2409435C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2822—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere of microwave or radiofrequency circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/308—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation
    • G01R31/311—Contactless testing using non-ionising electromagnetic radiation, e.g. optical radiation of integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Automation & Control Theory (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The present invention is for an apparatus and method for the wireless testing of Integrated Circuits and wafers. The apparatus comprises a test unit external from the wafer and at least one test circuit which is fabricated on the wafer which contains the Integrated Circuit. The test unit transmits an RF
signal to power the test circuit. The test circuit, comprising a variable ring oscillator, performs a series of parametric tests at the normal operating frequency of the Integrated Circuit and transmits the test results to the test unit for analysis.

Claims (73)

1. Apparatus for testing an integrated circuit on a wafer, comprising:
a) a test circuit formed on the wafer with the integrated circuit, the test circuit comprising:
i) a variable ring oscillator circuit having a base ring oscillator circuit, and a plurality of sub-circuits coupled to the base ring oscillator circuit; and, ii) a control circuit to selectively couple the sub-circuits to the base ring oscillator circuit to change the frequency of oscillation of said variable ring oscillator circuit based on a selected sub-circuit; and, b) a test unit separate from the wafer, the test unit linked wirelessly to the test circuit to transmit a signal to activate the test circuit, wherein the test circuit, when activated by the test unit, conducts a separate test of the integrated circuit for at least one of said sub-circuits, the result of said test being represented by said change in frequency of said variable ring oscillator circuit.
2. The apparatus of claim 1 wherein each test conducted by the test circuit is a parametric test.
3. The apparatus of claim 1 wherein at least one sub-circuit comprises a capacitive load to change the frequency of oscillation of the variable ring oscillator circuit.
4. The apparatus of claim 1 wherein at least one sub-circuit comprises a capacitive load and a resistive load to change the frequency of oscillation of the variable ring oscillator circuit.
5. The apparatus of claim 1 wherein at least one sub-circuit comprises a delay element to change the frequency of oscillation of the variable ring oscillator circuit.
6: The apparatus of claim 3 wherein the capacitive load comprises at least one capacitor.
7. The apparatus of claim 4 wherein the capacitive load comprises at least one capacitor and the resistive load comprises at least one resistor.
8. The apparatus of claim 5 wherein the delay element comprises at least one inverter.
9. The apparatus of claim 8 wherein each inverter is a standard CMOS inverter.
10. The apparatus of claim 1 wherein the control circuit comprises a sequencer to selectively couple the sub-circuits to the base ring oscillator circuit to produce a series of test states.
11. The apparatus of claim 1 wherein the signal produced by the test unit is a power signal sufficient to energize the test circuit.
12. The apparatus of claim 1 wherein the test circuit is formed on the wafer with at least two metallization layers of the integrated circuit.
13. The apparatus of claim 1 wherein the test circuit is formed on the wafer with at least one metallization layer and one polysilicon layer of the integrated circuit.
14. The apparatus of claim 1 wherein the test circuit further comprises a transmitter circuit to transmit a test result signal from the test circuit to the test unit.
15. The apparatus of claim 1 wherein said test unit comprises a receiver circuit to receive the test result signal from the test circuit.
16. The apparatus of claim 15 wherein the test unit further comprises a circuit to analyze and display the test result signal.
17. The apparatus of claim 16 wherein the analyzing circuit calculates the value of a parameter being tested.
18. The apparatus of claim 16 wherein the analyzing circuit calculates a ratio of the values of the parameter being tested.
19. The apparatus of claim 18 wherein the test result signal is the output of the variable ring oscillator circuit.
20. The apparatus of claim 10 wherein the test circuit further comprises an antenna adapted to receive the signal from the test unit and a power supply circuit coupled to the antenna and adapted to provide power to the test circuit.
21. The apparatus of claim 20, wherein the power supply circuit comprises a voltage rectifier coupled to the antenna, a voltage regulator coupled to the voltage rectifier and an energy storage element coupled to the voltage regulator, wherein the power supply circuit is adapted to provide a plurality of voltage levels to the test circuit.
22. The apparatus of claim 20, wherein the control circuit further comprises a ring oscillator adapted to provide a first clock signal, and a divider coupled to the ring oscillator and the sequencer and adapted to provide a second clock signal, wherein the second clock signal is provided to the sequencer so that the sequencer can provide a series of test state signals to the variable ring oscillator circuit.
23. The apparatus of claim 14, wherein the transmitter circuit comprises a coupler which is coupled to the variable ring oscillator circuit and an antenna and is adapted to selectively couple the output of the variable ring oscillator to the antenna for transmission of the test result signal to the test unit.
24. The apparatus of claim 23 wherein the coupler capacitively couples the test result signal to the antenna.
25. The apparatus of claim 23 wherein the coupler modulates the impedance of the antenna to transmit the test result signal to the test unit.
26. The apparatus of claim 25, wherein the transmitter circuit further comprises a synchronization element to couple the variable ring oscillator circuit to the coupler.
27. The apparatus of claim 11 wherein the power signal produced by the test unit is a RF power signal.
28. The apparatus of claim 1 wherein there are a plurality of test circuits on the wafer and the test unit tests each test circuit sequentially.
29. The apparatus of claim 1 wherein there is a plurality of test circuits on the wafer and the test unit tests the plurality of test circuits in parallel.
30. The apparatus of claim 1, wherein the test circuit is formed adjacent to a die containing the integrated circuit.
31. The apparatus of claim 1 wherein the test circuit is formed on a die that contains the integrated circuit.
32. The apparatus of claim 1 wherein said test circuit is formed on a large percentage of dies on the wafer.
33. The apparatus of claim 1 wherein said test circuit is formed on dies near the edge of said wafer.
34. The apparatus of claim 1, wherein said test circuit is coupled to a sub-circuit of said integrated circuit and said test is a functional test of the sub-circuit of said integrated circuit, the result of said test being encoded via frequency.
35. A test circuit for testing an integrated circuit on a wafer, the test circuit formed on the wafer with the integrated circuit, the test circuit comprising:
a) a variable ring oscillator having a base ring oscillator circuit and a plurality of sub-circuits coupled to the base ring oscillator circuit;
and b) a control circuit to selectively couple the sub-circuits to the base ring oscillator circuit to change the frequency of oscillation of said variable ring oscillator circuit based on a selected sub-circuit, wherein the test circuit conducts a separate test of the integrated circuit for at least one of said sub-circuits, the result of said test being represented by said change in frequency of said variable ring oscillator circuit.
36. The test circuit of claim 35 wherein each test conducted by the test circuit is a parametric test.
37. The test circuit of claim 35 wherein at least one sub-circuit comprises a capacitive load to change the frequency of oscillation of the variable ring oscillator circuit.
38. The test circuit of claim 35 wherein at least one sub-circuit comprise a capacitive load and a resistive load to change the frequency of oscillation of the variable ring oscillator circuit.
39. The test circuit of claim 35 wherein at least one sub-circuit comprises a delay element to change the frequency of oscillation of the variable ring oscillator circuit.
40. The test circuit of claim 37 wherein the capacitive load comprises at least one capacitor.
41. The test circuit of claim 38 wherein the capacitive load comprises at least one capacitor and the resistive load comprises at least one resistor.
42. The test circuit of claim 39 wherein the delay element comprises at least one inverter.
43. The test circuit of claim 42 wherein each inverter is a standard CMOS inverter.
44. The test circuit of claim 35 wherein the control circuit comprises a sequencer to selectively couple the sub-circuits to the base ring oscillator circuit to produce a series of test states.
45. The test circuit of claim 35 wherein the test circuit is formed on the wafer with at least two metallization layers of the integrated circuit.
46. The apparatus of claim 35 wherein the test circuit is formed on the wafer with at least one metallization layer and one polysilicon layer of the integrated circuit.
47. The test circuit of claim 35 wherein the test circuit produces a test result signal that is the output of the variable ring oscillator circuit.
48. The apparatus of claim 44, wherein the test circuit further comprises an antenna adapted to receive a signal, a power supply circuit coupled to the antenna and adapted to provide power to the test circuit and a transmitter circuit coupled to the variable ring oscillator circuit and the antenna and adapted to transmit a test result signal.
49. The apparatus of claim 48, wherein the power supply circuit comprises a voltage rectifier coupled to the antenna, a voltage regulator coupled to the voltage rectifier and an energy storage element coupled to the voltage regulator, wherein the power supply circuit is adapted to provide a plurality of voltage levels to the test circuit.
50. The apparatus of claim 48, wherein the control circuit further comprises a ring oscillator adapted to provide a first clock signal, and a divider coupled to the ring oscillator and the sequencer and adapted to provide a second clock signal, wherein the second clock signal is provided to the sequencer so that the sequencer can provide a series of test state signals to the variable ring oscillator circuit.
51. The apparatus of claim 48, wherein the transmitter circuit comprises a coupler which is coupled to the variable ring oscillator and the antenna and is adapted to selectively couple the output of the variable ring oscillator circuit to the antenna for transmission of the test result signal.
52. The test circuit of claim 51, wherein the coupler capacitively couples the test result signal to the antenna.
53. The test circuit of claim 51, wherein the coupler modulates the impedance of the antenna to transmit the test result signal.
54. The test circuit of claim 51, wherein the transmitter circuit further comprises a synchronization element to couple the variable ring oscillator circuit to the coupler.
55. The test circuit of claim 35, wherein the test circuit is formed adjacent to a die containing the integrated circuit.
56. The test circuit of claim 35, wherein the test circuit is formed on a die that contains the integrated circuit.
57. The test circuit of claim 35, wherein the test circuit is formed on a large percentage of dies on the wafer.
58. The test circuit of claim 35, wherein the test circuit is formed on dies near the edge of the wafer.
59. The apparatus of claim 35, wherein said test circuit is coupled to a sub-circuit of said integrated circuit and said test is a functional test of the sub-circuit of said integrated circuit, the result of said test being encoded via frequency.
60. A method of testing an integrated circuit on a wafer using a test circuit formed on the wafer with the integrated circuit, the test circuit comprising a variable ring oscillator circuit, having a plurality of sub-circuits coupled to a base ring oscillator circuit, and a control circuit to selectively couple the sub-circuits to the base ring oscillator circuit, wherein each sub-circuit changes the frequency of oscillation of the variable ring oscillator circuit to produce a test result, the method comprising:

(a) activating the test circuit;
(b) coupling a selected sub-circuit to the base ring oscillator circuit to selectively change the frequency of oscillation of the variable ring oscillator circuit thereby producing a test result signal; and, (c) analyzing the test result signal to determine the frequency of oscillation.
61. The method of claim 60, wherein each test conducted by the test circuit is a parametric test.
62. The method of claim 61, wherein step (c) of the method further comprises:
(d) calculating a value for the parameter being tested.
63. The method of claim 61, wherein step (c) of the method further comprises:
(e) calculating a ratio of values for the parameter being tested.
64. The method of claim 60, wherein step (b) further comprises the steps of:
(f) providing a clock signal; and, (g) generating a sequence of test states and state signals based on the clock signal to switchably couple the sub-circuits to the base ring oscillator.
65. The method of claim 64, wherein step (c) further comprises the steps of:
(h) coupling the test result signal to an antenna within the test circuit through a coupler in the test circuit; and, (i) enabling and disabling the coupler to intermittently wirelessly transmit the test result signal to a test unit to allow the test unit to synchronize to the test result signal and analyze the test result signal.
66. The method of claim 65, wherein step (i) further comprises providing a synchronization element to enable and disable the coupler.
67. The method of claim 60, wherein at least one sub-circuit comprises a capacitive load to change the frequency of operation of the variable ring oscillator circuit.
68. The method of claim 60, wherein at least one sub-circuit comprises a capacitive load and a resistive load to change the frequency of operation of the variable ring oscillator circuit.
69. The method of claim 60, wherein at least one sub-circuit comprises a delay element to change the frequency of oscillation of the variable ring oscillator circuit.
70. The method of claim 60, wherein the control circuit comprises a sequencer.
71. The method of claim 60, wherein there are a plurality of test circuits on the wafer and the method further comprises testing each test circuit sequentially.

-43a-
72. The method of claim 60, wherein there are a plurality of test circuits on the wafer and the method further comprises testing each test circuit in parallel.
73. The method of claim 60, wherein said test circuit is coupled to a sub-circuit of said integrated circuit, said test is a functional test of the sub-circuit of said integrated circuit and the result of said test is encoded by the frequency of said test result signal.
CA2409435A 2000-05-15 2001-05-15 Wireless radio frequency technique design and method for testing of integrated circuits and wafers Expired - Fee Related CA2409435C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA2409435A CA2409435C (en) 2000-05-15 2001-05-15 Wireless radio frequency technique design and method for testing of integrated circuits and wafers

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CA002308820A CA2308820A1 (en) 2000-05-15 2000-05-15 Wireless radio frequency technique design and method for testing of integrated circuits and wafers
CA2,308,820 2000-05-15
PCT/CA2001/000688 WO2001088976A2 (en) 2000-05-15 2001-05-15 Wireless radio frequency testing methode of integrated circuits and wafers
CA2409435A CA2409435C (en) 2000-05-15 2001-05-15 Wireless radio frequency technique design and method for testing of integrated circuits and wafers

Publications (2)

Publication Number Publication Date
CA2409435A1 true CA2409435A1 (en) 2001-11-22
CA2409435C CA2409435C (en) 2010-07-20

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014222203B3 (en) * 2014-10-30 2016-03-10 Infineon Technologies Ag Check for marginal damage
CN117785590A (en) * 2024-02-27 2024-03-29 深圳市纽创信安科技开发有限公司 Chip and chip data protection method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014222203B3 (en) * 2014-10-30 2016-03-10 Infineon Technologies Ag Check for marginal damage
US9658279B2 (en) 2014-10-30 2017-05-23 Infineon Technologies Ag Contactless damage inspection of perimeter region of semiconductor device
CN117785590A (en) * 2024-02-27 2024-03-29 深圳市纽创信安科技开发有限公司 Chip and chip data protection method
CN117785590B (en) * 2024-02-27 2024-05-28 深圳市纽创信安科技开发有限公司 Chip and chip data protection method

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Publication number Publication date
CA2409435C (en) 2010-07-20

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Effective date: 20160516