DE102011108172B4 - Speichersystem und Verfahren zum Übermitteln von Konfigurationsbefehlen - Google Patents

Speichersystem und Verfahren zum Übermitteln von Konfigurationsbefehlen Download PDF

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Publication number
DE102011108172B4
DE102011108172B4 DE102011108172A DE102011108172A DE102011108172B4 DE 102011108172 B4 DE102011108172 B4 DE 102011108172B4 DE 102011108172 A DE102011108172 A DE 102011108172A DE 102011108172 A DE102011108172 A DE 102011108172A DE 102011108172 B4 DE102011108172 B4 DE 102011108172B4
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DE
Germany
Prior art keywords
register
drams
mode
inverted
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
DE102011108172A
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German (de)
English (en)
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DE102011108172A1 (de
Inventor
Ingolf Edgar Frank
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Deutschland GmbH
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Texas Instruments Deutschland GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Deutschland GmbH filed Critical Texas Instruments Deutschland GmbH
Priority to DE102011108172A priority Critical patent/DE102011108172B4/de
Priority to US13/554,897 priority patent/US8635418B2/en
Priority to JP2014522930A priority patent/JP6182528B2/ja
Priority to PCT/US2012/047864 priority patent/WO2013016291A2/en
Priority to CN201280036448.8A priority patent/CN103718246B/zh
Publication of DE102011108172A1 publication Critical patent/DE102011108172A1/de
Application granted granted Critical
Publication of DE102011108172B4 publication Critical patent/DE102011108172B4/de
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE102011108172A 2011-07-22 2011-07-22 Speichersystem und Verfahren zum Übermitteln von Konfigurationsbefehlen Active DE102011108172B4 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE102011108172A DE102011108172B4 (de) 2011-07-22 2011-07-22 Speichersystem und Verfahren zum Übermitteln von Konfigurationsbefehlen
US13/554,897 US8635418B2 (en) 2011-07-22 2012-07-20 Memory system and method for passing configuration commands
JP2014522930A JP6182528B2 (ja) 2011-07-22 2012-07-23 構成コマンドを伝えるためのメモリシステム及び方法
PCT/US2012/047864 WO2013016291A2 (en) 2011-07-22 2012-07-23 Memory system and method for passing configuration commands
CN201280036448.8A CN103718246B (zh) 2011-07-22 2012-07-23 存储器系统和用于传输配置命令的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102011108172A DE102011108172B4 (de) 2011-07-22 2011-07-22 Speichersystem und Verfahren zum Übermitteln von Konfigurationsbefehlen

Publications (2)

Publication Number Publication Date
DE102011108172A1 DE102011108172A1 (de) 2013-01-24
DE102011108172B4 true DE102011108172B4 (de) 2013-10-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE102011108172A Active DE102011108172B4 (de) 2011-07-22 2011-07-22 Speichersystem und Verfahren zum Übermitteln von Konfigurationsbefehlen

Country Status (3)

Country Link
US (1) US8635418B2 (enExample)
JP (1) JP6182528B2 (enExample)
DE (1) DE102011108172B4 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10310547B2 (en) * 2016-03-05 2019-06-04 Intel Corporation Techniques to mirror a command/address or interpret command/address logic at a memory device
US10395722B2 (en) * 2017-09-29 2019-08-27 Intel Corporation Reading from a mode register having different read and write timing
KR20240000101A (ko) 2022-06-23 2024-01-02 삼성전자주식회사 메모리 칩 및 상기 메모리 칩을 포함하는 메모리 시스템

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090141564A1 (en) * 2007-11-29 2009-06-04 Micron Technology, Inc. Memory register definition systems and methods
US20110156934A1 (en) * 2006-05-27 2011-06-30 Bae Seung Jun Method and apparatus for parallel data interfacing using combined coding and recording medium therefor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11282591A (ja) * 1998-03-31 1999-10-15 Hitachi Ltd メモリ回路
US7102958B2 (en) 2001-07-20 2006-09-05 Samsung Electronics Co., Ltd. Integrated circuit memory devices that support selective mode register set commands and related memory modules, memory controllers, and methods
DE60308150T2 (de) 2002-02-06 2007-07-19 Koninklijke Philips Electronics N.V. Adressenraum, bussystem, speicherungssteuerung und einrichtungssystem
DE10345384B3 (de) * 2003-09-30 2005-03-24 Infineon Technologies Ag Schaltungssystem
US7188208B2 (en) * 2004-09-07 2007-03-06 Intel Corporation Side-by-side inverted memory address and command buses
US7610455B2 (en) 2005-05-11 2009-10-27 Infineon Technologies Ag Technique to read special mode register
KR100919815B1 (ko) 2008-08-04 2009-10-01 주식회사 하이닉스반도체 반도체 메모리 장치
US8200925B2 (en) 2008-10-31 2012-06-12 Mosaid Technologies Incorporated Data mirroring in serial-connected memory system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110156934A1 (en) * 2006-05-27 2011-06-30 Bae Seung Jun Method and apparatus for parallel data interfacing using combined coding and recording medium therefor
US20090141564A1 (en) * 2007-11-29 2009-06-04 Micron Technology, Inc. Memory register definition systems and methods

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Norm JEDEC Standard No. 79-2A Revision of JESD79-2, January 2004. JEDEC STANDARD DDR2 SDRAM SPECIFICATION *

Also Published As

Publication number Publication date
CN103718246A (zh) 2014-04-09
US8635418B2 (en) 2014-01-21
US20130046923A1 (en) 2013-02-21
JP2014523600A (ja) 2014-09-11
DE102011108172A1 (de) 2013-01-24
JP6182528B2 (ja) 2017-08-16

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R082 Change of representative

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