DE102010019487B8 - Speichervorrichtung, Datenverarbeitungsvorrichtung und Verfahren - Google Patents

Speichervorrichtung, Datenverarbeitungsvorrichtung und Verfahren Download PDF

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Publication number
DE102010019487B8
DE102010019487B8 DE102010019487.5A DE102010019487A DE102010019487B8 DE 102010019487 B8 DE102010019487 B8 DE 102010019487B8 DE 102010019487 A DE102010019487 A DE 102010019487A DE 102010019487 B8 DE102010019487 B8 DE 102010019487B8
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Germany
Prior art keywords
data processing
storage device
processing device
storage
data
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DE102010019487.5A
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German (de)
English (en)
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DE102010019487A1 (de
DE102010019487B4 (de
Inventor
Daniele Balluchi
Graziano Mirichigni
Corrado Villa
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Micron Technology Inc
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Micron Technology Inc
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Publication of DE102010019487A1 publication Critical patent/DE102010019487A1/de
Application granted granted Critical
Publication of DE102010019487B4 publication Critical patent/DE102010019487B4/de
Publication of DE102010019487B8 publication Critical patent/DE102010019487B8/de
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G11C5/144—Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Power Sources (AREA)
  • Read Only Memory (AREA)
  • Control Of Voltage And Current In General (AREA)
DE102010019487.5A 2009-05-26 2010-05-05 Speichervorrichtung, Datenverarbeitungsvorrichtung und Verfahren Active DE102010019487B8 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/472,153 US8504759B2 (en) 2009-05-26 2009-05-26 Method and devices for controlling power loss
US12/472,153 2009-05-26

Publications (3)

Publication Number Publication Date
DE102010019487A1 DE102010019487A1 (de) 2010-12-23
DE102010019487B4 DE102010019487B4 (de) 2022-12-29
DE102010019487B8 true DE102010019487B8 (de) 2023-02-23

Family

ID=43123141

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102010019487.5A Active DE102010019487B8 (de) 2009-05-26 2010-05-05 Speichervorrichtung, Datenverarbeitungsvorrichtung und Verfahren

Country Status (6)

Country Link
US (1) US8504759B2 (enExample)
JP (1) JP6066392B2 (enExample)
KR (1) KR101550469B1 (enExample)
CN (1) CN101901041B (enExample)
DE (1) DE102010019487B8 (enExample)
SG (1) SG166735A1 (enExample)

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2011013351A1 (ja) * 2009-07-30 2013-01-07 パナソニック株式会社 アクセス装置およびメモリコントローラ
US8601202B1 (en) * 2009-08-26 2013-12-03 Micron Technology, Inc. Full chip wear leveling in memory device
US8607089B2 (en) 2011-05-19 2013-12-10 Intel Corporation Interface for storage device access over memory bus
US8671299B2 (en) * 2011-05-26 2014-03-11 Google Inc. Delaying the initiation of transitioning to a lower power mode by placing a computer system into an intermediate power mode between a normal power mode and the lower power mode
EP2729863B1 (en) 2011-07-06 2017-09-06 Telefonaktiebolaget LM Ericsson (publ) A method for controlling transaction exchanges between two integrated circuits
US9294224B2 (en) 2011-09-28 2016-03-22 Intel Corporation Maximum-likelihood decoder in a memory controller for synchronization
EP3712774B1 (en) 2011-09-30 2023-02-15 Tahoe Research, Ltd. Apparatus and method for implementing a multi-level memory hierarchy
WO2013048491A1 (en) 2011-09-30 2013-04-04 Intel Corporation Apparatus, method and system that stores bios in non-volatile random access memory
US9378133B2 (en) 2011-09-30 2016-06-28 Intel Corporation Autonomous initialization of non-volatile random access memory in a computer system
CN103946816B (zh) 2011-09-30 2018-06-26 英特尔公司 作为传统大容量存储设备的替代的非易失性随机存取存储器（nvram）
WO2013048467A1 (en) 2011-09-30 2013-04-04 Intel Corporation Generation of far memory access signals based on usage statistic tracking
EP3364304B1 (en) 2011-09-30 2022-06-15 INTEL Corporation Memory channel that supports near memory and far memory access
CN103946826B (zh) 2011-09-30 2019-05-31 英特尔公司 用于在公共存储器通道上实现多级存储器层级的设备和方法
EP2761464B1 (en) 2011-09-30 2018-10-24 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy having different operating modes
WO2013077867A1 (en) 2011-11-22 2013-05-30 Intel Corporation Access control for non-volatile random access memory across platform agents
CN103975287B (zh) 2011-12-13 2017-04-12 英特尔公司 使用非易失性随机存取存储器的服务器中的增强系统睡眠状态支持
CN104106057B (zh) 2011-12-13 2018-03-30 英特尔公司 用非易失性随机存取存储器提供对休眠状态转变的即时响应的方法和系统
KR101571991B1 (ko) 2011-12-20 2015-11-25 인텔 코포레이션 2-레벨 메모리 계층구조에서 메모리측 캐쉬의 동적인 부분적 전원 차단
CN103999161B (zh) 2011-12-20 2016-09-28 英特尔公司 用于相变存储器漂移管理的设备和方法
WO2013095465A1 (en) 2011-12-21 2013-06-27 Intel Corporation High-performance storage structures and systems featuring multiple non-volatile memories
BR112014015441B1 (pt) 2011-12-22 2021-05-25 Intel Corporation conservação de energia por meio de desligamento de canal de memória
WO2013095530A1 (en) 2011-12-22 2013-06-27 Intel Corporation Efficient pcms refresh mechanism background
CN104137084B (zh) 2011-12-28 2017-08-11 英特尔公司 提高耐久性和抗攻击性的用于pcm缓存的有效动态随机化地址重映射
US9152428B2 (en) 2012-09-28 2015-10-06 Intel Corporation Alternative boot path support for utilizing non-volatile memory devices
US9329990B2 (en) 2013-01-11 2016-05-03 Micron Technology, Inc. Host controlled enablement of automatic background operations in a memory device
US9753487B2 (en) 2013-03-14 2017-09-05 Micron Technology, Inc. Serial peripheral interface and methods of operating same
US9195406B2 (en) 2013-06-28 2015-11-24 Micron Technology, Inc. Operation management in a memory device
US9459676B2 (en) 2013-10-28 2016-10-04 International Business Machines Corporation Data storage device control with power hazard mode
US9343116B2 (en) 2014-05-28 2016-05-17 Micron Technology, Inc. Providing power availability information to memory
US10204047B2 (en) 2015-03-27 2019-02-12 Intel Corporation Memory controller for multi-level system memory with coherency unit
US10387259B2 (en) 2015-06-26 2019-08-20 Intel Corporation Instant restart in non volatile system memory computing systems with embedded programmable data checking
US10073659B2 (en) 2015-06-26 2018-09-11 Intel Corporation Power management circuit with per activity weighting and multiple throttle down thresholds
US10108549B2 (en) 2015-09-23 2018-10-23 Intel Corporation Method and apparatus for pre-fetching data in a system having a multi-level system memory
US10185501B2 (en) 2015-09-25 2019-01-22 Intel Corporation Method and apparatus for pinning memory pages in a multi-level system memory
US10261901B2 (en) 2015-09-25 2019-04-16 Intel Corporation Method and apparatus for unneeded block prediction in a computing system having a last level cache and a multi-level system memory
US9792224B2 (en) 2015-10-23 2017-10-17 Intel Corporation Reducing latency by persisting data relationships in relation to corresponding data in persistent memory
US10719236B2 (en) * 2015-11-20 2020-07-21 Arm Ltd. Memory controller with non-volatile buffer for persistent memory operations
US10033411B2 (en) 2015-11-20 2018-07-24 Intel Corporation Adjustable error protection for stored data
US10095618B2 (en) 2015-11-25 2018-10-09 Intel Corporation Memory card with volatile and non volatile memory space having multiple usage model configurations
US9747041B2 (en) 2015-12-23 2017-08-29 Intel Corporation Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device
US10007606B2 (en) 2016-03-30 2018-06-26 Intel Corporation Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory
US10185619B2 (en) 2016-03-31 2019-01-22 Intel Corporation Handling of error prone cache line slots of memory side cache of multi-level system memory
US10120806B2 (en) 2016-06-27 2018-11-06 Intel Corporation Multi-level system memory with near memory scrubbing based on predicted far memory idle time
US10915453B2 (en) 2016-12-29 2021-02-09 Intel Corporation Multi level system memory having different caching structures and memory controller that supports concurrent look-up into the different caching structures
US10445261B2 (en) 2016-12-30 2019-10-15 Intel Corporation System memory having point-to-point link that transports compressed traffic
US20180261281A1 (en) 2017-03-10 2018-09-13 Micron Technology, Inc. Methods for mitigating power loss events during operation of memory devices and memory devices employing the same
US10884656B2 (en) * 2017-06-16 2021-01-05 Microsoft Technology Licensing, Llc Performing background functions using logic integrated with a memory
US10304814B2 (en) 2017-06-30 2019-05-28 Intel Corporation I/O layout footprint for multiple 1LM/2LM configurations
KR102244921B1 (ko) * 2017-09-07 2021-04-27 삼성전자주식회사 저장 장치 및 그 리프레쉬 방법
US11188467B2 (en) 2017-09-28 2021-11-30 Intel Corporation Multi-level system memory with near memory capable of storing compressed cache lines
US10860244B2 (en) 2017-12-26 2020-12-08 Intel Corporation Method and apparatus for multi-level memory early page demotion
US11099995B2 (en) 2018-03-28 2021-08-24 Intel Corporation Techniques for prefetching data to a first level of memory of a hierarchical arrangement of memory
US11112997B2 (en) * 2018-08-21 2021-09-07 Samsung Electronics Co., Ltd. Storage device and operating method thereof
KR102784807B1 (ko) * 2018-08-21 2025-03-24 삼성전자주식회사 저장 장치 및 그것의 동작 방법
CN110908491B (zh) * 2018-08-28 2023-08-08 上海忆芯实业有限公司 功耗控制方法、控制部件及其电子系统
US11055228B2 (en) 2019-01-31 2021-07-06 Intel Corporation Caching bypass mechanism for a multi-level memory

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0481508A2 (en) 1990-10-18 1992-04-22 Seiko Epson Corporation Back-up/restore information processing system
US20050057957A1 (en) 2003-09-12 2005-03-17 Fujitsu Limited Ferroelectric memory
US20060184719A1 (en) 2005-02-16 2006-08-17 Sinclair Alan W Direct data file storage implementation techniques in flash memories

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003131956A (ja) * 2001-10-25 2003-05-09 Fuji Xerox Co Ltd デバイス制御システム
JP4302970B2 (ja) * 2002-12-16 2009-07-29 富士通株式会社 差分更新方法、プログラム及び装置
US20040153902A1 (en) * 2003-01-21 2004-08-05 Nexflash Technologies, Inc. Serial flash integrated circuit having error detection and correction
US20040268046A1 (en) * 2003-06-27 2004-12-30 Spencer Andrew M Nonvolatile buffered memory interface
JP2007019576A (ja) * 2005-07-05 2007-01-25 Megachips System Solutions Inc カメラシステムの起動方法
US8010764B2 (en) * 2005-07-07 2011-08-30 International Business Machines Corporation Method and system for decreasing power consumption in memory arrays having usage-driven power management
US7984084B2 (en) * 2005-08-03 2011-07-19 SanDisk Technologies, Inc. Non-volatile memory with scheduled reclaim operations
US7801576B2 (en) * 2006-06-09 2010-09-21 Sony Ericsson Mobile Communications Ab Wireless communications devices with self-cleaning displays
EP2030205B1 (en) * 2006-06-22 2011-07-06 SanDisk Corporation Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages
JP2010267341A (ja) * 2009-05-15 2010-11-25 Renesas Electronics Corp 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0481508A2 (en) 1990-10-18 1992-04-22 Seiko Epson Corporation Back-up/restore information processing system
US20050057957A1 (en) 2003-09-12 2005-03-17 Fujitsu Limited Ferroelectric memory
US20060184719A1 (en) 2005-02-16 2006-08-17 Sinclair Alan W Direct data file storage implementation techniques in flash memories

Also Published As

Publication number Publication date
JP6066392B2 (ja) 2017-01-25
KR101550469B1 (ko) 2015-09-04
CN101901041A (zh) 2010-12-01
DE102010019487A1 (de) 2010-12-23
CN101901041B (zh) 2016-01-06
DE102010019487B4 (de) 2022-12-29
JP2010277685A (ja) 2010-12-09
US8504759B2 (en) 2013-08-06
US20100306446A1 (en) 2010-12-02
KR20100127719A (ko) 2010-12-06
SG166735A1 (en) 2010-12-29

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Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: NUMONYX B.V., ROLLE, CH

8181 Inventor (new situation)

Inventor name: VILLA, CORRADO, SOVICO, IT

Inventor name: MIRIVHIGNI, GRAZIANO, PIETRACAMELA, IT

Inventor name: BALLUCHI, DANIELE, VIMERCATE, IT

R081 Change of applicant/patentee

Owner name: MICRON TECHNOLOGY, INC., BOISE, US

Free format text: FORMER OWNERS: BALLUCHI, DANIELE, VIMERCATE, IT; MIRICHIGNI, GRAZIANO, PIETRACAMELA, IT; VILLA, CORRADO, SOVICO, IT

Effective date: 20110304

Owner name: MICRON TECHNOLOGY, INC., BOISE, US

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Effective date: 20110304

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Representative=s name: SAMSON & PARTNER, PATENTANWAELTE, 80538 MUENCHEN,

R081 Change of applicant/patentee

Owner name: MICRON TECHNOLOGY, INC., BOISE, US

Free format text: FORMER OWNER: NUMONYX B.V., ROLLE, CH

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Effective date: 20120521

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