DE102007045851A8 - Elektronische Vorrichtung, Verfahren zum Betreiben einer elektronischen Vorrichtung, Speicherschaltung und Verfahren zum Betreiben einer Speicherschaltung - Google Patents

Elektronische Vorrichtung, Verfahren zum Betreiben einer elektronischen Vorrichtung, Speicherschaltung und Verfahren zum Betreiben einer Speicherschaltung Download PDF

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Publication number
DE102007045851A8
DE102007045851A8 DE102007045851A DE102007045851A DE102007045851A8 DE 102007045851 A8 DE102007045851 A8 DE 102007045851A8 DE 102007045851 A DE102007045851 A DE 102007045851A DE 102007045851 A DE102007045851 A DE 102007045851A DE 102007045851 A8 DE102007045851 A8 DE 102007045851A8
Authority
DE
Germany
Prior art keywords
operating
electronic device
memory circuit
memory
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE102007045851A
Other languages
English (en)
Other versions
DE102007045851A1 (de
Inventor
Thomas Hein
Aaron Nygren
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Polaris Innovations Ltd
Original Assignee
Qimonda AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qimonda AG filed Critical Qimonda AG
Publication of DE102007045851A1 publication Critical patent/DE102007045851A1/de
Publication of DE102007045851A8 publication Critical patent/DE102007045851A8/de
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE102007045851A 2006-09-29 2007-09-25 Elektronische Vorrichtung, Verfahren zum Betreiben einer elektronischen Vorrichtung, Speicherschaltung und Verfahren zum Betreiben einer Speicherschaltung Withdrawn DE102007045851A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/537,401 US7844888B2 (en) 2006-09-29 2006-09-29 Electronic device, method for operating an electronic device, memory circuit and method of operating a memory circuit
US11/537,401 2006-09-29

Publications (2)

Publication Number Publication Date
DE102007045851A1 DE102007045851A1 (de) 2008-04-10
DE102007045851A8 true DE102007045851A8 (de) 2008-09-11

Family

ID=39154850

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102007045851A Withdrawn DE102007045851A1 (de) 2006-09-29 2007-09-25 Elektronische Vorrichtung, Verfahren zum Betreiben einer elektronischen Vorrichtung, Speicherschaltung und Verfahren zum Betreiben einer Speicherschaltung

Country Status (4)

Country Link
US (1) US7844888B2 (de)
JP (1) JP4783765B2 (de)
KR (1) KR100980694B1 (de)
DE (1) DE102007045851A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8132074B2 (en) * 2007-11-19 2012-03-06 Intel Corporation Reliability, availability, and serviceability solutions for memory technology
US8255783B2 (en) * 2008-04-23 2012-08-28 International Business Machines Corporation Apparatus, system and method for providing error protection for data-masking bits
KR20120098326A (ko) * 2011-02-28 2012-09-05 에스케이하이닉스 주식회사 반도체 장치 및 데이터 처리방법
US9823966B1 (en) 2013-11-11 2017-11-21 Rambus Inc. Memory component with error-detect-correct code interface
US11385963B1 (en) 2021-02-24 2022-07-12 Western Digital Technologies, Inc. Usage of data mask in DRAM write
KR20220140234A (ko) * 2021-04-09 2022-10-18 삼성전자주식회사 멀티 레벨 신호 시스템에서 최적 전이 코드를 생성하기 위한 신호 처리 방법 및 반도체 장치
KR20230013395A (ko) * 2021-07-19 2023-01-26 에스케이하이닉스 주식회사 메모리 및 메모리의 동작 방법
CN115291816B (zh) * 2022-10-10 2022-12-09 新云滕(云南)科技有限公司 一种用于基于三维可视化的配电管理系统的存储器系统

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573728A (en) * 1969-01-09 1971-04-06 Ibm Memory with error correction for partial store operation
US3814922A (en) * 1972-12-01 1974-06-04 Honeywell Inf Systems Availability and diagnostic apparatus for memory modules
JPH04107757A (ja) * 1990-08-29 1992-04-09 Koufu Nippon Denki Kk メモリエラーチェックシステム
JPH0793225A (ja) 1993-09-27 1995-04-07 Toshiba Corp メモリチェック方式
JPH0816486A (ja) 1994-06-29 1996-01-19 Hitachi Ltd 欠陥救済用ｌｓｉとメモリ装置
US6014720A (en) * 1997-05-05 2000-01-11 Intel Corporation Dynamically sizing a bus transaction for dual bus size interoperability based on bus transaction signals
US6311299B1 (en) 1999-03-01 2001-10-30 Micron Technology, Inc. Data compression circuit and method for testing embedded memory devices
US6718444B1 (en) * 2001-12-20 2004-04-06 Advanced Micro Devices, Inc. Read-modify-write for partial writes in a memory controller
JP2005327437A (ja) * 2004-04-12 2005-11-24 Nec Electronics Corp 半導体記憶装置
US7464241B2 (en) * 2004-11-22 2008-12-09 Intel Corporation Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding
US7392456B2 (en) * 2004-11-23 2008-06-24 Mosys, Inc. Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory
JP2006221334A (ja) 2005-02-09 2006-08-24 Tdk Corp メモリコントローラ、フラッシュメモリシステム及びフラッシュメモリの制御方法

Also Published As

Publication number Publication date
JP2008091012A (ja) 2008-04-17
DE102007045851A1 (de) 2008-04-10
JP4783765B2 (ja) 2011-09-28
KR20080030526A (ko) 2008-04-04
KR100980694B1 (ko) 2010-09-07
US7844888B2 (en) 2010-11-30
US20080082898A1 (en) 2008-04-03

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8196 Reprint of faulty title page (publication) german patentblatt: part 1a6
OP8 Request for examination as to paragraph 44 patent law
R016 Response to examination communication
R016 Response to examination communication
R016 Response to examination communication
R081 Change of applicant/patentee

Owner name: INFINEON TECHNOLOGIES AG, DE

Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE

Owner name: POLARIS INNOVATIONS LTD., IE

Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE

R082 Change of representative

Representative=s name: WILHELM & BECK, DE

R081 Change of applicant/patentee

Owner name: POLARIS INNOVATIONS LTD., IE

Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE

R082 Change of representative

Representative=s name: WILHELM & BECK, DE

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee