DE102007012054B4 - Mehrmasterverkettungszweidrahtseriellbus - Google Patents

Mehrmasterverkettungszweidrahtseriellbus Download PDF

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Publication number
DE102007012054B4
DE102007012054B4 DE102007012054.2A DE102007012054A DE102007012054B4 DE 102007012054 B4 DE102007012054 B4 DE 102007012054B4 DE 102007012054 A DE102007012054 A DE 102007012054A DE 102007012054 B4 DE102007012054 B4 DE 102007012054B4
Authority
DE
Germany
Prior art keywords
serial
wire
data
bus
slave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE102007012054.2A
Other languages
German (de)
English (en)
Other versions
DE102007012054A1 (de
Inventor
Takashi Hidai
Slawomir K. Ilnicki
Martin Curran-Gray
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Viavi Solutions Inc
Original Assignee
JDS Uniphase Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JDS Uniphase Corp filed Critical JDS Uniphase Corp
Publication of DE102007012054A1 publication Critical patent/DE102007012054A1/de
Application granted granted Critical
Publication of DE102007012054B4 publication Critical patent/DE102007012054B4/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Debugging And Monitoring (AREA)
  • Small-Scale Networks (AREA)
DE102007012054.2A 2006-03-17 2007-03-13 Mehrmasterverkettungszweidrahtseriellbus Expired - Fee Related DE102007012054B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/378,884 US7634611B2 (en) 2006-03-17 2006-03-17 Multi-master, chained two-wire serial bus
US11/378,884 2006-03-17

Publications (2)

Publication Number Publication Date
DE102007012054A1 DE102007012054A1 (de) 2007-09-20
DE102007012054B4 true DE102007012054B4 (de) 2014-10-30

Family

ID=38375141

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102007012054.2A Expired - Fee Related DE102007012054B4 (de) 2006-03-17 2007-03-13 Mehrmasterverkettungszweidrahtseriellbus

Country Status (3)

Country Link
US (1) US7634611B2 (enExample)
JP (1) JP4966695B2 (enExample)
DE (1) DE102007012054B4 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4978421B2 (ja) * 2007-10-24 2012-07-18 セイコーエプソン株式会社 データ通信システム及び通信制御装置
US7752365B2 (en) * 2008-04-01 2010-07-06 Kyocera Corporation Bi-directional single conductor interrupt line for communication bus
JP5324908B2 (ja) * 2008-08-22 2013-10-23 パナソニック株式会社 カードホストｌｓｉを有するセット機器、およびカードホストｌｓｉ
US8860249B2 (en) * 2010-12-08 2014-10-14 Schlumberger Technology Corporation Power allocation to downhole tools in a bottom hole assembly
US8812760B1 (en) * 2011-12-22 2014-08-19 Cisco Technology, Inc. System and method for monitoring two-wire communication in a network environment
US9858235B2 (en) * 2012-11-15 2018-01-02 Advanced Micro Devices, Inc. Emulated legacy bus operation over a bit-serial bus
US9769051B2 (en) 2014-01-13 2017-09-19 Viavi Solutions Inc. Demarcation unit enclosure and method
JP6321393B2 (ja) * 2014-02-14 2018-05-09 山洋電気株式会社 マスタスレーブ相互間中継装置およびその中継方法
DE102014103524B4 (de) * 2014-03-14 2015-12-17 Osram Gmbh Schaltungsanordnung zum Betreiben zumindest eines Leuchtmittels
TWI569253B (zh) * 2016-01-12 2017-02-01 友達光電股份有限公司 驅動器及其操作方法
CN111984576B (zh) * 2019-05-24 2022-03-22 鸿富锦精密电子(天津)有限公司 数据通信系统以及方法
CN112202573B (zh) * 2020-09-30 2022-08-30 金华飞光科技有限公司 一种二线制的供电、组网通信系统

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050246475A1 (en) * 2001-05-29 2005-11-03 Sun Microsystems, Inc. Method and apparatus for constructing wired-and bus systems

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW230808B (en) * 1993-06-04 1994-09-21 Philips Electronics Nv A two-line mixed analog/digital bus system and a station for use in such a system
JPH103447A (ja) * 1996-06-18 1998-01-06 Matsushita Electric Ind Co Ltd バスブリッジ装置
JP2000242612A (ja) * 1999-02-25 2000-09-08 Sega Enterp Ltd メモリ及びバスを共有化したシステム
US20040255195A1 (en) * 2003-06-12 2004-12-16 Larson Thane M. System and method for analysis of inter-integrated circuit router

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050246475A1 (en) * 2001-05-29 2005-11-03 Sun Microsystems, Inc. Method and apparatus for constructing wired-and bus systems

Also Published As

Publication number Publication date
JP4966695B2 (ja) 2012-07-04
DE102007012054A1 (de) 2007-09-20
US7634611B2 (en) 2009-12-15
JP2007251947A (ja) 2007-09-27
US20070220190A1 (en) 2007-09-20

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8127 New person/name/address of the applicant

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D. STAATES, US

R081 Change of applicant/patentee

Owner name: JDS UNIPHASE CORP. (N. D. GES. D. STAATES DELA, US

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Owner name: VIAVI SOLUTIONS INC. (N. D. GES. D. STAATES DE, US

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R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee