DE102006046129A1 - Vorrichtung, System und Verfahren für einen ständigen Thread auf Benutzerebene - Google Patents

Vorrichtung, System und Verfahren für einen ständigen Thread auf Benutzerebene Download PDF

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Publication number
DE102006046129A1
DE102006046129A1 DE102006046129A DE102006046129A DE102006046129A1 DE 102006046129 A1 DE102006046129 A1 DE 102006046129A1 DE 102006046129 A DE102006046129 A DE 102006046129A DE 102006046129 A DE102006046129 A DE 102006046129A DE 102006046129 A1 DE102006046129 A1 DE 102006046129A1
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DE
Germany
Prior art keywords
thread
sequencer
operating system
level
persistent user
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE102006046129A
Other languages
German (de)
English (en)
Inventor
Gauntam Hillsboro Chinya
Hong Santa Clara Wang
Prashant Folsom Sethi
Shiv Portland Kaushik
Bryant Scottsdale Bigbee
John San Jose Shen
Richard Santa Clara Hankins
Xiang Beaverton Zou
Baiju Portland Patel
Jason Austin Brandt
Anil Portland Aggarwal
John Portland Reid
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE102006046129A1 publication Critical patent/DE102006046129A1/de
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/3009—Thread control instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Executing Machine-Instructions (AREA)
DE102006046129A 2005-09-30 2006-09-28 Vorrichtung, System und Verfahren für einen ständigen Thread auf Benutzerebene Ceased DE102006046129A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/239,475 2005-09-30
US11/239,475 US8028295B2 (en) 2005-09-30 2005-09-30 Apparatus, system, and method for persistent user-level thread

Publications (1)

Publication Number Publication Date
DE102006046129A1 true DE102006046129A1 (de) 2007-04-12

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE102006046129A Ceased DE102006046129A1 (de) 2005-09-30 2006-09-28 Vorrichtung, System und Verfahren für einen ständigen Thread auf Benutzerebene

Country Status (4)

Country Link
US (5) US8028295B2 (https=)
JP (1) JP4690988B2 (https=)
CN (2) CN102981808B (https=)
DE (1) DE102006046129A1 (https=)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8719819B2 (en) 2005-06-30 2014-05-06 Intel Corporation Mechanism for instruction set based thread execution on a plurality of instruction sequencers
US8028295B2 (en) * 2005-09-30 2011-09-27 Intel Corporation Apparatus, system, and method for persistent user-level thread
US8689215B2 (en) * 2006-12-19 2014-04-01 Intel Corporation Structured exception handling for application-managed thread units
JP4450242B2 (ja) 2007-04-10 2010-04-14 ヒロセ電機株式会社 同軸コネクタ
US20080307419A1 (en) * 2007-06-06 2008-12-11 Microsoft Corporation Lazy kernel thread binding
US20080313656A1 (en) * 2007-06-18 2008-12-18 Microsoft Corporation User mode stack disassociation
US20080320475A1 (en) * 2007-06-19 2008-12-25 Microsoft Corporation Switching user mode thread context
US8261284B2 (en) * 2007-09-13 2012-09-04 Microsoft Corporation Fast context switching using virtual cpus
JP4978914B2 (ja) * 2007-10-19 2012-07-18 インテル・コーポレーション マイクロプロセッサ上での複数命令ストリーム／複数データストリームの拡張を可能にする方法およびシステム
JP5167844B2 (ja) * 2008-02-05 2013-03-21 日本電気株式会社 プロセッサ、電子機器、割込み制御方法及び割込み制御プログラム
DE202009018265U1 (de) * 2008-11-04 2011-08-26 Htc Corporation System und Vorrichtung zur Verbesserung eines Ressourcenfreigabeprozesses bei der semi-persistenten Terminierung in einem drahtlosen Kommunikationssystem
US9354944B2 (en) 2009-07-27 2016-05-31 Advanced Micro Devices, Inc. Mapping processing logic having data-parallel threads across processors
US8464035B2 (en) 2009-12-18 2013-06-11 Intel Corporation Instruction for enabling a processor wait state
US9720730B2 (en) * 2011-12-30 2017-08-01 Intel Corporation Providing an asymmetric multicore processor system transparently to an operating system
KR101691063B1 (ko) * 2012-01-10 2016-12-29 인텔 코포레이션 콜백을 이용하는 isa 브리징
WO2013162589A1 (en) * 2012-04-27 2013-10-31 Intel Corporation Migrating tasks between asymmetric computing elements of a multi-core processor
US10162687B2 (en) * 2012-12-28 2018-12-25 Intel Corporation Selective migration of workloads between heterogeneous compute elements based on evaluation of migration performance benefit and available energy and thermal budgets
US9384036B1 (en) 2013-10-21 2016-07-05 Google Inc. Low latency thread context caching
US10037227B2 (en) * 2015-12-17 2018-07-31 Intel Corporation Systems, methods and devices for work placement on processor cores
US11023233B2 (en) 2016-02-09 2021-06-01 Intel Corporation Methods, apparatus, and instructions for user level thread suspension
CN108009007B (zh) * 2016-10-27 2021-01-15 华为技术有限公司 轻量级线程的调度方法及协同管理器、vCPU调度器
CN113946528B (zh) * 2020-07-16 2024-07-30 华为技术有限公司 切换系统架构的方法与装置

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0497445A (ja) 1990-08-16 1992-03-30 Nec Corp 情報処理装置の診断方式
JPH05265876A (ja) 1992-03-19 1993-10-15 Fujitsu Ltd エラー報告処理方式
US5485626A (en) * 1992-11-03 1996-01-16 International Business Machines Corporation Architectural enhancements for parallel computer systems utilizing encapsulation of queuing allowing small grain processing
US6732138B1 (en) * 1995-07-26 2004-05-04 International Business Machines Corporation Method and system for accessing system resources of a data processing system utilizing a kernel-only thread within a user process
US5991790A (en) * 1996-07-01 1999-11-23 Sun Microsystems, Inc. Generation and delivery of signals in a two-level, multithreaded system
US6223204B1 (en) * 1996-12-18 2001-04-24 Sun Microsystems, Inc. User level adaptive thread blocking
US5872963A (en) * 1997-02-18 1999-02-16 Silicon Graphics, Inc. Resumption of preempted non-privileged threads with no kernel intervention
US6766515B1 (en) * 1997-02-18 2004-07-20 Silicon Graphics, Inc. Distributed scheduling of parallel jobs with no kernel-to-kernel communication
US6175916B1 (en) * 1997-05-06 2001-01-16 Microsoft Corporation Common-thread inter-process function calls invoked by jumps to invalid addresses
US6189023B1 (en) * 1997-09-30 2001-02-13 Tandem Computers Incorporated Simulating shared code thread modules with shared code fibers
US5923892A (en) 1997-10-27 1999-07-13 Levy; Paul S. Host processor and coprocessor arrangement for processing platform-independent code
US6289369B1 (en) * 1998-08-25 2001-09-11 International Business Machines Corporation Affinity, locality, and load balancing in scheduling user program-level threads for execution by a computer system
US6366946B1 (en) * 1998-12-16 2002-04-02 Microsoft Corporation Critical code processing management
EP1037147A1 (en) * 1999-03-15 2000-09-20 BRITISH TELECOMMUNICATIONS public limited company Resource scheduling
JP3557947B2 (ja) * 1999-05-24 2004-08-25 日本電気株式会社 複数のプロセッサで同時にスレッドの実行を開始させる方法及びその装置並びにコンピュータ可読記録媒体
US7043725B1 (en) * 1999-07-09 2006-05-09 Hewlett-Packard Development Company, L.P. Two tier arrangement for threads support in a virtual machine
HK1046049A1 (zh) * 1999-09-01 2002-12-20 Intel Corporation 用於多线程处理器的分支指令
JP2001255961A (ja) 2000-03-01 2001-09-21 Internatl Business Mach Corp <Ibm> コンピュータ及び冷却ファンの制御方法
US6651163B1 (en) * 2000-03-08 2003-11-18 Advanced Micro Devices, Inc. Exception handling with reduced overhead in a multithreaded multiprocessing system
US6961941B1 (en) * 2001-06-08 2005-11-01 Vmware, Inc. Computer configuration for resource management in systems including a virtual machine
JP3702813B2 (ja) * 2001-07-12 2005-10-05 日本電気株式会社 マルチスレッド実行方法及び並列プロセッサシステム
US20030191730A1 (en) * 2002-04-05 2003-10-09 Compaq Information Technologies Group, L.P. Unobtrusive rule-based computer usage enhancement system
US7200846B2 (en) * 2002-08-05 2007-04-03 Sun Microsystems, Inc. System and method for maintaining data synchronization
US7962545B2 (en) * 2002-12-27 2011-06-14 Intel Corporation Dynamic service registry for virtual machines
US7216346B2 (en) * 2002-12-31 2007-05-08 International Business Machines Corporation Method and apparatus for managing thread execution in a multithread application
US7406699B2 (en) * 2003-04-02 2008-07-29 Microsoft Corporation Enhanced runtime hosting
US7093147B2 (en) * 2003-04-25 2006-08-15 Hewlett-Packard Development Company, L.P. Dynamically selecting processor cores for overall power efficiency
US7376954B2 (en) * 2003-08-28 2008-05-20 Mips Technologies, Inc. Mechanisms for assuring quality of service for programs executing on a multithreaded processor
US7496928B2 (en) * 2003-08-28 2009-02-24 Microsoft Corporation Method and system for moderating thread priority boost for I/O completion
US7360223B2 (en) * 2003-09-24 2008-04-15 Hewlett-Packard Development Company, L.P. Arrangements and methods for invoking an upcall in a computer system
US20050076186A1 (en) * 2003-10-03 2005-04-07 Microsoft Corporation Systems and methods for improving the x86 architecture for processor virtualization, and software systems and methods for utilizing the improvements
US7380039B2 (en) * 2003-12-30 2008-05-27 3Tera, Inc. Apparatus, method and system for aggregrating computing resources
US8533716B2 (en) * 2004-03-31 2013-09-10 Synopsys, Inc. Resource management in a multicore architecture
US9189230B2 (en) * 2004-03-31 2015-11-17 Intel Corporation Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution
US20060075404A1 (en) * 2004-10-06 2006-04-06 Daniela Rosu Method and system for scheduling user-level I/O threads
US7669204B2 (en) * 2004-10-14 2010-02-23 International Business Machines Corporation Autonomic SMT System tuning
US8621458B2 (en) * 2004-12-21 2013-12-31 Microsoft Corporation Systems and methods for exposing processor topology for virtual machines
US8607235B2 (en) * 2004-12-30 2013-12-10 Intel Corporation Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention
US8719819B2 (en) * 2005-06-30 2014-05-06 Intel Corporation Mechanism for instruction set based thread execution on a plurality of instruction sequencers
US7992144B1 (en) * 2005-04-04 2011-08-02 Oracle America, Inc. Method and apparatus for separating and isolating control of processing entities in a network interface
US8516483B2 (en) 2005-05-13 2013-08-20 Intel Corporation Transparent support for operating system services for a sequestered sequencer
US7752620B2 (en) * 2005-06-06 2010-07-06 International Business Machines Corporation Administration of locks for critical sections of computer programs in a computer that supports a multiplicity of logical partitions
US8028295B2 (en) * 2005-09-30 2011-09-27 Intel Corporation Apparatus, system, and method for persistent user-level thread

Also Published As

Publication number Publication date
US9383997B2 (en) 2016-07-05
CN102981808A (zh) 2013-03-20
US20110314480A1 (en) 2011-12-22
US9766891B2 (en) 2017-09-19
US9875102B2 (en) 2018-01-23
CN101038543A (zh) 2007-09-19
JP2007102781A (ja) 2007-04-19
US20070079301A1 (en) 2007-04-05
CN102981808B (zh) 2015-07-29
US20160274910A1 (en) 2016-09-22
CN101038543B (zh) 2013-01-02
US8479217B2 (en) 2013-07-02
JP4690988B2 (ja) 2011-06-01
US20170102944A1 (en) 2017-04-13
US8028295B2 (en) 2011-09-27
US20130275735A1 (en) 2013-10-17

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