DE10124351B4 - Verfahren und Vorrichtung zum Verarbeiten zweier Datenoperanden in einem Prozessor - Google Patents

Verfahren und Vorrichtung zum Verarbeiten zweier Datenoperanden in einem Prozessor Download PDF

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Publication number
DE10124351B4
DE10124351B4 DE10124351A DE10124351A DE10124351B4 DE 10124351 B4 DE10124351 B4 DE 10124351B4 DE 10124351 A DE10124351 A DE 10124351A DE 10124351 A DE10124351 A DE 10124351A DE 10124351 B4 DE10124351 B4 DE 10124351B4
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DE
Germany
Prior art keywords
data
operand
coding scheme
data operand
path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE10124351A
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German (de)
English (en)
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DE10124351A1 (de
Inventor
Glenn T. Ft. Collins Colon-Bonet
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Hewlett Packard Development Co LP
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Hewlett Packard Development Co LP
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Publication of DE10124351A1 publication Critical patent/DE10124351A1/de
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Publication of DE10124351B4 publication Critical patent/DE10124351B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/012—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising in floating-point computations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
DE10124351A 2000-05-30 2001-05-18 Verfahren und Vorrichtung zum Verarbeiten zweier Datenoperanden in einem Prozessor Expired - Fee Related DE10124351B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/583,206 US6738795B1 (en) 2000-05-30 2000-05-30 Self-timed transmission system and method for processing multiple data sets
US583206 2000-05-30

Publications (2)

Publication Number Publication Date
DE10124351A1 DE10124351A1 (de) 2001-12-20
DE10124351B4 true DE10124351B4 (de) 2005-10-27

Family

ID=24332126

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10124351A Expired - Fee Related DE10124351B4 (de) 2000-05-30 2001-05-18 Verfahren und Vorrichtung zum Verarbeiten zweier Datenoperanden in einem Prozessor

Country Status (3)

Country Link
US (2) US6738795B1 (enExample)
JP (1) JP2002007111A (enExample)
DE (1) DE10124351B4 (enExample)

Families Citing this family (22)

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US20050177588A1 (en) * 2002-04-17 2005-08-11 Koninklijke Philips Electronics N.V. Data communication bus
US7065602B2 (en) * 2003-07-01 2006-06-20 International Business Machines Corporation Circuit and method for pipelined insertion
EP1538635B1 (en) * 2003-11-26 2008-05-14 Texas Instruments Incorporated Scan testable first-in first-out architecture
US7392270B2 (en) * 2004-07-29 2008-06-24 International Business Machines Corporation Apparatus and method for reducing the latency of sum-addressed shifters
JP4571903B2 (ja) 2005-12-02 2010-10-27 富士通株式会社 演算処理装置，情報処理装置，及び演算処理方法
US8443030B1 (en) * 2007-03-09 2013-05-14 Marvell International Ltd. Processing of floating point multiply-accumulate instructions using multiple operand pathways
US8176391B2 (en) * 2008-01-31 2012-05-08 International Business Machines Corporation System to improve miscorrection rates in error control code through buffering and associated methods
US7746103B1 (en) * 2009-04-02 2010-06-29 Xilinx, Inc. Multi-mode circuit in a self-timed integrated circuit
US9002915B1 (en) 2009-04-02 2015-04-07 Xilinx, Inc. Circuits for shifting bussed data
US7746108B1 (en) 2009-04-02 2010-06-29 Xilinx, Inc. Compute-centric architecture for integrated circuits
US8527572B1 (en) 2009-04-02 2013-09-03 Xilinx, Inc. Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same
US8706793B1 (en) 2009-04-02 2014-04-22 Xilinx, Inc. Multiplier circuits with optional shift function
US9411554B1 (en) 2009-04-02 2016-08-09 Xilinx, Inc. Signed multiplier circuit utilizing a uniform array of logic blocks
US7746109B1 (en) 2009-04-02 2010-06-29 Xilinx, Inc. Circuits for sharing self-timed logic
US7948265B1 (en) 2009-04-02 2011-05-24 Xilinx, Inc. Circuits for replicating self-timed logic
US7982496B1 (en) 2009-04-02 2011-07-19 Xilinx, Inc. Bus-based logic blocks with optional constant input
WO2011137209A1 (en) 2010-04-30 2011-11-03 Cornell University Operand-optimized asynchronous floating-point units and methods of use thereof
US8914430B2 (en) 2010-09-24 2014-12-16 Intel Corporation Multiply add functional unit capable of executing scale, round, GETEXP, round, GETMANT, reduce, range and class instructions
US8402164B1 (en) 2010-10-27 2013-03-19 Xilinx, Inc. Asynchronous communication network and methods of enabling the asynchronous communication of data in an integrated circuit
US10318297B2 (en) 2015-01-30 2019-06-11 Huawei Technologies Co., Ltd. Method and apparatus for operating a self-timed parallelized multi-core processor
US11132198B2 (en) * 2019-08-29 2021-09-28 International Business Machines Corporation Instruction handling for accumulation of register results in a microprocessor
CN113489482B (zh) * 2021-07-06 2023-10-20 北京中科芯蕊科技有限公司 基于Mousetrap的异步微流水线数据流控制器

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5649225A (en) * 1994-06-01 1997-07-15 Advanced Micro Devices, Inc. Resynchronization of a superscalar processor

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US5040190A (en) * 1989-12-22 1991-08-13 Adtran Analog data station terminal
US5805479A (en) * 1995-09-25 1998-09-08 United Microelectronics Corp. Apparatus and method for filtering digital signals
US5798952A (en) 1996-02-29 1998-08-25 Hewlett-Packard Company Leading bit anticipator
US5757687A (en) * 1996-08-06 1998-05-26 Hewlett-Packard Co. Method and apparatus for bounding alignment shifts to enable at-speed denormalized result generation in an FMAC
US6609189B1 (en) * 1998-03-12 2003-08-19 Yale University Cycle segmented prefix circuits
US6529924B1 (en) * 2000-03-27 2003-03-04 International Business Machines Corporation Method and apparatus for generating shift amount signals for an alignment shifter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5649225A (en) * 1994-06-01 1997-07-15 Advanced Micro Devices, Inc. Resynchronization of a superscalar processor

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
CIRCELLO, J.C.: The Superscalar Hardware Architec- ture of the MC68060, August 1994, S. 1-2 (Internet: http://www.computerhistory.org/store/ac atalog/GB_HCVI_Circello.html)
CIRCELLO, J.C.: The Superscalar Hardware Architec-ture of the MC68060, August 1994, S. 1-2 (Internet: http://www.computerhistory.org/store/acatalog/GB_HCVI_Circello.html) *
POWEL, J.: Meet the 68000, Digital Antic, Vol. 4, No. 1, May 1985, pg. 28, S. 1-6 (Internet: http:// www.atarimagazines.com/v4n1/68000.html
POWEL, J.: Meet the 68000, Digital Antic, Vol. 4, No. 1, May 1985, pg. 28, S. 1-6 (Internet: http://www.atarimagazines.com/v4n1/68000.html *

Also Published As

Publication number Publication date
DE10124351A1 (de) 2001-12-20
US6738795B1 (en) 2004-05-18
JP2002007111A (ja) 2002-01-11
US20040044716A1 (en) 2004-03-04
US6970897B2 (en) 2005-11-29

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee