DE10121792C2 - Universelle Ladeadresse/Wertevorhersageschema - Google Patents
Universelle Ladeadresse/WertevorhersageschemaInfo
- Publication number
- DE10121792C2 DE10121792C2 DE10121792A DE10121792A DE10121792C2 DE 10121792 C2 DE10121792 C2 DE 10121792C2 DE 10121792 A DE10121792 A DE 10121792A DE 10121792 A DE10121792 A DE 10121792A DE 10121792 C2 DE10121792 C2 DE 10121792C2
- Authority
- DE
- Germany
- Prior art keywords
- value
- prediction
- counter
- command
- counters
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 claims description 21
- 230000007246 mechanism Effects 0.000 claims description 3
- 230000011664 signaling Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 12
- 230000008901 benefit Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 101150035983 str1 gene Proteins 0.000 description 2
- 238000012790 confirmation Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
- G06F9/3832—Value prediction for operands; operand history buffers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
- G06F9/3455—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results using stride
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Advance Control (AREA)
Description
- a) erforderlich, die bestmögliche Ladeadresse/Wertvorhersage zu machen, und
- b) erforderlich, die Befehle zu bestimmen, deren Operanden mit der höchsten Wahrscheinlichkeit vorhergesagt werden können und die einen nur geringen Mehraufwand verursachen, auch wenn die vorhergesagte Adresse/Wert falsch war.
Ein Kennzeichenfeld 14 (Stand der Technik), 32 Bit lang,
ein LRU Info-Feld 32, 6 Bit lang, in Abhängigkeit von der Anzahl der gebrauchten Schrittweitenfelder,
ein Letztwertfeld 42, 64 Bit lang,
vier Schrittweitenfelder 41a bis 41d, jedes 16 Bit lang, und ein Schrittweitenverlaufmuster-(SHP)-Feld 43, 6 mal 2 Bit = 12 Bit lang.
Damit zeigt das SHP auf den PHT-Eintrag '000000000000' mit seinem Zähler gesetzt auf: c0 = 12 (max), c1 = c2 = c3 = 0 (min).
Damit zeigt der c0-Zähler 45a auf str0-Feld 41a, das im nächsten Zyklus für eine Letztwertvorhersage benutzt werden kann.
Da das Schrittweitenfeld 41a, str0, für die Vorhersage benutzt wird, bleibt SHP gleich '00 00 00 00 00 00'.
Die Vorhersage benutzt immer noch str0, aber in dem leeren Schrittweitenfeld wird keine Schrittweite gespeichert. Das SHP wird verändert in Abhängigkeit von dem benutzten Schrittweitenfeld:
Wenn str1-Feld 41b zum Speichern des neuen Deltawerts benutzt wird, ist das entsprechende SHP '01 00 00 00 00 00'.
In einem ersten Schritt 510 - beim Anlaufen des Programms - werden alle Zähler initialisiert, d. h. beim Setup - vorteilhafterweise gemäß dem oben angegebenen Schema.
In einem Schritt 610 wird der Befehl zunächst decodiert. Dann wird in einem Entscheidungsblock 620 geprüft, ob dieser gleiche Befehl als in Tabelle 40 vorkommend identifiziert werden kann. Damit wird die Befehlsadresse verglichen mit der Kennzeichnung, die im Kennzeichnungsfeld 14 in Tabelle 40 gespeichert ist.
Claims (10)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00111339 | 2000-05-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE10121792A1 DE10121792A1 (de) | 2001-12-06 |
DE10121792C2 true DE10121792C2 (de) | 2003-09-25 |
Family
ID=8168843
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10121792A Expired - Fee Related DE10121792C2 (de) | 2000-05-26 | 2001-05-04 | Universelle Ladeadresse/Wertevorhersageschema |
Country Status (2)
Country | Link |
---|---|
US (1) | US6986027B2 (de) |
DE (1) | DE10121792C2 (de) |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7222226B1 (en) | 2002-04-30 | 2007-05-22 | Advanced Micro Devices, Inc. | System and method for modifying a load operation to include a register-to-register move operation in order to forward speculative load results to a dependent operation |
US7028166B2 (en) * | 2002-04-30 | 2006-04-11 | Advanced Micro Devices, Inc. | System and method for linking speculative results of load operations to register values |
US7089400B1 (en) * | 2002-08-29 | 2006-08-08 | Advanced Micro Devices, Inc. | Data speculation based on stack-relative addressing patterns |
CN1726459A (zh) * | 2002-12-12 | 2006-01-25 | 皇家飞利浦电子股份有限公司 | 基于用于数据预取的步距预测的计数器 |
US7024537B2 (en) * | 2003-01-21 | 2006-04-04 | Advanced Micro Devices, Inc. | Data speculation based on addressing patterns identifying dual-purpose register |
US6976147B1 (en) * | 2003-01-21 | 2005-12-13 | Advanced Micro Devices, Inc. | Stride-based prefetch mechanism using a prediction confidence value |
US8386648B1 (en) | 2003-06-26 | 2013-02-26 | Nvidia Corporation | Hardware support system for accelerated disk I/O |
US8683132B1 (en) | 2003-09-29 | 2014-03-25 | Nvidia Corporation | Memory controller for sequentially prefetching data for a processor of a computer system |
US8356142B1 (en) * | 2003-11-12 | 2013-01-15 | Nvidia Corporation | Memory controller for non-sequentially prefetching data for a processor of a computer system |
US8700808B2 (en) * | 2003-12-01 | 2014-04-15 | Nvidia Corporation | Hardware support system for accelerated disk I/O |
US7263600B2 (en) * | 2004-05-05 | 2007-08-28 | Advanced Micro Devices, Inc. | System and method for validating a memory file that links speculative results of load operations to register values |
US7461211B2 (en) * | 2004-08-17 | 2008-12-02 | Nvidia Corporation | System, apparatus and method for generating nonsequential predictions to access a memory |
US7441087B2 (en) * | 2004-08-17 | 2008-10-21 | Nvidia Corporation | System, apparatus and method for issuing predictions from an inventory to access a memory |
US7554464B1 (en) * | 2004-09-30 | 2009-06-30 | Gear Six, Inc. | Method and system for processing data having a pattern of repeating bits |
US8356143B1 (en) | 2004-10-22 | 2013-01-15 | NVIDIA Corporatin | Prefetch mechanism for bus master memory access |
US8533430B2 (en) * | 2005-04-14 | 2013-09-10 | International Business Machines Corporation | Memory hashing for stride access |
US20060253677A1 (en) * | 2005-05-04 | 2006-11-09 | Arm Limited | Data access prediction |
US7747841B2 (en) * | 2005-09-26 | 2010-06-29 | Cornell Research Foundation, Inc. | Method and apparatus for early load retirement in a processor system |
AU2007212342B2 (en) | 2006-02-03 | 2011-05-12 | Russell H. Fish Iii | Thread optimized multiprocessor architecture |
US7657729B2 (en) * | 2006-07-13 | 2010-02-02 | International Business Machines Corporation | Efficient multiple-table reference prediction mechanism |
US7856548B1 (en) * | 2006-12-26 | 2010-12-21 | Oracle America, Inc. | Prediction of data values read from memory by a microprocessor using a dynamic confidence threshold |
US7788473B1 (en) * | 2006-12-26 | 2010-08-31 | Oracle America, Inc. | Prediction of data values read from memory by a microprocessor using the storage destination of a load operation |
US9311085B2 (en) * | 2007-12-30 | 2016-04-12 | Intel Corporation | Compiler assisted low power and high performance load handling based on load types |
US8356128B2 (en) * | 2008-09-16 | 2013-01-15 | Nvidia Corporation | Method and system of reducing latencies associated with resource allocation by using multiple arbiters |
US8370552B2 (en) * | 2008-10-14 | 2013-02-05 | Nvidia Corporation | Priority based bus arbiters avoiding deadlock and starvation on buses that support retrying of transactions |
US8698823B2 (en) * | 2009-04-08 | 2014-04-15 | Nvidia Corporation | System and method for deadlock-free pipelining |
US20110010506A1 (en) * | 2009-07-10 | 2011-01-13 | Via Technologies, Inc. | Data prefetcher with multi-level table for predicting stride patterns |
JP5552042B2 (ja) * | 2010-12-27 | 2014-07-16 | インターナショナル・ビジネス・マシーンズ・コーポレーション | プログラム解析の方法、システムおよびプログラム |
US9569385B2 (en) | 2013-09-09 | 2017-02-14 | Nvidia Corporation | Memory transaction ordering |
WO2016097790A1 (en) * | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Apparatus and method to preclude non-core cache-dependent load replays in out-of-order processor |
US11709679B2 (en) * | 2016-03-31 | 2023-07-25 | Qualcomm Incorporated | Providing load address predictions using address prediction tables based on load path history in processor-based systems |
CN108762221B (zh) * | 2018-07-09 | 2021-05-11 | 西安电子科技大学 | 含有不可控事件的自动制造系统的无死锁控制方法 |
US11204771B2 (en) * | 2019-10-24 | 2021-12-21 | Arm Limited | Methods and apparatus for handling processor load instructions |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5442767A (en) * | 1992-10-23 | 1995-08-15 | International Business Machines Corporation | Address prediction to avoid address generation interlocks in computer systems |
US5996060A (en) * | 1997-09-25 | 1999-11-30 | Technion Research And Development Foundation Ltd. | System and method for concurrent processing |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2503984B2 (ja) * | 1986-07-15 | 1996-06-05 | 日本電気株式会社 | 情報処理装置 |
JPS63284673A (ja) * | 1987-05-15 | 1988-11-21 | Nec Corp | 情報処理装置 |
US5222767A (en) * | 1991-09-30 | 1993-06-29 | Volkema Russell H | Double use manuscript divider |
EP0663083B1 (de) * | 1992-09-29 | 2000-12-20 | Seiko Epson Corporation | System und verfahren zur handhabung von laden und/oder speichern in einem superskalar mikroprozessor |
JPH09231203A (ja) * | 1996-02-27 | 1997-09-05 | Kofu Nippon Denki Kk | ベクトルストア追い越し制御回路 |
US5919256A (en) * | 1996-03-26 | 1999-07-06 | Advanced Micro Devices, Inc. | Operand cache addressed by the instruction address for reducing latency of read instruction |
US6148394A (en) * | 1998-02-10 | 2000-11-14 | International Business Machines Corporation | Apparatus and method for tracking out of order load instructions to avoid data coherency violations in a processor |
JP2000132390A (ja) * | 1998-10-23 | 2000-05-12 | Toshiba Corp | プロセッサ及び分岐予測器 |
-
2001
- 2001-05-04 DE DE10121792A patent/DE10121792C2/de not_active Expired - Fee Related
- 2001-05-24 US US09/864,590 patent/US6986027B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5442767A (en) * | 1992-10-23 | 1995-08-15 | International Business Machines Corporation | Address prediction to avoid address generation interlocks in computer systems |
US5996060A (en) * | 1997-09-25 | 1999-11-30 | Technion Research And Development Foundation Ltd. | System and method for concurrent processing |
Non-Patent Citations (5)
Title |
---|
CODRESCU, L. u.a.: Architecture of Atlas Chip-Mul-tiprocessor: Dynamically Parallelizing Irregular Applications. In: IEEE Trans. on Computers, Vol. 50, No. 1, Januar 2001, S. 67-82 * |
MARCUELLO, Pedro u.a.: Value prediction for specu-lative multithreaded Architectures. In: Proc. of the 32nd Annual ACM/IEEE International Symposium on Microarchitectures, IEEE, 1999, S. 230-236 * |
NAKRA, Tarun u.a.: Global Context-Based Value Prediction. In: Proc. 5th International Symposium on High-Performance Computer Architecture, IEEE, 1999, S. 4-12 * |
SAZEIDES, Y. u.a.: The Predictability of Data Values. In: Proc. of the 30th Annual ACM/IEEE International Symposium on Microarchitectures, 1997, S. 248-258 * |
WANG, K. u.a.: Highly Accurate Data Value Predic- tion using Hybrid Predictors. In: Proc. of the 30th Annual ACM/IEEE International Symposium on Microarchitecture, IEEE, 1997, S. 281-290 * |
Also Published As
Publication number | Publication date |
---|---|
US6986027B2 (en) | 2006-01-10 |
DE10121792A1 (de) | 2001-12-06 |
US20020023204A1 (en) | 2002-02-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE10121792C2 (de) | Universelle Ladeadresse/Wertevorhersageschema | |
DE10084556B4 (de) | Optimierte Ausführung von statisch sehr wahrscheinlich vorhergesagten Verzweigungsbefehlen | |
EP0010198B1 (de) | Vorrichtung zur Steuerung des Seitenaustausches in einem Datenverarbeitungssystem mit virtuellem Speicher | |
DE4447238B4 (de) | Schaltungsanordnung und Verfahren zum Gewinnen von Informationen zur Verzweigungsvorhersage | |
AT389772B (de) | Datenverarbeitungsanordnung mit einem programmspeicher und einer schutzeinheit | |
DE112007001397B4 (de) | Verfahren zum Vorabholen von Daten | |
DE69838966T2 (de) | Prozessor zur Ausführung von hochwirksamen VLIW-Befehlen | |
DE69734403T2 (de) | Verfahren im bezug auf die behandlung von konditionellen sprüngen in einer multietagen-pipeline-struktur | |
DE102014000372A1 (de) | Verbesserte steuerung des prefetch-traffics | |
DE2630323A1 (de) | Datenspeichereinrichtung | |
DE19527031A1 (de) | Verbesserte Vorrichtung zum Reduzieren von Verzögerungen aufgrund von Verzweigungen | |
DE3131341A1 (de) | "pufferspeicherorganisation" | |
EP0048767A1 (de) | Prioritätsstufengesteuerte Unterbrechungseinrichtung | |
DE10015675A1 (de) | Spekulative Auswahl von heißen Spuren in einem dynamischen CACHE-Übersetzer mit geringem Aufwand | |
DE19526008A1 (de) | Vertikal partitionierter, primärer Befehls-Cache-Speicher | |
DE2403039C2 (de) | Einrichtung zur Befehlsausführung in einer adressenerweiterten elektronischen Datenverarbeitungsanlage | |
DE112004002505T5 (de) | Entkoppeln der Anzahl der logischen Threads von der Anzahl der gleichzeitigen physischen Threads in einem Prozessor | |
DE2854400A1 (de) | Anordnung zum wechsel zwischen verzahnt zu verarbeitenden programmen | |
DE60036667T2 (de) | Prozess zur Seitenfreigebung für virtuellen Adressierungsmechanismus | |
DE2906685A1 (de) | Instruktionsdecodierer | |
AT501213B1 (de) | Verfahren zum steuern der zyklischen zuführung von instruktionswörtern zu rechenelementen und datenverarbeitungseinrichtung mit einer solchen steuerung | |
DE4342521C1 (de) | Verfahren und Anordnung zur Expansion komprimierter Daten | |
DE19926580C2 (de) | Verfahren und Vorrichtung zur Vorhersage von Sprungzieladressen | |
EP0818728B1 (de) | Verfahren zur Behandlung von indizierten Sprüngen bei einer Codetransformation | |
DE10232488B4 (de) | Verfahren und Prozessor zur Verzweigungsvorhersage mit zwei parallel durchsuchten Verzweigungsziel-Speichern |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8304 | Grant after examination procedure | ||
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Representative=s name: DUSCHER, R., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 7 |
|
R081 | Change of applicant/patentee |
Owner name: INTEL CORPORATION (N.D.GES.D. STAATES DELAWARE, US Free format text: FORMER OWNER: INTERNATIONAL BUSINESS MACHINES CORPORATION, ARMONK, N.Y., US Effective date: 20130529 Owner name: INTEL CORPORATION (N.D.GES.D. STAATES DELAWARE, US Free format text: FORMER OWNER: INTERNATIONAL BUSINESS MACHINES CORPORATION, ARMONK, US Effective date: 20130529 |
|
R082 | Change of representative |
Representative=s name: BOEHMERT & BOEHMERT ANWALTSPARTNERSCHAFT MBB -, DE Effective date: 20130529 Representative=s name: BOEHMERT & BOEHMERT, DE Effective date: 20130529 |
|
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |