DE10084439T1 - Zweistufiges chemisch-mechanisches Verfahren zum ebnen für Damascene-Strukturen auf Halbleiter-Wafern - Google Patents

Zweistufiges chemisch-mechanisches Verfahren zum ebnen für Damascene-Strukturen auf Halbleiter-Wafern

Info

Publication number
DE10084439T1
DE10084439T1 DE10084439T DE10084439T DE10084439T1 DE 10084439 T1 DE10084439 T1 DE 10084439T1 DE 10084439 T DE10084439 T DE 10084439T DE 10084439 T DE10084439 T DE 10084439T DE 10084439 T1 DE10084439 T1 DE 10084439T1
Authority
DE
Germany
Prior art keywords
leveling
semiconductor wafers
mechanical process
damascene structures
stage chemical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10084439T
Other languages
English (en)
Inventor
Thomas Laursen
Krishna P Murella
Malcolm K Grief
Sanja Basak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Speedfam IPEC Corp
Original Assignee
Speedfam IPEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Speedfam IPEC Corp filed Critical Speedfam IPEC Corp
Publication of DE10084439T1 publication Critical patent/DE10084439T1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE10084439T 1999-03-29 2000-03-23 Zweistufiges chemisch-mechanisches Verfahren zum ebnen für Damascene-Strukturen auf Halbleiter-Wafern Withdrawn DE10084439T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/280,767 US6555466B1 (en) 1999-03-29 1999-03-29 Two-step chemical-mechanical planarization for damascene structures on semiconductor wafers
PCT/US2000/007652 WO2000059031A1 (en) 1999-03-29 2000-03-23 Two-step chemical-mechanical planarization for damascene structures on semiconductor wafers

Publications (1)

Publication Number Publication Date
DE10084439T1 true DE10084439T1 (de) 2002-06-06

Family

ID=23074547

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10084439T Withdrawn DE10084439T1 (de) 1999-03-29 2000-03-23 Zweistufiges chemisch-mechanisches Verfahren zum ebnen für Damascene-Strukturen auf Halbleiter-Wafern

Country Status (7)

Country Link
US (1) US6555466B1 (de)
JP (1) JP4750948B2 (de)
KR (1) KR100630293B1 (de)
DE (1) DE10084439T1 (de)
GB (1) GB2363680A (de)
TW (1) TW440948B (de)
WO (1) WO2000059031A1 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7041599B1 (en) * 1999-12-21 2006-05-09 Applied Materials Inc. High through-put Cu CMP with significantly reduced erosion and dishing
US20020023715A1 (en) * 2000-05-26 2002-02-28 Norio Kimura Substrate polishing apparatus and substrate polishing mehod
US6609950B2 (en) * 2000-07-05 2003-08-26 Ebara Corporation Method for polishing a substrate
DE10053467A1 (de) * 2000-10-27 2002-05-16 Infineon Technologies Ag Verfahren zum Bilden von Kontakten in integrierten Schaltungen
KR20040000009A (ko) * 2002-06-19 2004-01-03 주식회사 하이닉스반도체 플라티늄-ｃｍｐ용 용액
US20040077295A1 (en) * 2002-08-05 2004-04-22 Hellring Stuart D. Process for reducing dishing and erosion during chemical mechanical planarization
US20040209066A1 (en) * 2003-04-17 2004-10-21 Swisher Robert G. Polishing pad with window for planarization
JP2004363524A (ja) * 2003-06-09 2004-12-24 Matsushita Electric Ind Co Ltd 埋め込み配線の形成方法および半導体装置
US20060089093A1 (en) * 2004-10-27 2006-04-27 Swisher Robert G Polyurethane urea polishing pad
US20060089094A1 (en) * 2004-10-27 2006-04-27 Swisher Robert G Polyurethane urea polishing pad
US20060089095A1 (en) * 2004-10-27 2006-04-27 Swisher Robert G Polyurethane urea polishing pad
US20080242106A1 (en) * 2007-03-29 2008-10-02 Anuj Sarveshwar Narain CHEMICAL MECHANICAL POLISHING METHOD AND APPARATUS FOR REDUCING MATERIAL RE-DEPOSITION DUE TO pH TRANSITIONS
US20110132868A1 (en) * 2009-12-03 2011-06-09 Tdk Corporation Polishing composition for polishing silver and alumina, and polishing method using the same
CN102615584A (zh) * 2011-01-31 2012-08-01 中芯国际集成电路制造(上海)有限公司 一种化学机械研磨的方法

Family Cites Families (21)

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Publication number Priority date Publication date Assignee Title
DE3735158A1 (de) 1987-10-16 1989-05-03 Wacker Chemitronic Verfahren zum schleierfreien polieren von halbleiterscheiben
US5244534A (en) * 1992-01-24 1993-09-14 Micron Technology, Inc. Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs
JPH07263537A (ja) * 1994-03-16 1995-10-13 Sony Corp トレンチ素子分離の形成方法
JPH08139060A (ja) * 1994-11-04 1996-05-31 Ricoh Co Ltd 半導体装置の製造方法及び化学的機械研磨装置
US5478436A (en) * 1994-12-27 1995-12-26 Motorola, Inc. Selective cleaning process for fabricating a semiconductor device
JP3557700B2 (ja) * 1995-03-24 2004-08-25 富士通株式会社 配線形成方法
JP2850803B2 (ja) 1995-08-01 1999-01-27 信越半導体株式会社 ウエーハ研磨方法
JP3230986B2 (ja) * 1995-11-13 2001-11-19 株式会社東芝 ポリッシング方法、半導体装置の製造方法及び半導体製造装置。
US5573633A (en) 1995-11-14 1996-11-12 International Business Machines Corporation Method of chemically mechanically polishing an electronic component
US5676587A (en) * 1995-12-06 1997-10-14 International Business Machines Corporation Selective polish process for titanium, titanium nitride, tantalum and tantalum nitride
DE69719847T2 (de) 1996-05-16 2004-02-05 Ebara Corp. Verfahren und Vorrichtung zum Polieren von Werkstücken
JP3076244B2 (ja) * 1996-06-04 2000-08-14 日本電気株式会社 多層配線の研磨方法
KR100241537B1 (ko) 1996-06-21 2000-02-01 김영환 반도체 소자의 층간 절연막 평탄화 방법
US5854140A (en) * 1996-12-13 1998-12-29 Siemens Aktiengesellschaft Method of making an aluminum contact
EP0848417B1 (de) 1996-12-13 2004-09-08 International Business Machines Corporation Verbesserungen im chemisch-mechanischen Polieren von Halbleiterscheiben
US5801094A (en) 1997-02-28 1998-09-01 United Microelectronics Corporation Dual damascene process
US5934980A (en) * 1997-06-09 1999-08-10 Micron Technology, Inc. Method of chemical mechanical polishing
US6001730A (en) * 1997-10-20 1999-12-14 Motorola, Inc. Chemical mechanical polishing (CMP) slurry for polishing copper interconnects which use tantalum-based barrier layers
GB2326523B (en) * 1997-11-24 1999-11-17 United Microelectronics Corp Chemical mechanical polishing methods using low ph slurry mixtures
US6004188A (en) * 1998-09-10 1999-12-21 Chartered Semiconductor Manufacturing Ltd. Method for forming copper damascene structures by using a dual CMP barrier layer
US6083840A (en) * 1998-11-25 2000-07-04 Arch Specialty Chemicals, Inc. Slurry compositions and method for the chemical-mechanical polishing of copper and copper alloys

Also Published As

Publication number Publication date
TW440948B (en) 2001-06-16
US6555466B1 (en) 2003-04-29
GB2363680A (en) 2002-01-02
JP4750948B2 (ja) 2011-08-17
JP2003517720A (ja) 2003-05-27
KR100630293B1 (ko) 2006-09-29
WO2000059031A1 (en) 2000-10-05
GB0125570D0 (en) 2001-12-19
KR20010108429A (ko) 2001-12-07

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Legal Events

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8139 Disposal/non-payment of the annual fee