CS231702B1 - Connected to record logic signals - Google Patents

Abstract

The circuit for recording logical signals is intended to achieve increased reliability of the function of recording logical signals in conditions of disturbing environmental influences, especially in industrial applications of single-purpose control machines. The essence of the circuit consisting of at least one signal line is that the first input of the first signal line is connected to the first input of the first memory circuit and to one input of the combinational logic circuit, where the output of the combinational logic circuit is connected to the input of the discrimination circuit. The output of the discrimination circuit is connected to the second input of the first memory circuit, and the output of the first memory circuit is connected to the first output of the first signal line.

Description

The essence of the connection of at least one signal line is that the first input of the first signal line is connected both to the first input of the first memory circuit and to one input of the combinational logic circuit, where the output of the combinational logic circuit is connected to the discriminant circuit input.

The output of the discriminator circuit is coupled to the second input of the first memory circuit, and the output of the first memory circuit is coupled to the first output of the first signal line.

CC

The invention relates to circuitry for recording logic signals in electronic, current and other systems, in particular in the field of direct control of production processes or production facilities.

Signal recording circuits are known, consisting of logic circuits, for example binary memories, flip-flops, and the like, wherein there is one logic circuit with a parity function to record each individual signal.

The disadvantage of these wiring is the fact that after a longer time delay of the arrival of two groups of write signals, for example, due to environmental disturbance and the like change the state of these logic circuits, the effect of a written group of signals in terms of time sequence of these signals in this one group is distorted will occur, for example, when the written signals affect the next flow of logical signals in a digital machine and the like.

These drawbacks are overcome by a circuit according to the invention, comprising at least one signal line, characterized in that the first input of the first signal line is connected to both the first input of the first memory circuit and the input of the combinational logic circuit, connected to the input of the discriminator circuit, the output of the discriminator circuit is coupled to the second input of the first memory circuit, and the output of the first memory circuit is coupled to the first output of the first signal line.

The memory circuit is any flip-flop, binary memory and the like. The selected logic level signal that arrives at the first input, preferably the recording input, causes the selected logic level signal to be excited at the output. Similarly, a selected logic level signal that arrives at the second input, preferably a lubrication input, causes the output signal to disappear.

A multiple logic input or a multiple erase input assumes a simple logical functional dependence of the signals on. elementary recorders, or on elementary erase targets, for example, a logical sum function, a logical product, and the like.

A timing circuit is considered to be any logic circuit with the property that the selected logic level signal arriving at the input causes the selected logic level signal to be excited at the output for a predetermined period of time.

Multiple input assumes a simple logical functional dependence of the signals on elementary inputs, for example the function of logical sum, logical product and the like. The time circuit thus considered can be understood as a time memory with a predetermined amount of time duration of the output signal.

Any combination logic circuit with an input, an output, a control input having the property that the passage of the signal from the input to the output is released by the action of the selected logic level signal on the control input is considered as a gate.

For example, a combinational logic circuit with a logic conjunction function relative to the input and the control input may act as a gate. The combination circuit is preferably a circuit having a function of logic sum, based on the first input, on the second input, or on the next input, or on the next input of the combination circuit.

A discriminating circuit is any arbitrary logic circuit, with the property that a signal of a selected logic level, preferably a logic one level, for example, an increase in a voltage signal from a logic zero value to a logic one value input, causes the selected logic level output signal which lasts at this output for a predetermined period of time, the length of which is determined by the properties e by adjusting this discriminating circuit.

The advantage of the circuitry according to the invention is that it enables to achieve increased reliability of the logical signal recording function, especially in intermittent operating mode, where the signals in groups with different time order come at longer time intervals to the circuit inputs for recording.

The advantage of wiring is increased resistance to environmental disturbances, especially in industrial applications in dedicated control systems, achieved by purposefully bringing the memory circuits always at the beginning of the arrival of a particular group of signals into a predetermined initial state and subsequent positioning to the same state.

Another advantage is that the signals at the wiring outputs achieve the correct control effect at the right time, even where the controlled member reacts to the beginning of the signal at the output, in the event that in the longer time interval false flip of memory circuit.

The circuit according to the invention is illustrated by way of example in the accompanying drawing, in which Fig. 1 is a basic circuit, and Fig. 2 is a modified circuit with additional logic circuits.

In FIG. 1, a first input S connected directly to a first input ¹ p) of the first memory circuit Pj whose output <Pi> is connected to the first output circuit, the second input of S2 is directly connected to the first input ¹ P2 of the second memory circuit R whose output <P ₂ > is connected to the second output X _{2 of the} wiring, the other input is connected directly to the first input of the next memory circuit P, whose output <P,> is connected to the other output X-, the wiring »» l ni · 1 ** W in sequence the input is connected directly to the first input p ^ of the next in the memory circuit P _N , whose output% 1P _N > is connected to the next in the output X ^ of the wiring.

1 shows a combination logic circuit K whose inputs k ₍ , k ₂ , k ^, ..., k ^ are connected to the inputs S,, S-, S, ..., S _{N of the} circuit, and whose v.vstup <K> not connected via discriminatory iO '2 amination D circuit and a second input p ^ of the first memory circuit, a second input P ₂ of the second memory circuit P _2, the second input ² p ^ dalěího memory circuit P ^ , with a second input of the next in the memory circuit P1.

The inputs of the combination circuit K are connected to the wiring inputs such that the first wiring input S, the wiring is connected to the first input kj, the second wiring input S ₂ is connected to the second input k ₂ , the other wiring input is connected to the other input k ^, in turn, the wiring input is coupled to another in the order k k of this combination circuit K, whose input <K> is connected to the input d of the discriminant circuit D.

Output <D> discriminating circuit is connected to the periphery Pi of a second input ,, P ₂ of the second memory storage circuit P ^, a second input of the next _N ^ p *

a second input p, a first memory circuit P ₂ , with a second input further in the memory circuit P 1.

In another exemplary embodiment of FIG. 2, the ancient logic circuit Hp T, with a first input

1.

is the first input S, connected via the first input <P.> is connected to the first output X consists of the first gate H, that this first input S.

Ρ] of the first memory circuit Pp whose circuit output, the first additional logic circuit connected in cascade in sequence so connected to the input h of the first gate Hp whose output <H,> is from the first time circuit of the first memory circuit P ,, the second input S ~ is connected via a second additional logic ob1 —1 _in -A

H ₂ , T _? with the first input p _? the second memory circuit P ₂ , whose output <P ~> is connected ?.

wherein the second additional logic circuit consists of a second connected in cascade so that the second whose output <T ₂ > is connected to the first input of the second memory is to the input t. of the first time circuit Τ whose output <T.> is connected with first input 1 - ¹

If the second output X _{2 is} connected:

gate H ₂ from the second timing circuit T ₂ input S ₂ is connected to the input h ₂ of the second gate H ₂ whose output _<H2> is connected to input T ₂ of the second timing circuit RS, dumping perimeter P _o of the entry Sg is connected via another additional logic circuit Hg, Tg, whose output <P,> is connected to another high input 'p

The Xg circuit, which additional logic circuit consists of another cascade Hg of a wider timing circuit connected in sequence so that this additional input S of the next memory circuit P1, only with the input circuit Tg »circuit Pg.

whose output <H,> is connected to input t, _ - .. J ... i whose output <'I ^> is connected to the first input pg of another memory

Next, the input Sg is connected via the next additional logic circuit Hg, Tg to the first input ¹ p _{R of the} next in the memory circuit Pg, whose output <Pg> is connected to the next in the output ^X N connection, the next in sequence the additional logic circuit consists of another in the order of gate Hg and another in the order of time circuit Tg connected in cascade so that this next in sequence input Sg is connected to input h ,, another in order of gate Hg, whose output <Hg> It connected to an inlet next in order tg Time Tg circuit whose output <Tg> is connected to first input pg next in order and the storage circuit ⁵ ^. ·

In addition, FIG. 2 shows a combination logic circuit K whose inputs kg, _k2 , kg, ..., kg are connected to inputs S1, S1, Sg,. , Sg involved, and whose output <K> is connected via a discriminating circuit D to a second input of the first memory circuit Pj second input ^ p second memory circuit P _2, a second input * ^ pg another memory circuit PG, the second input of the next in order of the memory circuit Pg.

The inputs of the combination circuit K are connected to the wiring inputs such that the first wiring input Sg is connected to the first input k ^, the second wiring input is connected to the second input k ^, the next wiring input Sg is connected to the next input kg, The Sg circuit is connected to the next in the order of the input kg of this combination circuit K, the outputs of which K>

it is connected to the input d of the discriminant circuit D, whose output <D> is connected to the second input2 * - 2 ⁱⁿ p p, the first memory circuit Ρ ,, with the second input p _{2 of the} second memory circuit Pg, with the second input% g of another memory circuit Pg, with a second input% g of the next in the memory circuit Pg, and longer with control input h ^ of the first gate Η, with control input h ^ of the second gate H ₂ , with control input hg of the next gate Hg, with control input hg of the next gate sequence Hg.

The wiring function of the exemplary embodiment of FIG. 1 is such that the signal that arrived at the first input passes to the first input p, the first memory circuit P1, and the first input kj of the combinational logic circuit K.

In combination logic circuit K with logic sum function, this signal passes to its output <K> and longer to input disk of the discriminant circuit D, where the generation of the signal, for example from logic zero to logic one, causes the signal to be excited at input <D> this discriminatory circuit for a predetermined period of time.

The signal at the output <D> of this discriminant circuit L passes to the second input ^ p ^ of the first memory circuit Ρ, to the second input of the second memory circuit P-, to the second

O in I2 -η— v input pg of the next memory circuit Pg, to the second input p _{Js [} next in the order of memory circuit Pg.

It is assumed that the function of the memory circuits is such that with the excitation of the first input and the second input, the logical function of the signal prevails on the second input, ie the erasing predominates.

As a result, for the duration of the signal at the input <D> of the discriminant circuit D, signal excitation at the output <P ₍ > of the first memory circuit Pg) is prevented, although it is already excited by the signal at the first input 'pp and similarly , another, next in memory order.

23Π02

Only when the signal at the output <D> of this discriminating circuit D disappears is the signal from the inputs S, Sg, S ^, ... connected to the respective memory circuits.

P ₍ , Pg, Pj ..... Pjp, this record always following a previously erased state of these memory circuits.

in the exemplary embodiment of FIG. 2 is such that the signal that, at, and at the first input to, the.

The sel on the first input passes to the input h _{1 of the} first gate H of the logic circuit K. '

For a combination logic circuit K with a logic sum function, this signal is not passed to its output <K> and further to the input of the discriminant circuit D, where the generation of the signal, for example from logical zero to logic one, causes the circuit for a predetermined period of time.

The signal at the output <D> of this discriminant circuit 6 passes to the second input p, the first memory circuit Ρ, to the second input ² p _{2 of the} second memory circuit Pg, to the second input ² ρ ^ of the next memory circuit Pj, to the second input ² pjj in the order of the memory circuit Pjj.

Due to the flip function of the memory circuits, a preselected, for example, erased state of the memory circuits is achieved.

The signal at the output <D> of the discriminant circuit D goes further to the control input Hj of the first gate H ₍ , to the control input H2 of the _second gate Hg, to the control input Hj of the next gate Hp to the control input of the next gate H11.

gate for signals from inputs S ₁ , Sg, Sj hjj gate Hj

Due to the logic function, the passage of these, Sjj wiring, or from the inputs h ₍ , hg, hj,. Hg, Hj ..... Hj ^ ňa and their output ^ H ^, <H ₂ > is closed for the duration of this signal. , <H ^>,

Only when the signal at the output <E> of the discriminating circuit 6 disappears, the signals pass through these gates from their inputs to their outputs.

For example, the signal at the first input S, the wiring, or the signal at the input hj of the first gate <H ^> passes to its output and further to the input t _{1 of the} first time circuit ^- ₁ ,.

Due to the logic function of the time circuit used, this signal at input t causes the signal to be selected at a logical level at the output <T ₁ >, preferably a one-logical log, for a predetermined period of time. This logic signal goes further to the first input ¹ Pj of the first memory circuit Pj, causing the signal to be excited at its output <Pj>, and thus to the first output X1 of the wiring.

The signal flow from the second input Sg, the next input Sj, the next in the order of the input connection to the second output Xg, the next output Txg, the other in the order of the output X _N connection is quite similar.

It is assumed a relatively long signal duration at the inputs S ₁ , S ₂ , Sj, ..., wiring, and a corresponding signal duration at the outputs Xj, X ₂ , Xj, ..., X ^ wiring "or such insensitivity to these signals at the outputs that potentially transient signals due to different, when the reaction of the circuits used can be completely neglected. This assumption justifies the idealized idea of the immediate reaction of the circuits used, regardless of their physical nature.

The circuitry of the invention finds its well-established application in dedicated control systems composed of logic circuits where it increases the operational reliability of circuits responsive to input signals, for example sensor signals, production device status signals, and the like.

23Π02

In particular, when starting a production cycle with a time delay from the previous production cycle, the memory circuits are brought into the initial state or another default preselected state, and then the actual input signals are input to the respective penetrant circuits.

SUBJECT OF THE INVENTION

Claims (2)

A circuit for recording logic signals, comprising at least one signal line, characterized in that the first input (S1) of the first signal line is connected both to the first input ('p') of the first memory circuit (P1) and to one input (k ₍ ) of the combinational logic circuit (K), where the output (<K>) of the combinational logic circuit (K) is connected to the input (d) of the discriminant circuit (D), the output (<D>) of the discriminant circuit (D) is connected to the second input (p ₁ ) of the first memory circuit (P 1), and the output (<P _t >) of the first memory circuit (P 1) is coupled to the first output (X 1) of the first signal line. 2. Circuit according to claim 1, characterized in that the first input (S ^) of the first signal lines connected to the first input ⁽¹ p) of the first memory circuit (P) via a first additional logic circuit comprising a first gate (Hj) and a first time circuit (T1) connected in cascade in succession, the output of the first gate (11j) being connected to the input (t)) of the first time circuit (T1), and the control input (Hj) of the first gate (H1) it is connected to the output (<D>) of the discriminant circuit (D). 2 drawings 23U02 & }, Yeah £ Α X ν ΓΜΟ Λ