CS227458B1 - Method of planarizing surface of integrated circuits with dielectric insulation - Google Patents

Description

(54) Method of surface planarization of integrated circuits with dielectric insulation

The invention relates to a method of planarizing the surface of integrated circuits with dielectric insulation.

The use of dielectric isolation technology makes it possible to significantly increase integration density and circuit speed. However, the formation of oxide insulations is accompanied by the formation of oxide growths at the edges of isolated areas, the so-called bird heads. As a mask for selective isolation oxidation, a layer of silicon nitride Si 4 N 4 formed by chemical deposition under reduced pressure is most often used.

Selective oxidation and the nitride mask create tensions along the edge of the insulating oxide, which, particularly in the case of an embedded insulating oxide, can produce a strong contusion of silicon in the form of a dense dislocation network. This stress is the sum of the intrinsic tensile stress of the nitride layer and the compressive stress of the embedded oxide insulation.

The condition for proper functioning of the integrated circuits is the creation of a defective structure, which is ensured by the use of thin nitride layers and an oxidation temperature T »1000 ° C.

These conditions, however, cause an increase in the size of the bird's heads. For a silicon nitride thickness x - - 100 nm, the oxidation temperature T = 1000 ° C is the head height H = · 0.8 to 1 µm.

Surface irregularities of these dimensions already significantly reduce the accuracy of the photolithographic process, especially when creating the first e of the second metallization network and the contacts between the first and second metelization levels. On bird heads, the quality of the dielectric insulation between the first and second metelization levels is reduced. Finally, large surface irregularities tend to reduce the reliability of integrated circuits due to the hot coverage of large deficits by the metallization network.

227458 2

Reducing the size of the bird's head is currently řeěí several ways, the disadvantage is the formation of the crystallographic defects in the edges of isolated areas in cases where the use of thick layers of silicon nitride Si ^ N ^ for a longer process, it is difficult preparation of thin films of silicon dioxide Si0 ₂ and silicon nitride and low reproducibility of reactive ion etching of silicon nitride

In the case of the use of high-frequency stripping, the disadvantages include a time-consuming process and a multiple change in the stripping rate with the gradual stripping of thermal SiO2. The difficulty in determining the corrosion of the non-selective silicon oxide and the time consuming process is a disadvantage of the multiple oxidation planarization process.

The above-mentioned drawbacks are eliminated by the method of planarization of the surface of integrated dielectric insulated circuits according to the invention, which consists in applying a positive photomolecule to silicon substrates followed by plasmachemical etching of substrates deposited on either a high-frequency electrode or grounded electrode or apparatus with plenum-parallel electrodes in a gas stream of tetrefluoromethane with 0.1 to 30% oxygen.

An advantage of the process according to the invention is the formation of a plenary surface, thereby eliminating the problems associated with the surface irregularities that form at the edges of the insulated areas. The process is productive because the process takes about one hour. By suitably selecting the composition of the etching composition, the reproducibility of the process can be ensured.

The process according to the invention is illustrated by way of example with reference to FIGS. 1 and 2, in which a silicon substrate 1 is shown which is coated with a positive photo-paint 6 having a thickness of .mu.m. This is followed by drying at 180 ° C for 20 minutes in air. During this drying, the bird heads are cured. Flow rate CF ^ - 100 cm ^ / min, 0 ₂ - 10 ceP / min, high-frequency etching power is 500 W, frequency 60 kHz. The substrate temperature is 40 ° C and the etching time is selected from 4 to 7 minutes.

The silicon substrates 11 lie on a grounded electrode. The etching rate of the positive photoresist ⁸ second thermal silica or bird head 2 D® from these etching conditions, approximately the same, so there is a gradual uniform removal of the surface layer, the etching is terminated when tloušlce photoresist Í. »Ý0,3 + 0.4« um . The remaining photo-pressure 2 is removed, for example, in the oxygen plesmS.

The surface planarization method according to the invention can be included in the process of manufacturing a transistor and bipolar and unipolar integrated circuits using embedded dielectric insulation technology.

Claims (1)

Method of planarization of the surface of integrated circuits with dielectric isolation, characterized in that after applying a positive photo-paint (2) to the silicon substrates (1) and drying it is followed by pleamochemical etching of substrates deposited either on the high-frequency electrode or on the grounded electrode or electrodes in a mixture of tetrafluoromethane gases with 0.1 + 30% oxygen.