CS219484B1 - Real-time microprocessor bus monitoring - Google Patents

Abstract

The invention relates to a circuit circuit for expanding the function of an analyzer. The circuit is intended for diagnostics in software and hardware of microprocessors. The essence of the invention is that the monitored microprocessor buses are connected to a fast RAM memory, connected to a modulo N counter, while the data outputs of the fast RAM memories are connected to the analyzer microcomputer, the outputs of which are connected via two gates to a modulo N counter. The circuit is intended for automatic verification of parameters of microprocessor systems.

Description

The invention relates to a circuit for real-time monitoring of microprocessor bus states. It is designed especially for program analysis with the possibility of tracing back the n-steps of the crawled program.

Microprocessor bus analyzers are used in electronic devices designed to detect the status of microprocessor systems. The analyzer basically consists of input registers connected in a circuit combination with timing circuits, comparators, delay and sequential circuits. The buses are connected in parallel to the keyboard microcomputer. This device detects data at the specified address of the program, where it is possible to trace the program. Monitoring each program backward step is essentially a measurement in different time loops. When analyzing microprocessor buses, it is important to track backward, especially the sequence of program steps, not only in successive time loops but in one time loop, which is not possible by the prior art.

This disadvantage is overcome by real-time monitoring of microprocessor bus statuses, according to the invention, which is based on the fact that microprocessor buses are connected to fast RAMs, which are address inputs associated with a modulo N counter and data outputs and control input with a keyboard-based microcomputer. , which is part of the analyzer, which is connected to the inputs of the second gate with two outputs, the output of which is connected to the second input of the first gate, whose first input is connected to the microcomputer output and its output to the input of the modulo N counter.

The main advantage of the connection is fast analysis of the required program from microprocessor buses in real time with the possibility of monitoring N previous steps in one time loop.

BRIEF DESCRIPTION OF THE DRAWINGS The invention is illustrated in greater detail in the drawing, in which a block arrangement is shown.

The circuit shown in the figure consists of a microprocessor bus 7 coupled to the 3 RAMs. These fast RAMs 3 are connected to the address inputs AD, the counter 4 modulo > N and the data outputs DT and the control input 12 to the microcomputer 2, which is part of the microprocessor bus analyzer 1. The microcomputer 2 is connected both to the keyboard 11 for triggering the HIS and HIS 1 signals and to the output 10 of the POS signals with the first input of the first gate 5 and the second input connected to the output of the second gate B. 9 of the microprocessor bus analyzer 1 are connected to the inputs of the second gate 6.

The wiring works as follows:

First, the microprocessor bus analyzer 1 is set to the default position in the selected mode. Both the addresses and the data begin to change on the buses 7 analyzed. Fast RAM 3, which is set to read mode with the R signal, sequentially records N of the last addresses and data. The modulo N counter 4 registers, depending on the pulses of the DIS-HIS signals passing through both the S, 6 gates, so each pulse of this signal announces new data and addresses on the buses 7 analyzed. 3 RAM, so that the N value and N + 1 are always written. the value is written instead of the first value. In this way, the last N values of the monitored program are always written in the 3 RAM memory. If the set address matches the address being searched for on the bus 7 being analyzed, the microprocessor bus analyzer 1 sends a DIS signal that disables the second gate 6 and hence the DIS-HIS signal. By pressing the 11-HIS keypad 1, a POS signal is programmed in the microcomputer 2. This signal moves the modulo N counter 4, which addresses the 3 RAM. At the same time, the signal 3 switches the RAM 3 to read mode. The microcomputer 2 reads the stored value from the addressed RAM memory cell 3, writes to its RAM and outputs the POS signal again, and repeats the process until all N values are recorded in the microcomputer 2 memory. Press the 11-HIS keypad to display the first value, press it again to display the next value, etc. until the Nth. Subsequent pressing will display the first value, etc.

The circuit is designed especially for use in measuring technology for automatic verification of microprocessor system parameters.

Claims (1)

SUBJECT A real-time state-of-the-art microprocessor bus monitoring circuit, characterized in that the microprocessor buses (7) are connected to fast memories (3) of RAM that are address inputs (AD) associated with a modulo N counter (4) and data outputs (DT) with a control input (12) with a microcomputer (2) with a keyboard (11), which is part of the invention of the analyzer (1), which is connected via two outputs (8, 9) to the inputs of the second gate (6) a second input of the first gate (5), the first input of which is connected to the output (10) of the microcomputer (2) and its output to the input of the counter (4) modulo N.