SU1605214A1 - Device for monitoring process variables - Google Patents

Abstract

The invention relates to the field of automation and computing and can be used to monitor discrete sensors of the state of objects. The purpose of the invention is to increase the reliability of the control. The device contains elements OR 3, 11, 34, elements AND 8,14,16,27,28,21,35, registers 4,29,31, shift register 12, block 17 of elements OR, adder 13 modulo two, triggers 10 , 15, pulse counter 9, reversible counter 30, delay elements 25.26, comparison circuits 32.33. The introduction of new elements and logical connections expands the field of application of the device and allows to increase the reliability of the control parameters. 1 il.

Description

The invention relates to automation and computing and can be used to monitor the sensors of the state of objects.

The purpose of the invention is to increase the reliability of the control.

The drawing shows a diagram of the proposed device.

The device contains inputs of 1 data, JL send block, first element OR 3, register 4, bus 5 clock pulses, output 6 of register 4, driver 7 pulses, first element 8, pulse counter 9, first trigger 10, second element OR 11, shift register 12, adder 13 modulo two, third element AND 14, second trigger 15, second element AND 16, block of elements AND 17, output 18 of the service request, service permission input 19, information outputs of the device 20, a fast element And 21, the first mode setting input 22, the output of the p of that element, and 23, the output of the second element OR 24, the first delay element 25, the second delay element 26, the fourth 27 and fifth 28 elements AND, the first register 29 of settings, the reversible counter 30, the second register 31 of settings, the first 32 and second 33 of the comparison circuit, the third element OR 34 , the seventh element And 35, outputs Norm 36, Avari 37, the second mode setting input 38, warning output 39.

The device works as follows.

The device periodically polls and monitors the states of discrete sensors. The removed information from the sensors enters in a parallel code in the register 4 of the block 2 of the conjugation.

The processing of incoming information is performed during one cycle. The device operation week is set by counter 9, which is configured for a number of clock pulses equal to the number of monitored sensors. When the device is turned on, all the memory elements are reset, and in register 4 a parallel code is written to its information inputs from the sensor outputs 1. For simplicity, the initial setting circuit is not shown.

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To pass the clock pulses through the AND 8 element, its inverse input must have a zero potential, which is formed at the output of the AND 16 element and supplied through the AND 21 element as a result of zeroing of the trigger 15 on the initial installation signal during power-up or on arrival at its R- the input from the control input 19 of a single pulse during the servicing of this device, if a voltage is present at the input 22 of the device. In this case, the clock pulses pass through the element And 8, which allows the device to process the information received from the monitored sensors, when receiving a new information, and trigger the trigger 15, resulting in the trigger 10 on the output element And 16 zero potential is replaced by a single one. This signal, if a voltage is present at the input 22 of the device, blocks the passage of clock pulses through the element 8. At this time, the device is in standby mode, i.e. it does not at this time perform a census of regular information from register 4 to register 12. Only after a single impulse arrives at input 19, when trigger 15 clears, and at output of AND 16 element, a single signal changes to zero, the clock pulses again begin to pass through -element And 8, which allows the device to proceed to the next information processing cycle. In the absence of voltage on the device input 22, the blocking signal does not pass to the inverted input of the element AND 8 and the device operates in continuous mode, fixing the number of healthy objects — the control in the reversing counter 30,

Information can be recorded at the initial moment of time by a signal of the initial setup or by using a single pulse generated by the trigger 10. The latter produces the specified single pulse using two control pulses .- which are formed in the pauses of the clock pulses at the output of the driver of the 7 pulses. In this case, the beginning of the recording of information in the register 4 is delayed by the time of processing.

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counter 9. Clock pulses formed at the output of element And 8 fill pulse counter 9 and pass to the control input of register 4. As a result, information is read as a serial code of register A and written to register 12. This information enters also through the delay element 25 and the element 27 on the summing input of the reversible counter 30 and on the first INPUT of the adder 13 modulo two, the second input of which receives information from the last output of the shift register 12. The same information is supplied through the delay element 26 and, the AND element 28 to the subtractive input of the reversible counter 30.

With the help of adder 13 modulo two, the received information (current) is compared with the previously issued information stored in register 12 If at least one of these bits of information is unequal, the output signal of adder 13 is a single signal that (if there is a clock pulse at the second input of the element And 14), having passed the element And 14, switches the trigger 15 to the one state, and also passes through one of the elements 27 and 28 to the corresponding input of the reversing counter 30, adding to its content or. the combination of signals on the first inputs of AND gates 27 and 28.

At the output of the trigger 15, a single signal is then turned on, resulting in blocking from the first input of the element 16. After the completion of testing the counter 9, a single signal is formed at its output, and then when a pulse pulse pulse appears at the output of the clock pulse 7 10. At the output of this trigger, the zero signal changes to a single one, which zeroes the counter 9 and goes to the first control input of the first register 4, and through the OR 3 element to the second control input of this register to record the signal Alov from sensors 1. In addition, a single signal from the output of the trigger 10 through the element OR 11 post goes to the input of the element AND 16, as a result of which the latter is triggered, a single request signal for the service is generated at its output. He pic

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blunt to the output 18 of the device, to the input of the element OR 11 and through the element And 21 to the inverse of the internal element And 8, resulting in the prohibition of the passage of clock pulses through this element.

The next clock pulse, having passed the pulse shaper 7, resets the trigger 10 to the zero state. At the output of this trigger, the single signal changes to zero, with the result that register 4 is prepared for the mode of the next retrieval of information from it. At the same time, at the output of the OR 11 element, a single signal is retained due to the presence of a single signal at its second input. After this, the device, in the presence of voltage at input 22, is in standby mode for its service. Upon the arrival of a single impulse signal allowing the device to be serviced, at input 19, information is output from register 12 through block 17 of the AND elements in the form of a parallel code. Each position of this code carries information about the state of the monitored object.

Simultaneously with the acquisition of information, the trigger 15 is reset to the zero state by means of the indicated control signal. As a result, at the output of the AND 16 element, the single signal changes to zero, which leads to a change of the single signal to zero at the output of the OR 11 element and to release the blocking from the second input of the AND 21 element and, therefore, from the inverse of the first And 8 element Then the clock pulses begin to pass through this element. This means that the device proceeds to the next cycle of information processing.

If during the next cycle of recording information from sensors into register 4, their state has changed, then the information in this register will be identical to the previously issued and stored register 12. In this case, during the next cycle of processing this information, there are single signals on both inputs of the adder 13, therefore The adder 13 does not operate, the state of the counter 30 does not change and the device does not generate at its output 18 a single request signal for its service. After testing the counter 9 pulses at the trigger output

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10, a single signal is generated, which enters the interface 2 for the next recording of information from sensor 1 into its register 4. Information processing takes place during one cycle, and at the end of each cycle, the state of the sensors is checked, i.e. login information from them

4. Removing this information can begin only if the device is not in standby mode.

To ensure the passage of signals from the outputs of registers 4 and 12, when the state of the control objects changes, the reversible counter 30 from the output of the AND 14 element enters the second inputs of the And 27 and 28 elements, which is used to change the contents of the counter 30,

When the sensor enters the alarm state, the O code is removed from its output. This code in the next cycle of the device operation does not correspond to the code from the output of the register 12. At the first input of the And 28 element, a signal appears that allows the clock pulse to pass through the open element 14 on the subtracting input of the counter 30, reducing its content by one. If the sensor returns to its original position, i.e. goes from state O to 1, then in the next cycle the element And 27. will be opened and the clock pulse through the element 14 will go to the summing input of the reversible counter 30, adding one to its content.

The reversible counter 30 records a certain number of healthy control objects, which is fed to the comparison elements 32, 33 and compared with the boundary values set by the numbers in registers 29 and 31.

In registers 29 and 31, the numbers characterizing the upper and lower limits, respectively, determining the integral assessment of the state of a group of control objects, are entered. If the number of healthy control objects (sensors in state 1). recorded in the reversible counter 30, greater than the limit value set by register 29, the signal Norm from the output of the comparison circuit 32

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em on the device output 36 and through the element ШШ 34 closes the element И 35.

If this number is less than the number set in the register; 31 of the lower limit, the Avariya signal from the output of the comparison circuit 33 enters the output 37 of the device and closes the AND 35 element through the OR 34 element.

In the case when the number of serviceable objects does not exceed the established limits, there are no signals at the outputs of the comparison circuits 32 and 33 through the open element. And 35 signal A warning from the input 38 of the device passes to output 39 of the device. In the continuous control mode of an integral parameter characterized by the number of sensors in state 1, the voltage at the first input of the element And 21 is absent and the device blocking signal does not pass to the inverse input of the element And 8.

The use of four AND elements in a device, two reversible counter delay elements, two level setting registers, two comparison circuits, an AND element and new logical connections distinguishes it from the known one, since it allows continuous monitoring of the integral parameter of the sensor group and its comparison with the established levels. mi

Thus, the device, unlike the known ones, increases the reliability of the control parameters and extends the functionality by fixing the number of sensors in the group, which is not 1xs in an emergency state, and generating a comparison signal of this integral parameter with the established limits. continuously monitor the level of performance of the entire group of objects.

Claims (1)

Formula from obra.teni Device for controlling parameters, containing the first to the third elements AND, modulo two, the first and second triggers, the first and second elements OR, the first register, the pulse shaper pulse counter, the unit of the elements AND and the shift register, the inputs of the parallel input of which are device data inputs and the output is connected to the data input of the shift register and the first data input of the modulo two adder, the outputs parallel to the shift register code are connected to the input of the I group and the group of the I block, the first input of which and the reset input of the second trigger are the input The device’s information outputs, and the second input and the second data input of the modulo two are connected to the serial output of the shift register, the output of the modulo two is connected to the first input by a third its element is AND, the output is connected to the installation input of the second trigger, the output of which is connected to the first input of the second element AND whose output is the output device service request and connected to the first input of the second element OR, the output connected to the second input of the second element AND, input the pulse former and the first input of the first element I are connected to the bus clock of the device, the output of the first element I is connected to the counting input of the pulse counter, with the first input of the first OR element and with the shift register shift input, output, pulse counter overflow is connected to the data input of the first trigger, the output connected to the second inputs of the first and second elements I.Sh, the reset input of the pulse counter and the gate input of the first register, the synchronous input connected to the output of the first element OR, output pulse generator connected to the reset input of the first Tpiirrepa, to the second input of the third element I, of that, in order to increase the reliability of control, in the BBejiePUii device, the first IT of the second element will be delayed from fourth to seventh 3JUiN: enTbi And, the first and second registers of settings, reversible counter, Q the first and second circuits H and the third element IL1-1, the output of the first register and the output of the serial code of the shift register, respectively, through the first and second delay elements 11 are connected to the first inputs of the fourth and fifth AND elements, the second inputs of which are connected to the output of the third sjieNjej Ta And, and outputs respectively - to cy imiryushchyyy 0 and the subtractive inputs of the reversible counter, the outputs connected to the first inputs of the first and second comparison circuits, the second inputs connected to the outputs of the first and second 5 settings registers, respectively, the output of the first cxeML i comparison is connected to the first input of the third element IL11 and is the output device norm, the output of the second comparison circuit is connected to the second input of the third OR element and is the output of the Avari device, the third OR element is connected to the inverting input the seventh element OR, the direct input and output of which are the first input of the mode setting and the output Device warning, respectively, the first and second inputs of the output uiecToro of the AND element are respectively connected to the second input of the device mode setting, to the output of the second element I, and to the second input of the first element Egga I. five