CS215518B1 - Connection of asynchronous return counter - Google Patents

Abstract

A circuit formed from at least two four-input negated product gates and at least four stages of an asynchronous round-trip counter, each stage containing two opening circuits, for example inverters, three negated product gates, one two-state D-type flip-flop, four inputs and six outputs. The circuit has two inputs and two outputs for counting forward and backward, and two inputs for selecting the type of counter when counting forward and backward. The invention can be used primarily in control and automation technology and wherever an asynchronous round-trip counter is used, operating in decimal or binary and where its response to the leading edge of input pulses is advantageous.

Description

The invention relates to a wiring of an asynchronous reversing counter with universal use, particularly suitable for use where its reaction to the leading edge of the input pulses is advantageous. Internal wiring allows the counter to be operated either as decimal or as binary in each of the two counting directions - independently - by applying a logic one or a zero to the inputs to select the capacity citation. The wiring according to the invention is considerably simpler compared to comparable wiring.

Previously known reversible counter concepts are based on the principle of a synchronous system in which all circuits that are to change their state change it simultaneously. These synchronous circuits are considerably more complex than asynchronous circuits, but their use is necessitated by the properties of the flip-flops used to date for these purposes. The advantage of synchronous counter counters is the higher achievable working speed.

The disadvantages and disadvantages of the synchronous system are largely suppressed and give the possibility of better eliminating the potential negative influence of gambling states on the reliable operation of the circuit counter according to the invention, which relates to an asynchronous reversible counter with universal use. at least four stages of the asynchronous decadic counter, each stage of the asynchronous reverse counter having a first input for supplying counting pulses for forward and connected to the input of a first opening circuit, such as an inverter, and the first input of the first negated product gate , on the other hand, a second input intended for feeding backward counting pulses and connected to the input of a second opening circuit, for example an inverter, and to the second input of a third negative product The first output connected to the output of the first negated product gate and the second output connected to the output of the second negated product gate. The output of the first opening circuit is coupled to β by the first input of the first negated product gate and the output of the second opening circuit is coupled to the second input of the second negated product gate. The output of the third negated product gate is coupled to the TC input of the D-type two-state flip-flop whose input D is connected to its negated output C1 and at the same time to the second input of the first negated product gate. input of the second negated product gate.

According to the invention, the first wiring input for supplying the counted pulse train when counting forward is connected to the first input of the first stage of the asynchronous return counter. The second wiring input, intended to feed the counted pulse train in reverse counting, is connected to the second input of the first stage, whose first upstream transmission output is connected to the first input of the second stage, and whose second output for higher order transmission at the the reverse count is connected to the second input of the second stage. Similarly, both outputs of the second stage are connected to the corresponding two inputs of the third stage and both outputs of the third stage are connected to the corresponding both inputs of the fourth stage, the first output of which is connected to the first output of the high-order transmission. connected to the second output of the higher-order transmission circuit in reverse counting, while the first input of the first four-input negated product gate is connected to the third output of the first stage associated with the direct output Q of the D-type two-stage flip-flop inside the first stage. The second input of the first four-input negated product gate is connected to the fifth output of the first stage in the counting forward associated with the output of the first opening circuit. The third input of the first four-input negated product gate is connected to the third wiring input for selecting the counter type when counting forward. The fourth input of the first four-input negated product gate is connected to the fourth input of the second four-input negated product gate and at the same time to the third output of the fourth stage associated with the direct input Q of the D-type two-state flip-flop inside the fourth stage. The first input of the second four-input negated product gate is connected to the fourth output of the first stage associated with the negated output Q of the D-type two-state flip-flop inside the first stage. The second input of the second four-input negated product gate is connected to the sixth output of the first stage connected to the output of the second opening circuit and at the same time to the second input of the second negated product gate within the first stage. The third input of the second four-input negated product gate is connected to the fourth wiring input, designed to select the counter type when counting backward. The output of the first four-input negated product gate is connected to the third input of the second stage and at the same time to the third input of the third stage, the two third inputs being connected to the adjusting inputs P of the D-type two-state flip-flops. The output of the second four-input negated product gate is connected to the fourth input of the second stage and at the same time to the fourth input of the third stage, both of which are connected to the reset inputs C of the D-state double-state flip-flops.

The circuitry according to the invention is particularly useful in those cases where its reaction to the leading edge of the input pulses is advantageous. This connection, on the one hand, makes it possible to operate the counter either as a decimal or as a binary in each of the two counting directions, independently, by applying a logic one or zero to the counter selection inputs. less expensive.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an asynchronous return counter according to the present invention; and FIG. 2 is a diagram of one stage of a return counter.

In FIG. 1, the first wiring input 23 for supplying the counted pulse train for forward counting is connected to the first input 1 of the first stage 31 of the asynchronous return counter. Similarly, the second wiring input 24, intended to supply a counting pulse train when counting backward, is connected to the second input 4 of the first stage 31 of the return counter. The first output 10 and the second output 7 of the first stage 31 are connected to the corresponding first and second inputs of the second stage 32, whose first and second outputs are again connected to the corresponding first and second inputs of the third stage 33 and finally the first and second outputs of the third stage 33 are connected. to the corresponding first and second inputs of the fourth stage 34, whose first output 21 is connected to the first wiring output 25 and whose second output 22 is connected to the second wiring output 26. The first wiring output 25 is for forward counting and the second wiring output 26 is for counting backward. The wiring of stages 32, 33, 34 is the same as that of the first stage 31 of FIG. 2.

The fifth output 12 of the first stage 31 is coupled to the second input of the first four-input negated product gate 29, the first input of which is coupled to the third output 16 of the first stage 31, intended to indicate a forward count condition. The third wiring input 27, for selecting the counter type when counting forward, is coupled to the third input of the first four-input negated product gate 29, whose fourth input is connected to the fourth input of the second four * input negated product gate 30 and the third output 20 of the fourth stage 34 for indicating the condition. The output of the first four-input negated product gate 29 is connected to the third input 14 of the second stage 32 and at the same time to the third input 18 of the third stage 33. The third inputs 14 and 18 of the second stage 32 and the third stage 33 are intended for their adjustment. Similarly, the output of the second four-input unginned product gate 30 is coupled to the fourth input 15 of the second stage 32 and to the fourth input 19 of the third stage 33. The fourth inputs 15 and 19 of the second stage 32 and the third stage 33 are for resetting. The sixth output 13 of the first stage 31 is coupled to the second input of the second four-input negated product gate 30, the first input of which is coupled to the fourth output 17 of the first stage 31, indicated for reverse counting status: when counting backwards, it is connected to the third input of the second · four-input negated product · gate 30.

FIG. the first input 1 of the first stage 31 of the asynchronous reversing counter for forward pulse counting is connected both to the input of the first opening circuit 11, for example of the inverter, and to the first input of the third negated product gate 9. Second input 4 of the first a step 31, staked to feed back counting pulses, is connected to the input of the second opening circuit 5; on the one hand, to the second input of the third negated product gate 9, the negated output of which is connected to the TC input of the D-type flip-flop 8, the output of the first opening circuit 11 is connected to the first input of the first negated product gate 3; The output of the second opener 5 is connected to the second input of the second negated product gate 6 and to the sixth output 13 of the first stage 31. The output of the first negated product gate 3 is connected to the first output 10 of the first stage 31 and the output of the second negated product gate 6. it is connected to the second output 7 of the first stage 31. The third input 14 of the first stage 31 is connected to the input P for setting a two-state flip-flop 8 of type D, whose resetting input C is connected to the fourth; input 15 of the first stage 31 and whose input D is connected both with its negative output Q and with the second input of the first negated product gate 3 and with the fourth output 17 of the first stage 31 whose third output 16 is connected with the direct output Q of the 8 type D and at the same time as the first input of the second negated product, gate 6. The third negated · product gate 9 and the two-state flip-flop 8 type D form the two-state circuit 2. The third inlet 14 of the first stage 31 is is designed to be reset.

The operation of the reversible asynchronous counter is easily and briefly explained using the following logic table:

Status number

Logic state of the stage

33 32 31

9 o

o o

o o

, 1, 1 (1 o

o o

o, 1 o

o o

o .1, 1

AND.

o o

o o

o o

il.

o o

o o

o o

o o

o o

The asynchronous return counter connected in accordance with the invention operates as a binary counter that omits the ninth to fourteenth states, both in forward and backward counts, and when the ninth state occurs in forward counting, it is the logic circuit, i.e. the first four-input negated product gate, two-state flip-flops type D are set in the second and third stages so that the ninth state changes to the fifteenth state. Similarly, when counting backward, if the fourteenth state occurs, it immediately changes to the eighth state.

The change of the asynchronous decadic counter to the asynchronous binary counter is performed by bringing a level instead of a logical one level to the third wiring input for selecting the counter type for forward counting or the fourth wiring input for selecting the counter type for counting backward. logic zeros. However, such a change can be made independently for each count direction, i.e. for forward counting or reverse counting.

Negative pulses applied to the first and second wiring inputs appear at the fifth and sixth outputs of the first stage.

On the third and fourth outputs of the first stage there are pulses indicating the state when counting forward and backward.

The second and third stage settings are determined by their third inputs.

Fourth inputs are used to reset the second and third stages.

Claims (1)

Universal asynchronous reversing counter wiring consisting of at least two four-input negated product gates and at least four stages of an asynchronous reversing counter, each asynchronous reversing counter having a first input for forward counting and connected to the first opening circuit input the first input of the third negated product gate, the second input for inputting backward counting pulses and connected to the input of the second opening circuit, for example the inverter, and the second input of the third negated product gate; an output connected to the output of the first negated product gate, and a second output connected to the output of the second negated product gate, while the output of the first opening circuit is coupled to the first input of the pr and the output of the second · open circuit is connected to the second input of the second · negated product gate, while the output of the third negated product gate is coupled to the TC input of the D-type double-flip flip-flop · D input with its negative output Q and, at the same time, a second input of the first negated product gate and whose direct output Q of the D-type two-state flip-flop is connected to the first input of the second negated product gate, characterized in that the first wiring input (23) is designed to feed a counted pulse train. is connected to a first input (1) of the first stage (31), a second wiring input (24) for supplying a counting pulse train in reverse counting is connected to a second input (4) of the first stage (31), 10) for higher order transmission when counting forward is connected to the first the second input of the second stage (32) and whose second output (7) for higher backward counting is connected to the second input of the second stage (32), similarly both outputs of the second stage (32) are connected to the corresponding two inputs of the third stage (32) 33) and the two outputs of the third stage (33) are connected to the corresponding two inputs of the fourth stage (34), the first output (21) of which is connected to the first output (25) of the upstream transmission circuit a. (22) is connected to a second high-order wiring output (26) for reverse counting, while the first input of the first four-input negated product gate (29) is connected to a third output (16) of the first stage (31) associated with a direct output Q of the D-type two-state flip-flop (8) within the first stage (31), the second input of the first four-input negated product parallel bars (29) is connected to the fifth output (12) of the first stage (31) in forward counting associated with the output of the first opening circuit (11), the third input of the first four-input negated product gate (29) is connected to the third wiring input (27); intended to select the counter type when counting forward, the fourth input of the first four-input negated product gate (29) is connected to the fourth input of the second four-input negated product gate (30) and simultaneously to the third output (20) of the fourth stage (34) And the first input of the second four-input negated product gate (30) is connected to the fourth output (17) of the first stage (31) associated with the negated output Q of the D-type double-state flip-flop. within the first stage (31), a second input of a second four-input negated product the new gate (30) is connected to a sixth output (13) of the first stage (31) connected to the output of the second opening circuit (5) and simultaneously with the second input of the second negated product gate (6) inside the first stage (31); a second four-input negated product gate (30) is connected to a fourth input (28) for selecting the counter type when counting backward, and finally the output of the first four-input negated product gate (29) is connected to a third input (14) of the second stage (32) and simultaneously with the third input (18) of the third stage (i33), both of these third inputs (14, 18) are connected to the adjusting inputs P of the D-state double-state flip-flops within the second and third stages (32, 33), of the negated product gate (30) is connected to the fourth input (15) of the second stage (32) and at the same time with the fourth input (19) of the third The two inlets (15, 19) are connected to the reset inputs C of the two-state type D flip-flops within the second and third stages (32, 33).