CS210358B1 - Connection of the bit layered microproces ors - Google Patents

Description

This means that individual microprocessors process partial parts of the task and thus create overlap of logical and memory operations at the same time. With these advantages, the system minimizes downtime.

The advantages of the system are achieved with minimal costs and requirements for hardware and software.

Examples of parallel wiring of microprocessors according to the invention are schematically shown in the attached figures, where in FIG. 1 is. The parallel connection of two microprocessors is shown, and FIG. 2 shows in principle the parallel connection of three or more microprocessors.

The parallel connection of two microprocessors 3, 3a according to FIG. 1 is realized by means of external buses 2, 2a and a common memory module 1. Buses J2, 2a consist of a one-way control and address and two-way data part.

Internal microprocessors 5, 5a and I / O controllers 6, 6a are connected to each microprocessor via an internal bus 4, 4a.

Both microprocessors 3, 3 and are controlled by a common clock generator 1 and one scoring line. The parallel connection of the four microprocessors is schematically shown in FIG. 2. The connection of the microprocessors 3 - 3 n is realized by means of external buses 2 - 2n and common memory modules - 1 n.

The buses 2-2n consist of a one-way control, address and two-way data part. Each microprocessor is connected via internal buses - 4n with internal memory - 5n and with controllers v ssupne s supsity units 6 - 6n.

All microprocessors 3 - 3 n are controlled by a common clock generator 7 and by a delay line The requirements of microprocessors 3 - 3 n for common memory modules 64 - n are provided by the memory module address decoders 9 - 9n and the control logic 10 - 10n buses 2 - 2n. . The maximum number of n-microprocessors is given by the speed of the memory modules 11-1, the working speed of the buses 2-2n and the operating speed of the microprocessors 3-3n. Each system can be equipped with any number of memory modules 1 for special purposes.

The microprocessors connected in accordance with the invention operate such that each of the microprocessors operates separately, synchronously, but with shifted clock clocks. Data exchange between microprocessors is realized via common memory modules via buses. Since the systems operate with shifted clock pulses, there is no overlap in the requirements of individual microprocessors for the same memory module. The microprocessors are controlled from a single clock generator and the time shift is realized by a delay line.

The internal bus connects each microprocessor to its own memory and the I / O controller. The external buses connect the microprocessors with a common module memory. In a multi-microprocessor wiring system, each microprocessor's request for common memory modules is decoded by the memory module decoder. After the address is decoded, the next bus control logic provides a microprocessor-memory 1 connection.

The microprocessor circuit according to the invention can be used as a building block of large computer systems, a controller of peripheral units and controllers, as microcomputer controllers of technological processes, and for real-time processing of air traffic and similar areas requiring immediate, accurate and reliable data.

Claims (1)

OBJECT OF THE INVENTION Parallel connection of bit-layered microprocessors consisting of inert buses, inert memories and I / O controllers, characterized in that at least two microprocessors (3 to 3n) are mutually connected by common memory modules (1 to 1n) via external buses (2 to 2n) composed of a control, address and data part, each of the microprocessors (3 to 3n) being connected to a common clock generator (7) and a delay line (8).