CS209222B1 - Processor connexion for intelligent terminal - Google Patents

Description

CZECHOSLOVAK SOCIALIST DESCRIPTION FINDED 209222 R E P U B L 1 (ie) C A CERTIFICATE OF CERTIFICATE (11) (Bl) í (22) Registered 01 11 79 1 (21) (PV 7415-79). i (51) Int. Cl.3 G 06 F 3/00 OFFICE AND DISCOVERY OFFICE (40) Published 27 02 81 (45) Published 01 05 83 (75)

The inventor

BUREŠ JAROSLAV ing., BRNO (54) Connection of processor for intelligent terminal

BACKGROUND OF THE INVENTION The invention relates to a processor connection for an intelligent terminal.

The known processors of the intelligent terminal processor are designed such that the processors registers work with the same internal processor bus widths. Sixteen-tibit word processor systems using three internal collectors can be divided into roughly two types. The first type uses 16-bit collectors called R and S, which form the input to the arithmetic unit and the logical unit of the processor system and one of the 16-bit bus, designated T, which outputs the result of the operation and simultaneously input the processor registers. In the first type, the information is processed in parallel. The second type of serial processing of the 16-bit word, where the width of each of the three bits is one bit.

These types of processor systems are complex because they consist of a large number of elements, or their speed of operation is small for an intelligent terminal.  In the first type, it is typically vast, requiring parallel paths through sixteen bits of the word.  This disadvantage is particularly evident where direct execution of any operations is required.  In the second type, the low word processing rate exhibits an unfavorable effect of the one-bit output bus T, which prevents rapid shifts between processor work registers and other system blocks. the four-input sum of the product is the first input of the wiring, while its third input is connected to the third input of the second to the sixteenth four-input sum of the input and the second input of the second four-input additive gate is the third input of the input, the second input of the third four input input the input product, the second input of the fourth four-input sum of the product gate is the same-time input wiring, hour the inputs of the first to the fourth 5-bit shift register are connected and simultaneously form the sixth input of the connection, the second input of the fifth four-input addition gate is simultaneously the seventh input of the connection, the second input of the sixth input sum! , the second input of the seventh four-input 'sum product gate simultaneously forms the ninth input of the wiring, the second input of the eighth input four-input wedge gate is simultaneously the tenth input of the wiring, the second input of the ninth four-input sum of the product gate constitutes | 209222 2 209222 early eleventh wiring input, the second input of the tenth four-input product gate, simultaneously forms the twelfth input wiring, the second input of the eleventh four-input sum gate simultaneously forms the thirteenth wiring input, the second input of the twelfth four-input sum product gate at the same time, the 14th input of the connection, the second input of the thirteenth four-input sum of the product gate forms simultaneously. the fifteenth input of the wiring, the second input of the fourteenth four-input sum of the gate is simultaneously the sixteenth input of the wiring, the second input of the fourteenth four input wedge simultaneously forms the seventeenth input of the wiring, the second input of the sixteenth four-input wedge gate is simultaneously the eighteenth input wiring, the early nineteenth input of the wiring, while the output is connected to the output of the second two-input circuit of the logical product negation and forms the first wiring output, the second input of the first two-input circuit of the logic-type negation and the first input of the second two-input circuit of the logical product negation and it is also the twentieth input of the connection, the first input of the first three-input circuit of the non-negogenic product type is connected to the first on the input of the twenty-sixth five-bit shift register and simultaneously form the twenty-first input of the connection, while its second input forms the current fourth second input of the circuit, the third input of the first logical circuit negation circuit is connected to the third inputs of the fourth to sixth input circuit, and the second input of the twenty-second two-input the logic product negation circuit is the third third input circuit of the logic product negation and is connected to the input of the nineteenth inverter, the output of which is connected to the second input of the second two-input circuit of the logic product negation and to the basic input of the D type flip-flop, the hourly input input the type D flip-flop is the current fourth fourth input, whereas its one output is connected to the first inputs of the first to sixteenth four input o sum coefficient and at the same time form the second connection output, the output of the first four-input sum of the gate is connected to the input of the first inverter, the output of which is connected to the fourth input of the first five-bit shift register, the output of the second four-input sum of the gate is connected to the input of the second the inverter whose output is connected to the third input port of the first 5-bit shift register, the output of the third four-input sum of the product gate is connected to the input of the third inverter, the output of which is connected to the second input of the first 5-bit shift register, output of the fourth four-input sum of the the gate is connected to the input of the fourth inverter, the output of which is connected to the first setting input of the first five-bit shift register, the fifth J setting input of the first five-bit shift register u is connected to zero potential, while its fifth data output forms the sixty-fourth wiring output, the fourth data output of the first five-bit shift register is connected to the first inputs of the first and second two-input circuit of the logic product negation by the open collector, to the fourth setpoints of the eighth, twelfth, sixteenth , the twenty-fourth and five-fourth sliding registers, the fifth adjustment input of the thirty-first five-bit shift register, the serial input of the twenty-eighth five-bit shift register, and the second input of the twenty-two logic product negation circuit, the third data output the first 5-bit shift register is connected to the third set-up inputs of the eighth, twelfth, sixteenth, twentieth and twenty-fourth five-bit sliding registers and to the first settling inputs the second data bit of the first five bit shift register is connected to the second adjustment input of the eighth, twelfth, sixteenth, twenty, twenty, fourth and thirty five bit shift registers, the first data output of the first bit shift register is connected to the first eight input settings , the twelfth, sixteenth, twentieth, twenty-fourth, five-fifth shift registers, and the third set-up inlet of the twenty-ninth five-bit shift register, the null inputs of the first to fourth five-bit shift registers, and at the same time form the ninety-seventh wiring entry, the first and second five-bit adjustment inputs. The shift registers are connected to the output of the seventeenth inverter, the release inputs of the setting of the third and fourth five-bit shift registers are connected to the output of the axis. the fifteenth inverter, the input of which is connected to the inlet of the seventeenth inverter and at the same time forms the fifty-ninth wiring output, the serial input of the data of the first five-sliding shift register simultaneously forms an eighty-wavelength output; the input of the second 5-bit sliding register, whose serial data input is currently the seventy-fifth input input, the output of the sixth four-input cumulative gate is connected to the input of the sixth inverter, the output of which is connected to the third input input of the second five-bit shift register, the output of the seventh four-input cumulative gate is connected to the input of the seventh inverter whose output is connected to the second set-up input of the second five-bit shift register, outputting the eighth four-input sum the gate is connected to the input of the eighth inverter, the output of which is connected to the first setting input of the second five-bit shift register, the fifth data input of the second five-bit shift register is connected to zero potential, while the fifth data output is simultaneously the 60th circuit output, the fourth data output of the second-bit shift register is connected to the first inputs, the third and fourth two-input, logical product negation circuit with the open collector, further to the fourth set-up inputs 1 of the seventh, eleventh, fifteenth, nineteenth-; The third data output of the second five-bit sliding register is connected to the third set input of the seventh, eleventh, fifteenth, deviation - the fifteenth, twenty-five five-bit shift register, the fifth set-up input of the thirty-five shift register, the second one: - the output of the second five-bit shift register is connected to the second set-up inputs of the seventh, eleventh, fifteenth, nineteenth, twenty-third five-bit sliding register and the first set input of the thirty-bit shift register, the first data output of the second bit shift register is connected to the first set input inputs sed the 5th bit shift register and the second adjuster input of the 28th 5-bit shift register, the output of the ninth four-input sum gate is connected to the input of the ninth inverter, the output of which is connected to the third setting input of the third five-bit shift register, output of the tenth four-input; The output of the product is connected to the input of the tenth inverter, the output of which is connected to the third input of the third 5-bit shift register, the output of the eleventh four-input «gate of the product is connected to the input of the 11th inverter whose output is connected to the second input the third five-bit shift register, the output of the twelfth four-input sum product gate is connected to the inlet of the twelfth inverter whose output is connected to the first setting input of the third five-bit sliding register, the fifth adjustment input of the third, five-bit shift register is connected to the null potential, whereas its fifth data output.  H forms at the same time the sixty-sixth output connection, the fourth data output of the third five-bit sliding register is connected to the first inputs of the fifth and sixth two-track negation circuit! a logical product with an open collector, a fourth setting input of the sixth, tenth, fourteenth, eighteenth, twenty-second five-bit shift registers, as well as a serial data input of the twenty-sixth five-bit shift register; to the third input input of the thirty-first five-bit shift register and to the second input 209222 of the 24th two-input logic product negation type 1, the third data output of the third five-bit shift register is connected to the third adjusting inputs of the sixth, tenth, fourteenth, eighteenth, twenty-second five the second data output of the third five-bit shift register is connected to the second adjustment inputs, the sixth, tenth, fourteenth, eighth, twenty-second five-bit shift registers, and the fifth the twenty-thirty-shift shift register setting input, the first data output of the third five-bit shift register is connected to the first set input input of the sixth, tenth, fourteenth, eighteenth, twenty-second, and the 28th 5-bit sliding register, the serial data input of the third five-bit shift register simultaneously constitutes the 7th 9th input input, the output of the thirteenth four-input sum gate is connected to the thirteenth inverter input, the output of which is connected to the fourth fourth input five-bit shift register, the fourteenth four-input sum, it is connected to the input of the fourteenth inverter whose output is connected to the third setting fourth fourth bit shift register, the output of the fifteenth four input coefficient is connected to the input of the fifteenth inverter whose output is connected to the second input of the fourth five-bit shift register, output of the sixteenth four-input sum gate it is connected to the input of the 16th inverter whose output is connected to the first the setting input of the fourth five-bit shift register, the fifth setting input of the fourth five-bit shift register is connected to the zero potential, while its serial data input forms the 29th input input at the same time, the fifth data output of the fourth five-bit shift register is the sixty-seventh output , the fourth data output of the fourth five-bit sliding register is connected to the first inputs of the seventh and eighth two-input open-collector type of the non-agglomerate product, the fourth set-up inputs of the fifth, ninth, thirteenth, seventeenth, twenty-first five-bit shift registers; , to the serial input of the data of the twenty-fifth bits shift register and to the second input of the twenty-second two-input circuit of the logic product unification type, the third data the fourth 5-bit shift register is coupled to the third adjusting inputs of the fifth, ninth, thirteenth, seventeenth, twenty-first, and thirty-five five-shift shift registers, the second data output of the fourth five-bit sliding register is connected to the second adjusting input, ninth, thirteenth, seventeenth, two-way first five-bit sliding Further, to the fourth set-up input of the 28th 5-bit shift register, the first data output of the fourth five-bit shift register is connected to the first set-up inputs of the fifth, ninth, thirteenth, seventeenth, twenty-first (five-bit shift registers, and the second set of the third two-input shift register). the circuit of the type of non-cellular product, the second inputs of the first, third, fifth and seventh two-input circuit are connected and form simultaneously the twenty-fifth input of the connection, the tup of the first two-input circuit of the logic product type with open collector is connected via the second resistor to the positive electric power source and to the outputs of the twelfth, sixteenth, twenty, twenty-fourth, twenty-eighth and thirty-thirty-two two-input circuit of the negation of the open collector and, at the same time, forming a third wiring output, the output of the second two-input circuit of the logical product negation with the open collector is connected via the first resistor to the positive pole of the power supply and the output of the thirty-second two-input circuit of the logic product negation with the open the collector and form the fourth output, the canopy, the output of the third two-input circuit of the logic product negation with the open collector is connected via the fourth resistor of the power supply pole and on the eleventh output , the fifteenth, twenty-ninth, twenty-sixth, and the thirty-eighth eighth input circuit of the negation of the open-collector logic product and form simultaneously the seventh wiring output; the type of negation of the logic product with the open-collector, on the other hand, through the third resistor on the positive: pole of the electric energy source and simultaneously forms the eighth output connection, the output of the fifth two-input circuit of the negation of the logic product with the open collector is connected via the sixth resistor to the positive pole of the power source , on the other hand, on the output of the tenth, fourteenth, eighteenth, twenty-second, twenty-six and thirty-sixth two-input circuit of the type of open-collector non-agglomerate product, and at the same time form the ninth up wiring, the output of the sixth input circuit of the open-collector negation logic type is connected via the fifth resistor to the positive pole of the power source, and to the thirty-two-input circuit of the logic product negation with the open collector and forms the tenth output output, the output of the seventh two-input circuit the type of logic product with open collector is connected via the eighth resistor to the positive electric power source, and to the ninth, thirteenth, seventeenth, twenty-second, twenty-fifth, and thirty-sixth two-input circuits of the logic product negation with the output, the output of the eighth two-input circuit the type of negation of the logic product is connected via the seventh resistor to the positive pole of the power source, on the other hand to the output of the twenty-thirtyhour input circuit of the negation of the logicfunction with the open collector and forms the coefficient the fourteenth wiring output, the zeroing inputs of the fifth, sixth, seventh and eighth five-bit shift registers are connected to form the twenty-second wiring input, the clock inputs of the fifth to the five-bit shift register are coupled to form the 27th wiring input, the release settings of the fifth and the six-bit shift register is connected to the output of the twenty-first inverter, the release inputs of the settings of the seventh and eighth five-bit registers are connected to the output of the twenty-second inverter, its input is connected to the input of the twenty-second inverter and simultaneously forms the two-eighth input of the connection, the first data output of the five-bit shift register is simultaneously the sixteenth wiring output, the fourth data output of the fifth five-bit shift register is connected to the serial input of the fifth five-bit shift register and the first the ninth input of the open collector negation input circuit, the fourth data output of the sixth five-shift shift register is connected to the serial input of the sixth five-shift shift register and the first input of the tenth of the open collector negation input circuit, the fourth data input of the seventh five-shift shift register is connected to the seventh five-bit serial data input and the first input of the eleventh two-input logic open-circuit negation circuit, the fourth data output of the eight-bit shift register is connected to the serial input data of the eighth five-bit shift register and to the first input of the twelfth input circuit of the open-collector negation logic type and forms the fifteenth output wiring, second inputs of the ninth to twelfth two-input flip-flop, negation type l The coupled product with the open collector is coupled to form the thirtieth input of the connection, the ninth and tenth shift selections are connected to the output of the twenty-third inverter, the release inputs of the eleventh and twelfth five-bit shift registers are output to the 24th inverter, the input of which is connected to the input of the twenty-third inverter and simultaneously forms the thirty-third input of the connection, the zeroing inputs of the ninth to twelfth five-shift shift register are simultaneously connected to the thirty-first input of the connection, the hourly inputs of the ninth to twelfth five-bit shift register are connected and form the thirty-second second wiring input, first data output | of the ninth five-bit shift register, at the same time, the seventeenth wiring output, the fourth data! the output of the ninth five-bit shift register is connected to the serial input of the data of the ninth 5-bit shift register and to the first input of the thirteenth two-input logic open-loop negation circuit, the fourth data output of the 10th five-bit shift register is connected to the serial input of the tenth five-shift shift register data and to the first input of the fourteenth two-input circuit of the logic-type negation type with the open collector, the fourth data output of the eleventh five-bit sliding register is connected to the serial input of the eleven-bit shift register data and to the first input of the fifteenth two-input circuit of the non-glogical product with the open collector is connected to the serial input of the 12th 5-bit shift register data and to the first input of the 16th two-input circuit of the negation logickéhoisoučinus open collector inputs of the second to sixteenth třiriáctého dvouvstu-pového logical negation circuit of the type open collector součinus are connected to form. • at the same time the thirty-eighth wiring input, the release inputs of the thirteenth and fourteenth five-shift shift registers are connected to the output! the twenty-fifth inverter, the release inputs on! building of the fifteenth and sixteenth five-bit; The shift registers are connected to the output of the twenty-sixth inverter, the input of which is connected to the inlet of the twenty-fifth inverter, and the thirty-thirteenth wiring input, the zero to sixteenth five-bit sliding register is connected to form the thirty-fourth wiring, clock inputs of the thirteenth and sixteenth five-bit The first data output of the thirteenth five-bit shift register is simultaneously the eighteenth output of the connection, while its second data output is simultaneously the nineteenth wiring output, the third data output of the thirteenth five-bit shift register! I form the twentieth output of the circuit, while its fourth data output is connected to the serial data input of the thirteenth five-bit sliding register and to the first input of the seventeenth two-input circuit of the logic product negation with the open collector and simultaneously form the twenty-first wiring output, the first data output the fourteenth five-bit shift register simultaneously constitutes the twenty-second wiring output, while its second data output simultaneously forms the twenty-third wiring output, while the third data output of the fourteenth five-shift shift register is the twenty-fourth wiring output, while its fourth data output is connected to the serial input of the fourteen-bit shift register data and to the first eighteenth two-input circuit of the non-negogenic product type with an open collector and comprising: simultaneously the twenty-fifth wiring output, the first data wedge in degrees fifteenth five-bit shift re- 209,222 Gistr simultaneously form the twenty-sixth output circuit, while the second data output constitutes contemporary-twenty-seventh output wiring, the third data výstupj fifteenth five-bit shift register tvoříj while twenty-eighth output circuits, whereas | its fourth data output is connected to a serial, data input of the 15th 5-bit sliding relay! the first input of the nineteenth two-input circuit of the logic product negation with the open collector and at the same time form the twenty-ninth wiring output, the first data output of the sixteen-bit shift register simultaneously constitutes the thirtieth wiring output, while its second data output simultaneously constitutes the thirty-first wiring output, the third data output of the sixteenth five-bit shift register simultaneously constitutes the thirty-second connection output, while its fourth data output is; connected to the serial input data of the 16th 5-bit shift register and to the first input of the twenty-two logic open loop negation circuit of the twenty-second and forms the third wiring output, the second inputs of the seventeenth to twenty-two-input circuit of the logic product negation with the open collector they are connected and simultaneously form the thirty-seventh wiring input, the release inputs of the settings of the seventeenth and eighteenth five-bit sliding registers are connected to the output of the twenty-sixth inverter, the outputs of the setting of the nineteenth and twenty-five-shift shift registers are connected to the output of the twenty-fifth inverter whose input is connected to the twentieth input -the sixth inverter and simultaneously form the forty-first wiring input, the zeroing inputs of the seventeenth to twenty-five-shift shift registers are coupled to form a frictional the eighteenth wiring input, the clock inputs of the seventeenth to twenty-bit shift registers are coupled to form a fortieth wiring input, the first data output of the seventeenth five-bit shift register simultaneously forms the fifth wiring output, while its second data output is simultaneously: wired output, third data output output seventeen-! At the same time, its quarterly output is connected to the serial input of the seventeenth five-bit shift register and the input of the twenty-first two-input oblique. water of negation of logic product with open! the first data output of the eighteenth five-shift shift register simultaneously constitutes the thirty-fourth wiring output, while its second data output simultaneously forms the thirty-fifth wiring output, while the third data output of the eighteenth five-bit shift register is the thirty-third wiring output, whereas its fourth data output is connected to the serial input data of the eighteenth five-bit shift register and to the first input of the twenty-second two-input circuit of the non-gel product with open collector and form! at the same time the thirty-seventh wiring output, the first data output of the nineteenth five-bit sliding register is simultaneously the thirty-eighth wiring output, while its second data output is simultaneously the 39th wiring output, the third data output, the nineteenth five-bit shift register, is the 40th wiring output, while its fourth the data output is connected to the serial data input of the nineteenth five-bit shift register and to the first input of the twenty-second two-input circuit of the negation of the logic product by the open collector and simultaneously forms the forty-first connection output, the first data output of the twenty-five-shift shift register being the forty-second time the wiring output, while the second data output is simultaneously the forty-third and wiring output, the third data output of the twenty-five-bit sliding r the egistra is at the same time, the forty-fourth wiring output, while its quarter-quarter output is connected to the serial input of the twenty-five-shift shift register, and on iprviia is the twenty-fourth two-input circuit of the logic product negation with the open-collector, and simultaneously forms the 40th wiring output, the second inputs of the twenty-second to twenty-fourth two-input circuit The logic product negation type with the open collector is connected and simultaneously forms the forty-second wiring output, the twenty-second and twenty-second five-bit five-bit shift registers are connected to the twenty-eighth inverter output, the twenty-third and twenty-fourth set-off inputs. The 5-bit shift register is connected to the output of the 29th inverter, the input of which is connected to the twenty-eighth inverter and forms the current inverter. the 45th input input, the zeroing inputs of the two-thirty-to-twenty-fourth five-bit sliding register are connected at the same time forming the forty-third input of the wiring, the clock inputs of the two-thirty-to-twenty-fourth five-bit sliding register are connected and form at the 45th input of the wiring; the data input of the twenty-first five-bit shift register and the first twenty-second two-input circuit of the logic product unallocation of the fourth data shift of the twenty-second five-shift shift register is connected to the serial data output of the twenty-second five-bit shift register and to the first input of the sixty-sixth log input-negation input circuit the collector, the fourth data output of the 22nd the 5-bit sliding register is connected to the serial input of the twenty-third five-bit shift register data and the first input of the twenty-second two-input logic product negation circuit with the open collector, the fourth data output of the twenty-fourth five-bit shift register is connected to serial data input and to the first input the twenty-eighth two-input circuit of the negation of the logic product with the open collector, the second input of the twenty-fifth to the twenty-eighthour input circuit of the negation of the logicfunction with the open collector is connected to form the forty-thirty input of the wiring; inverter, the release inputs of the twenty-seventh and twenty-eighth five-bit shift registers. are connected to the output of the thirty-first inverter, the input of which is connected to the input thirty-fifth inverter and connected to the output of the second three-input circuit of the logical product negation, whose first input is simultaneously the forty-thirty input of the wiring and whose second input is simultaneously the forty-fifth input of the wiring, the third input the second input of the third three-input circuit of the logic product unification type is connected and simultaneously forms the fiftieth input of the connection, the second input of the third three-input circuit of the logical product negation is simultaneously the fifty-first input of the connection, while its third input is simultaneously the fifth input of the connection, the output of the third three-input circuit of the logical negation type the product> is connected to the reset inputs of the twenty-fifth to twenty-eighth five-bit sliding register, the hourly inputs of the twenty-fifth to the twenty-five-slider the first shift input of the twenty-fifth five-shift shift register simultaneously forms the fifty-fourth fourth input of the circuit, while its second input input is connected to the second input of the sixth three-input circuit of the logic circuit negation. - and the first input of the twenty-first two-way logic product negation circuit is the fifty-fifth wiring input, the third set input of the twenty-five five-bit shift register is the fifty-fifth wiring input, while its fourth set-up input is the seventy-fifth wiring input, its fourth data output is connected to the first input the 28th two-input logic product negation circuit with the open collector, the second input input of the twenty-sixth shift register is connected n and the first input of the fourth three-input circuit of the logic product type, further to the second input of the first first two-input circuit of the logical product type negation, and simultaneously constitutes a sixty-second circuit, while its third set-up input simultaneously comprises the sixty-first connection input and its fourth set input simultaneously constitutes the sixty-second line input the connection, wherein the fourth data output is connected to the first input of the thirty-two-input circuit of the negation of the logic product by the open collector, the first adjustment input of the 29th five-bit shift register is simultaneously the 60th input of the connection, while its second input input is the sixty-fourth input input and its third set - the input input is simultaneously the 60th switching input, the fourth input input of the twenty-fifth shift register is at the same time the thirty-first input of the wiring, while its quarterly output is connected to the first input of the thirty-first two-input circuit of the negation of the logic product with the open collector, the first setting input of the twenty-eight five-bit sliding register is simultaneously the sixty-seventh input of the wiring, while its second set-up input simultaneously forms the 60th input wiring and its input.  the third set-up input is the sixty-eight input of the wiring, the fourth set-up input of the twenty-eight-bit sliding-register is the seventieth input of the wiring, whereas its fourth data output is connected to the first input of the thirty-second two-input wireline of the logical product negation with the second collector, the first input of the fifth three-input circuit of the logic product unification type and simultaneously forms the seventh-seventh input of the circuit, while its output is connected to the input of the thirty-fifth inverter, the output of which is connected to the second input of the thirty-third input circuit of the open collector negation , the output of the first inverter with the open collector is connected to the output of the 29th circuit the type of negation of the logic product with the open collector, the output of the second inverter with the open collector is connected to the output of the thirty-second input circuit of the negation of the logicfunction with the open collector; The output of the fourth open-collector inverter is connected to the output of the thirty-second two-input circuit of the logic-negative negation, the second input of the three-input circuit of the logical product negation is connected to the first input of the sixth three-input circuit of the logical sequence negation. while the output is connected to the input of the thirty-sixth inverter, the output of which is connected to the second input of the thirty-fourth two-input circuit of the logic product negation, the output of the sixth three-input circuit of negation! the logical product is connected to the input of the thirty-seventh inverter whose output is connected to the input of the fifth open-collector inverter to the second inputs of the second, fourth, sixth, and eighth two-input negation circuits. the logical product with the open collector, the output of the twenty-second two-input circuit of the logic product type unification is connected to the first input of the twenty two-input circuit of the logic product type unification whose output is connected to the first input of the thirty-two two-input 209222 logic product negation circuit with the open collector and the second input to the twenty-second the third to thirty-second two-input circuit of the negation of the logic product with the open collector, the outputs of the thirty-third to thirty-fifth of the input circuit of the type of negation of the open-collector open-collector, and the output of the fifth-inverter with open-collector are connected via the twenty-fifth resistor of the load pole of the power supply and the basic input of a second type D flip-flop whose zero output is connected to the first input of the thirty-third of the two-input logic circuit type open collector, on the serial input of the twenty-fifth five-bit shift register, on the fourth input of the sixteenth four-input sum product gate on the first input of the two-input circuit of the logic product type, the hourly input of the second-type flip-flop is connected to the clock inputs of the twenty-fifth to thirty-first paw the tibitic shift register and at the same time form the third input of the circuit, the zeroing inputs of the 29th to 30th five-bit shift register are connected and connected to the nanodetection input of the second flip-flop circuit to form a fifty-fifth wiring input; the input of the wiring, the output of the thirty-second inverter is connected, on the one hand, to the first input of the third one of the two input circuits of the negation of logic, its the output is connected to the resetting input of the second type D flip-flop, on the other hand, the input of the twenty-second shift register, the thirty-third inverter output is connected to the thirty-first and thirty-first five-bit shift registers, the first data output of the twenty-fifth shift register is the fourth input of the twelve four-input sum of the product gate is connected to the first input of the fifth input circuit of the logic-type negation whose output is simultaneously the forty-eight output of the circuit; is connected to the fourth input four-input sum coefficient and the first input of the sixth input is The second data output of the 28th 5-bit shift register is connected to the fourth input fourth product gate and to the first input of the seventh two-input circuit of the non-logic product type, the output of which is at the same time fifty-first. the wiring output, the fourth data output of the 28th 5-bit shift register is connected to the fourth input of the fifteen-four-input sum gate and to 209222. . . . . . ? . . . . . . .  . . . - | the first input of the eighth input circuit of the logic product type, the output of which is simultaneously the fifty-second wiring output, the fifth data; the output of the 28th 5-bit shift register is connected to the fourth input of the eleventh] four-input sum gate, serial input of the thirty-five-shift shift register and the first input of the ninth two-input circuit of the logical product negation, whose output is simultaneously the fifty-fifth output of the junction, the first data output of the thirty-five-bit sliding register is connected to the fourth input sum of the product gate and the first input of the tenth two-input circuit of the non-logic product type, whose output is present The fourth data output of the thirty-five shift register is connected to the fourth input of the third four input chords. The first data gate of the fifth five-bit shift register is connected to the fourth input of the fourteenth four-input multiplex product gate and to the first input (twelfth two-input circuit of the non-germinal type). The fourth data output of the thirty-five shift register i is connected to the fourth input of the tenth four input gate of the product and to the first input of the thirteenth two-input circuit of the non-homogeneous product, the output of which is present the fifth, seventh, output fifth, the fifth data Vw, the step of the thirty-five shift register j «-connected to the fourth input of the sixth four-input gate product, n and a serial input of a thirty-first five-bit shift register and a first input of a fourteenth two-input logical product negation whose output is simultaneously a fifty-fifth wiring output, the first data output of the thirty-first five-bit shift register is connected to the fourth input of the second four-input sum and the first input of the fifteenth two-input-input the logic product negation circuit of which: the output is simultaneously the fifty-fifth interconnect output, the second data output of the thirty-second five-shift shift register is connected to the fourth input of the thirteenth four-input concurrent gate, and the first input of the sixteenth double-input circuit of the logical negation type the product of which the output is simultaneously the 60th output connection, the third data output of the thirty-first 5-bit shift register is connected to the the fourth input of the fourth four-input coefficient and the first input of the seventeenth two-input circuit of the logical product negation whose output is simultaneously the sixty-first output of the connection, the fourth data output of the thirty-second five-input shift register is connected to the fourth input four-input sum gate and to the first input of the eighteenth two-input logic-product negation, whose output is simultaneously the 60th switching output, the fifth data output of the thirty-first five-bit shift register is connected to the other input; the thirty-second two-input circuit of the logic product negation with the open collector, the fourth input of the first four-input logic product gate, and the first input of the nineteenth two-input circuit of the logic product type, the output of which is simultaneously the 60th output of the connection, the second input of the fourth two-input circuit of the negacelogic product the load pole of the power supply is connected via the ninth resistance and simultaneously forms the 80th input of the wiring, the second input input of the logic product negation is connected via the tenth resistor of the load pole of the power supply and simultaneously forms the wiring of the sixth input, the second input of the sixth two-input circuit the type of negation of the logical product is connected via the eleventh resistance positive pole of the electrical energy source and forms the eighth third input of the connection, the second exit of the seventh d in the input circuit of the non-logic product type, it is connected to the positive pole of the electric power source via a twelve-resistance, and at the same time forms the 80th input connected. the second input of the eighth input circuit is the logic product unification is connected via the thirteenth resistance to the positive pole of the power supply and simultaneously forms the 80th input input, the second input the ninth two-input circuit of the negation of the logic product is connected with the fourteenth resistance to the positive pole of the power source and simultaneously forms the 80th input of the connection, the second input of the tenth two-input circuit of the negation of the logic product is connected through the fifteenth resistance to the positive pole of the electric power source and simultaneously forms the 80th input of the connection, the second input of the eleventh the two-input circuit of the logic product negation is connected via the sixteenth resistor to the positive pole of the electrical energy source and forms a The second input of the twelfth two-stage circuit of the logic product negation is connected via the seventeenth resistance to the positive pole of the electric energy source and forms simultaneously the eighth-sixth input of the connection, the second input of the thirteenhour input circuit of the logic-type negation is connected via the eighteenth resistance to the positive pole of the power source and forms the present ninety-one input circuit, the second input of the fourteenth input circuit of the logic-type negation is connected via the nineteenth resistor of the load pole of the power source and forms the ninety-second wiring input; the current input is the ninety-second input, the second output of the sixteenth two-input circuit of the logic product negation is connected via d vacatý-1, the first resistor on the positive pole of the power supply jj and at the same time forms the ninety-third wiring input,! the type of negation of the logic product is connected through the 29th resistance to the positive pole of the power source and simultaneously forms the 90th input of the connection, the second input of the eighteenth two-input circuit of the logic product negation is connected via the thirty-third resistor to the positive pole of the electrical power source and forms at the same time devade-ΐ the fifth input of the wiring, the second input of the nineteenth two-input circuit of the logical-element negation type is connected via the 24th resistor to the 'positive pole of the power supply' and simultaneously forms the ninety-sixth wiring input, the second inputs of the thirty-sixth to thirty-sixth two-watt circuit of the logical product negation they are connected by an open collector and simultaneously form a seventy-second wiring input, the input inputs of the third to sixth flip-flop circuits D are connected to form a seventy-third wiring input where that their basic inputs j | they are connected to the positive pole of the electrical power source and their hourly inputs are connected simultaneously to the seventy-fourth wiring input, even zero The output of the third type D flip-flop circuit is connected to the first input of the thirty-sixth two-way circuit of negation of 'logic product' with 'open collector', whereas its zeroing. The input is connected to the output of the twenty-secondhour input circuit of the logic-type negation, the zero output of the fourth flip-flop circuit is connected to the first input of the thirty-seventh two-input circuit of the logic-negative negation, whereas its 'zeroing' input is connected to the output of the twenty-second two-input logic- The zero output of the fifth flip-flop type D is connected to the first input of the thirty-eighth double-input circuit of the non-germinal product with the open collector, while the zero input is connected to the output of the twenty-fourth two-input circuit of the non-germinal product type, the one output of the sixth flip-flop is at the same time, the forty-sixth wiring output, the zeroing input of the sixth flip-flop circuit of type D is connected to the output of the twenty-second two-input circuit of the negation type logic whereas, while its zero output is connected to the first input of the thirty-fourth two-input circuit of the logical product negation; ; with an open collector, the first input of the thirty-ninth two-input circuit of the type of non-negogenic product with an open collector and at the same time forms the forty-seventh connection output, the input of the thirty-fourth inverter is simultaneously a seven-I-fifth input of the wiring, while its output is connected to the first inputs of the twenty-second to twenty-fifth two-input circuit typing the logical product.  By connecting the processor for the intelligent terminal 209222 (according to the invention), the maximum number of processor elements is reduced, with a number of other advantages being achieved.  First, the processor register engagement allows the registers to be shifted over four-bit buses over the arithmetic and logical unit and the 16-bit bus to each other, resulting in a penetrating reduction of the necessary circuitry in a four-bit arithmetic unit, e.g.  of the author's axis of census no. 209221, as well as in their own four-wire bus control circuits.  Secondly, it is possible to easily perform direct decimal operations in the arithmetic unit.  Thirdly, a high data transfer rate between registers is achieved, since they run over the 16-bit bus.  This property is achieved by dividing the processor time cycle into six time intervals, of which two four-bit busses are controlled in the first four time slots, and the number of bits selectable by the microprogram is shifted at the same time and one is controlled in the last two time intervals. a 16-bit bus that allows parallel transfer between process registers.  These features are further achieved by employing processor-based registers for the serial-parallel and 16-bit bus, eliminating the complex multiplexers of the bus. The data register T2 is used in addition to memory for functions of one-bit shifts, rotation and cyclic rotations over one bit of the transfer register, which in turn leads to an increase in processor power while simplifying the process of the process.  ! An example of a processor for a smart ter- ritor The invention according to the invention is shown schematically in the accompanying drawings, in which: FIG.  la předst- | FIG.  1b {connection of the working register R 2, FIG.  lc connection! address register R 3, FIG.  The register wiring id (conditions Q, FIG.  le wiring of the macroinstrument counter P, fig.  lf engaging a constant register K, [fig.  lg, h connection of TI battery, ojbr.  FIG.  lk wiring register E, FIG.  2 is a diagram of a five-bit shift register; FIG.  3 shows the structure of the microinstruction and FIG.  4 Processor Control Timing Chart, __________________________________________________ The second input of the first four-input additive {SSHC1 product gate for the DAT (O) data signal simultaneously constitutes the first wiring input 01, connectable to the main memory (not shown), whereas its third input for the T2D0T1 signal is connected to the third input the second to sixteenth four-input sum of the product gate SSHC2 to SSHC16 and simultaneously form the second input 02 of the connection, connectable to a time source (not shown).  The second output of the second four-input summing gate SSHC2 for the data signal DAT (4) simultaneously constitutes the third input 03 of the wiring, the connectable main memory.  The second input of the third four-input sum gate SSHC3 for the data signal DAT (8) simultaneously constitutes the fourth input 04connection, connectable to the main memory.  The second 10 209222 input of the fourth four-input summing gate SSHC4 for the data signal DAT (12) simultaneously forms the fifth input 05 of the wiring, connectable to the main memory.  The clock inputs 1 of the first to the fourth 5-bit shift registers PR1 to PR4 for the signal T1 (HOD) are connected and form simultaneously the sixth input 06 of the connection, the connectable timing source.  The second input of the fifth four input SSHC5 product gate for the DAT (1) data signal simultaneously constitutes the seventh input of the connection, connectable to the main memory.  The second output of the sixth four-input sum of the SSHC6 product gate for the data signal DAT (5) is the eighth input 08 of the connection, the attachable memory.  The second input of the seventh four-input additive gate SSHC7 for the data signal DAT (9) simultaneously forms the ninth input 09 of the connection, connectable to the main memory.  The second exit of the eighth four-input sum of the SSHC8 product gate for the data signal DAT (13) simultaneously forms the tenth input 010 of the wiring, connectable to the main memory.  The second input of the ninth quadruple sum product gate SSHC9, the DAT (2) sales signal, constitutes the eleventh iv input 011 connection, connectable to the main memory. The second input of the tenth four input SSHC10 total input gate for the data signal, DAT (6), simultaneously forms the 12th input 012 of the junction, connectable to the main memory.  The second input of the eleventh four-input sum coefficient SSHC11 for the DAT data signal (10) forms the thirteenth input 013 wiring, connectable, to the main memory.  The second input of the twelfth four-input sum gate SSHC12, the DAT signal (14), simultaneously constitutes the fourteen-digit connection 014, connectable to the main memory. The second step of the thirteenth four-input cumulative gate SSHC13 for the data signal, D AT (3), simultaneously forms the fifteenth input 015 of the wiring, connectable to the main memory.  The second fourteenth input fourteenth sum SSHC14 of the data signal DAT (7) simultaneously forms the sixteenth input 016 of the wiring, connectable to the main memory.  The second input four-way sum of the product gate SSHC15 sell signal DAT (11) simultaneously constitutes the seventeenth input 017, connectable to the main memory.  The second input of the sixteenth four input SSHC16 splitter gate for the data signal DAT (15) simultaneously constitutes the eighteenth input 018 of the wiring, connectable to the main memory.  The first input of the first two-input circuit NSD1 of the logical product type for the ROM signal (33) constitutes at the same time the nineteenth input 019 of the connection, connectable to the ROM-type control memory (not shown), while its output for the control signal START1 is connected to the output of the second two-input circuit of the NSD2 type logic product negation and constitutes the first output 001 of the connection, the main memory can be connected.  The second input of the first two-input circuit NSD1 of the logic product negation type and the first input of the second logic product negation circuit 2ND2 of the logic product for signalTOA are connected and simultaneously form the twenty input 020 connection, connectable to the time source.  The first input of the first logical product type NST1 three input circuit NST1 for the ROM signal (20) is connected to the first set-up input 2 of the twenty-sixth 5-bit shift register PR26a constitutes at the same time the first input 021 connection, connectable to the ROM control memory, while the second input for the ROM signal (21) form a contemporary. twenty-second input 022 wiring, mountable ROM control memory.  The third input of the first three-input NST1 circuit of the types of negation of the logic product for the ROM signal (22) is connected to the third: inputs of the fourth to sixth three-input circuit NST4, NST5, NS6, then the second input of the twenty-two input circuit NSD20 of negation [logic product a they simultaneously form twenty-third input 023 wiring.  The output of the first logical product negation NST1 of the three input input is connected to the nineteenth inverter input INV19 "whose output is connected to the second input of the second logical product negation NSD2 input circuit and to the DTE first flip-flop circuit input 11.  The clock input 12 of the first AČT type D flip-flop for signalTAKT simultaneously forms the twenty-fourth input 024wiring; a time source, while its unlock output 101 for the READ control signal is connected, to the first inputs of the first to sixteenth four input input gate SSHCl to SSHC16, and simultaneously forms a second connection output 102 connectable to the main memory.  The output of the first four-input sum coefficient SSHCl is the connection to the input of the first invert INV1, the output of which is connected to the quarter-input input 6 of the first five-bit shift register PR1.  The output of the second four-input coefficient gate SSHC2 is connected to the input of the second inverter INV2, the output of which is connected to the third setting input 4 of the first triplet shift register PR1.  The output of the third four-input sum coefficient SSHC3 is connected to the input of the third inverter INV3, the output of which is connected to the second output input 3 of the first five-bit shift register PR1.  The output of the fourth four input input gate SSHC4 is connected to the input of the fourth inverter INV4, the output of which is connected to the first setting input 2 of the first triplet shift register PR1.  The fifth setting input 7 of the first 5-bit sliding register PR1 is connected to zero potential, while its fifth data output 10 for the signal T1 (0) V forms the sixty-fourth output 0064 of the wiring, connectable to an input / output control unit (not shown).  The fourth data output11 of the first 5-bit shift register PR1 for the signal T1 (0) is connected to the first input of the first and second two-input circuit NSDK1, NSDK2 of the negation of the logic product by the open collector, to the fourth set-up 11 'inputs 6 of the eighth, twelfth, sixteenth, twenty-third and twenty-fourth. of the 5-bit sliding '' register PR8, PR12, PR16, PR20, PR24, then on its PR31 sliding register, to the serial input 9 of the twenty-eighth five-way sliding register PR28 and the second input of the twenty-fifth of the input circuit NSD25 of the negation of logical products.  The third data output 13 of the first bias shift register PR1 for the signal T1 (4) is connected to the third adjusting input 4 of the eighth, twelfth, sixteenth, twentieth and twenty-fourth five-bit sliding modes PR8, PR12, PR16, PR20, PR24 and the first input 2 of the thirty-first five-bit sliding register PR31.  The second data output of the 14th first 5-bit shift register PR1 for the signal T1 (8) is connected to the second adjustment inputs 3 of the eighth, twelfth, sixteenth, twenty, twenty-fourth and thirty five-bit shift registers PR8, PR12, PR16, PR20, fPR24, PR30.  First data output 15 of the first three-bit shift register PR1 for the signaling device. T1 (12) is connected to the first setting inputs 2 of the eighth, twelfth, sixteenth, dyacat, twenty-fourth five-bit shift registers PR8, PR12, PR16, PR20, PR24 and on the third set input 4 of the 28th 5-bit pwsuv register PR29.  The reset inputs P6 of the up to the fourth five-bit sliding register PR1 to PR4 for the T1 (NUL) signal are connected and simultaneously form the 90th input 097 of the wiring, connectable to the time source.  The release inputs of setting 8 of the first and second bits shift registers PR1 and PR2 are connected to the output of the seventeenth inverter INV17.  The release inputs of setting 8 of the third and fourth five-bit shift registers PR3 and PR4 are connected to the eighteenth output.  the inverter INV18, whose input is connected to the input of the seventeenth inverter INV17 for the T1 signal (NAS) and simultaneously forms the fifty-fifth input 059 of the wiring, connectable to the time source.  The serial data input 9 of the first 5-bit shift register PR1 for the signal AU (0) forms simultaneously the 80th input 080 of the connection, connectable to an arithmetic and logical unit (not shown) of the micro-encoder.  The output of the fifth four-input summing gate SSHC5 is connected to the input inverter INV5, the output of which is connected to the fourth setting input 6 of the second five-bit shift register PR2, whose serial input of data 9 for the signal ALJ (1) is simultaneously the seventy-second input 076 wiring, connectable to the arithmetic logic unit of the microprocessor.  Output Six; The fourth four-input total gate SSHC6 is connected to the input of the sixth inverter INV6, the output of which is connected to the third setting and input 4 of the second five-bit sliding register PR2.  The output of the seventh four-input additive gate SSHC7 is connected to the input of the seventh i $ vertoraINV7 whose output is connected to 209222 to the second setting input 3 of the second 5-bit traverse register PR2.  The output of the eighth four-input sum gate SSHC8 is connected to the input of the eighth inverter INV8, the output of which is connected to the first setting input (2 of the second five-bit shift register PR2). The other input 7 of the second 5-bit / shift register PR2 is connected to the zero potential, while its fifth data output 10 is the signal T1 (1) V, which simultaneously forms the 60th output connection 0065, connectable to the control unit; inputs and outputs.  The fourth data output 11 of the second-bit shift register PR2 for the satellite

T1 (1) is connected to the first inputs of the third and fourth random input circuits NSDK3, NSDK4 of the open-collector logic product type, then to the fourth set-up inputs 6 of the seventh, eleventh, fifteenth, nineteenth, twenty-third and thirty-five five-bit shift registers PR7, PRII, PR15, PR19, PR23, PR31, then the second input of the twenty-fourth NSD24 input circuit of the logical product negation and serial data input 9 of the 27th 5-bit shift register R27. The third data output 13 of the second 5-bit shift register PR2 for the signal T1 (5) is connected to the third adjustment inputs 4 of the seventh, eleventh, fifteenth, nineteenth, twenty-third five-bit shift registers PR7, PRII, PR15, PR19, PR23, and the fifth adjusting input 7 of the thirty five-bit sliding register PR30. The expensive data output 14 of the expensive bit-shift shift register PR2 for the signal T1 (9) is connected to the second set-up inputs: 3 of the seventh, eleventh, fifteenth, nineteenth, twenty-third five-bit shift registers PR7, PRII, PR15, PR19, PR23 and the first ' an adjustment input 2 of the thirty five-bit shift register PR30. The first data output 15i of the second five-bit shift register PR15 for the signal T1 (13) is connected to the first adjusting inputs 2 of the seventh, eleventh, fifteenth, nineteenth, twenty-third, five-bit shift registers PR7, PRII, PR15, PR19, PR23 and, secondly, the setting input 3 of the 29th PR29 bit register. The output of the fourth four-input sum coefficient SSHC9 is connected to the input of the ninth inverter INV9, the output of which is connected to the quarterly input 6 of the third five-bit shift register PR3. The output of the tenth four input SSHC10 product gate is connected to the input of the tenth inverter INV10, the output of which is connected to the third setting input 4 of the third trip shift register PR3. The output of the eleventh four-input sum coefficient SSHC11 is connected to the input of the eleventh inverter INV11, whose output is connected a second time to the input input 3 of the third five-bit sliding register PR3. The output of the twelve four input input gate SSHC12 is connected to the input of the twelfth inverter 209222 INV12, the output of which is connected to the first setting input 2 of the third five-bit sliding register PR3. The fifth setting input 7 of the third five-bit shift register PR3 is connected to the zero potential, while its fifth data output 10 for the signal T1 (2) V forms simultaneously the sixty-sixth connection 0066, connectable to the control unit of the inputs and outputs. The fourth data output of the third 5-bit shift register PR3 signal T1 (2) is connected to the first inputs of the fifth and sixth two-input NSDK5, NSDK6 logic product with open collector, to the sixth, sixth, tenth, fourteenth, eighteenth, twenty-second The five-bit shift registerPR6, PR10, IPR14, PR18, PR22, further on the serial! 'Data input 9 of the 26th 5-bit shift register PR26, the third set input i4 of the thirty-first five-bit shift register PR31 and the second input of the twenty-threeth input circuit NSD23 type of negation of logic product. The third data output 13 of the third-bit shift register PR3 for the signal (6) is connected to the third adjusting inputs4 of the sixth, tenth, fourteenth, eighteenth, twenty-second five-bit shift registersPR6, PR10, PR14, PR18, PR22, and the fourth set input 6 of the thirty-five-bit shift register PR30. The second data output 14; the third 5-bit shift register PR3 of the signal T1 (10) is connected to the second adjusting entry 3 of the sixth, tenth, fourteenth, eighteenth, twenty-second five-bit sliding registers PR6, PR10, PR14, PR18, PR22 and the fifth-to-five-five-input input 7 -the shift register PR29. The first data output 15 of the third 5-bit shift register PR3 for the signal T1 (14) is connected to the first setting input 2 of the sixth, tenth, fourteenth, eighteenth, twenty-second and twenty-second five-bit shift registers PR6, PR10, PR14, PR18, PR22 and PR29. The serial input of the data> 9 of the third 5-bit shift register PR3 of the signal AU (2) constitutes the seventy-seventh input 079, which can be connected to the arithmetic and logical unit of the microprocessor. The output of the thirteenth four input input product gate SSHC13 is connected to the input of the thirteenth inverter INV13, the output of which is connected to the fourth setting input 6 of the fourth five bit sliding register PR4. The output of the fourteenth four input SSHC14 product gate is connected to the input of the fourteenth inverter INV14, the output of which is connected to the third setting input 4 of the fourth bit shift register PR4. The output of the fifteenth four input coefficient SSHC15 is connected to the input of the fifteenth inverter INV15, whose output is connected a second time to the input input 3 of the fourth five-bit shift register PR4. The output of the sixteenth four-input sum product gate SSHC16 is connected to the input of the sixteenth inverter input INV16, the output of which is connected to the first setting input 2 of the fourth 5-bit shift register PR4. The fifth set-up input 7 of the fourth-bit shift register PR4 is connected to Ha zero potential, while its serial input dd9 for the signal ALJ (3) forms simultaneously the twenty-second input 029 of the wiring, connectable to arithmetic and logic microprocessor unit. The fifth register PR4 for the signal T1 (3) V forms the seventy-sixth output 0067 connectable to the I / O control unit. The fourth data output11 of the fourth 5-bit shift register PR4 for the signal T1 (3) is connected to the first input of the seven-input two-input circuit NDD7, NSDK8 of the open collector negation type, to the fourth set-up input of the fifth, ninth, thirteenth, seventeenth, twenty-first five-bit sliding PRS, PR9, PR13, PR17, PR21, the second set input 3 of the thirty-first five-tenth shift register PR31, to the serial input, 9 twenty-five five-bit shift register PR25 and the second input of the twenty-second! . The third data output 13 of the fourth ip-bit shift register PR4 for the signal T1 (7) is connected to the third adjusting inputs 4 of the fifth, ninth, thirteenth, seventeenth, two-first and thirty five-bit sliding registers PR5, PR9, PR13, PR17, PR21, PR30.1Data output 14 of the fourth five-bit shift register PR4 for the signal T1 (11) is connected to the second adjustment inputs 3 of the fifth, ninth, thirteenth, seventeenth, twenty-first five-bit shift registers PR5, PR9, PR13, PR17, PR21, and the fourth set-in input 6 of the 28th 5-bit sliding register PR29. The first data output 15 of the fourth-bit shift register PR4 for the signal T1 (15) is connected to the first set-up inputs 2 of the fifth, ninth, thirteenth, seventeenth, two-way five-bit shift registersPRS, PR9, PR13, PR17, PR21 and the second three-input NSD3 of the nega type - ice logic product. The second inputs of the first, third, fifth and seventh two-input circuit, NSDK1, NSDK3, NSDK5, NSDK7 for the T1DOR signal are connected together and form the twenty-fifth input 025 connection, connectable to the time source. The output of the first two-input circuit NSDK1typp'negation of the logic product s the open collector for the RBVS (0) signal is connected, on the one hand, to the resistive R2 of the positive pole + of the power supply source, respectively, to the outputs of the twelfth, sixteenth, twenty-fourth, twenty-eighth and thirty-eighth two-input circuits; NSDK12, NSDK16, NSDK20, NSDK24, NSDK28, NSDK39 open collector negation of the logic product and form simultaneously the third 003 connection, connectable to the arithmetic Ia logic unit of the micsoprocessor + SBUS (O) is connected to the positive pole + power source via the first R1 resistor and to the thirty-second random input circuit NSDK32 of the non-gel product with the open collector and forms the fourth output 004 wiring, connectable; to the arithmetic and logical unit of the microprocessor. The output of the third two-input circuit of the NSDK3 type of negation of the logic product with open- | The same collector for the RBUS signal (1) is connected via the fourth resistor R4 to the positive pole + source of electrical energy, and to the output of the eleventh, fifteenth, nineteenth, twenty-third, twenty-sixth and thirty-eighth double-input circuit NSDK11, NSDK15, NSDK19, NSDK23, NSDK27, NSDK38 the type of negation of the logic product with the open collector and at the same time forms the seventh output 007 of the wiring, connectable to the arithmetic and logical unit of the microprocessor. The output of the fourth two-input circuit of the NSDK4 type of negation of the logic product with the open collector for the SBUS signal (l) is connected to the output of the thirty-first two-input circuit of the NSDK31 type of negation of the logic product with the open collector. electrical energy and simultaneously form the eighth output 008 of the wiring, 1 connectable to the arithmetic and logical single-microprocessor. The output of the fifth two-input NSDK5 type of negation of the logic product by the open collector for the RBUS signal (2) is connected both through the sixth resistor R6 to the positive + power source, and to the eighteenth, fourteenth, eighteenth, twenty-second, twenty-sixth, thirty-sixth two-input circuit NSDK10 , NSDK14, NSDK18, NSDK22, NSDK26, NSDK37, type of logic product with open collector ^ and simultaneously form ninth output 009 wiring, connectable to arithmetic and logical unicroprocessor. The output of the sixth input NSDK6 of the type of negation of the logic product by the open collector for the SBUS signal (2) is connected both through the fifth resistor R5 to the positive pole ·, 1 + of the power supply, and to the thirtieth, two-input circuit NSDK30 of the negation of the logic product with the open the collector and at the same time form the tenth output 0010 of the wiring, connectable to the arithmetic and logical unit of the microprocessor. The output of the seventh two-input circuit NDD7 of the logic product negation with the open collector for the RBUS signal (3) is connected via the eighth resistor R8 to the + pole + source I, and to the ninth output | the thirteenth, seventeenth, twenty-first, two-thirteenth and thirty-sixth two-input circuits of the NSDK9, NSDK13, NSDK17, NSDK21, NSDK25, NSDK36 open collector-type negation and form the thirteenth [output 0013 wiring, connectable to arithmetic 209222 and logical unit. The output of the eighth double-input circuit NSDK8 of the type of negation of the logical product for the SBUS signal (3) is connected both by the resistive resistor R7 to the positive pole + the power source, and by the output of the twenty-second input circuit NSDK29 of the type of non-cellular product with the open collector and simultaneously forms the fourteenth output 0014 of the wiring , connectable to the arithmetic and logical unit of the microarray. Zero inputs 16 fifth, sixth, sed-; the 5 and 5-bit shift registers PR5, PR6, PR7, PR8 for R1 (NUL) are; connected and form simultaneously the twenty-second input 026 of the wiring, connectable to the time source. The clock inputs 1 of the fifth to eighth five-bit shift registers PR5 to PRS for signal R1 (HOD) are connected and simultaneously form the 27th input 027 of the wiring, connectable to the time source. Release inputs of setting 8 of the fifth and sixth five-bit sliding registers PR5, PR6 are connected to the output of the twenty-first inverter INV21. Release inputs for setting 8 of the seventh and eighth bits shift registers PR7, PR8 are connected to the output of the twenty-second inverter INV22, the input of which is connected to the input of the twentieth hopper inverter INV21 and simultaneously forms two-; eighth input 028 wiring for R1 signal (NAS), connectable to time source. The first data output 15 of the fifth five-bit shift register PR5 for the signal R1 (15) simultaneously forms the 16th output terminal 0016, connectable to a microprocessor control unit (not shown). The fourth data output 11 of the fifth five-bit shift register PR5 for the signal R1 (3) is connected to the serial input 9 of the fifth five-bit shift register PRSa to the first input of the ninth two-input circuit! NSDK9 type negation logic product with open-! collector. The fourth data output 11 of the sixth five-bit shift register PR6 for the signal

R1 (2) is connected to serial input data 9 of the six-bit shift register PR6 and to the first input of the tenth two-input circuit NSDK10 of the logic product negation with open collector. Fourth Data Output 11 of the Seventh Five - | PR7 shift register for the signal. R1 (l) is connected to serial data input 9 of the seventh five-byte and the first input of the eleventh two-input NSDK11 circuit of the logic product negation with the open collector. The fourth data output 11 of the eighth five-bit shift register PR8 for the signal R1 (0) is connected to the serial data input 9 of the eighth five-bit shift register PR8 and the first one enters the twelfth two-input circuit NSDK12 of the logic product negation. and at the same time forms the fifteenth output 0015 of the wiring, connectable to the microprocessor control unit. The second inputs of the ninth to twelfth twin- The NSDK9 to NSDK12 flip-flop flip-flop with open collector is connected to form the 30th input 030 wiring for the R1DOR signal, connectable to

209222 time source. The release inputs of the settings 8 ' and 10 ' of the 5-bit shift registerPR9, PR10 are connected to the output of the twenty-third third INV23 inverter. Release inputs of setting 8 of the eleventh and twelfth five-bit sliding registers PRII, PR12 are connected to | the output of the twenty-fourth inverter INV24, the input of which is connected to the input of the twenty-third inverter INV23 and simultaneously forms the thirty-third input 033t of the wiring for signal R2 (NAS), connectable to the time source, zero inputs 16 of the ninth to! the twelfth five-bit shift register PR9 to PR12 for signal R2 (NUL) are connected and simultaneously form the thirty-first input 031 of the wiring, connectable to: time source. Hourly inputs 1 of the ninth to twelfth five-bit shift registers: PR9 to PR12 for signal R2 (HOD) are connected, and at the same time form the thirty-second input 032 of the wiring, connectable to time, swarm. The first data output15 of the ninth five-bit! The fourth data output 11 of the 9-bit shift register PR9 for signal R2 (3) is connected to serial data input 9 of the 9-bit shift register PR9 and to the first input; the thirteenth two-input shift register PR9 for signal R2 (3) is connected to the signal processor R2. The fourth data output 11 of the tenth-bit shift register PR10 for the signal is connected to serial data input 9 of the 10th bit shift register PR10 and to the first input of the fourteenth two-input circuit NSDK14 of the logic product negation with the open collector. the data output 11 of the eleventh five-bit shift register PRII for R2 (l) is connected to the serial input of the eleventh five-bit shift registerPr and the first input of the fifteenth two-input circuit NSDK15 type The fourth data output 11 of the 12th 5-bit shift register PR12 for signal R2 (0) is connected to the serial input data9 of the twelfth five-bit shift registerPR12 and to the first input of the 16th two-input circuit NSDK16 of the open-collector negation logic-type negation. The second inputs of the thirteenth to sixteenth two-input circuit of the open collectorNSDK13 to NSDK16 are connected to form the thirty-eighth input 038 of the connection for the R2DOR signal, connectable to the time source. output of twenty-fifth inverter INV25. Release inputs for setting the 8th and 16th five-bit shift registers PR15, PR16 are connected to the output of the twenty-sixth inverter INV26, whose input is coupled to the input of the twenty-fifth inverter INV25a, forming the thirty-third input 036 of the signal connection R3 (NAS), connectable to the time source. 14

The zeroing inputs 16 of the thirteenth to sixteen bit bits shift register PR13 to PR16 for signal R3 (NUL) are connected and form simultaneously the thirty-third input of wiring 034 wiring, connecting. time source. The clock inputs 1 of thirteenth to sixteenth five-bit shift registerPR13 to PR16 for signal R3 (HOD) are connected and form simultaneously the thirty-fifth input 035 connection,:! time source connectable; The first data output15 of the thirteenth five-bit shift registerPR13 for address address R3 (15) forms simultaneously; the eighteenth output 0018 engages the main memory, whereas its second data output 14.1 for the address signal R3 (11) simultaneously constitutes the nineth output 0019 of the connection, connectable to the main memory. The third data output 13 of thirteen-bit p-1j3 (7) simultaneously forms the twenty-output 0020 interconnectable to the main memory, while its quadruple output 11 of the address signal R3 (3X is connected to the serial data input 9 of the thirteenth pounding slider) register PR13 and on the first seventeenth two-input NSDK17 of the logic product negation with the open collector and simultaneously form the twenty-first output 0021connectable to the main memory The first data output 15 of the fourteenth five-bit shift register PR14 for the address signal R3 (14) forms at the same time twenty-second output 022 wiring, connectable to main memory, while its second data output 14 for address signal R3 (10) simultaneously forms twenty-third output 0023 wiring, connectable to the main memory, third data output 13-14 five-bit shift register PR14 for address signal R3 (6 ) tv simultaneously outputs the twenty-fourth output 0024 of the wiring, connectable to the master memory, while its fourth data output 11 of the address signal R3 (2) is connected to the serial input 9 of the fourteenth five-bit shift registerPR14 and the first input of the eighteenth two-input circuit of the logic-type negation NSDK18 with open collector and form the current fifth output 0025 wiring, connectable, main memory. The first data output 15 of the fifteen-bit shift register PR15 for the address signal R3 (13) simultaneously forms the twenty-second output 0026 of the connection, connectable to the main memory, while its second data output 14 for the addressing signal R3 (9) simultaneously forms the 27th output0027 of the connection , connectable to main memory. The third output 13 of the fifteenth five-bit shift register PR15 for address signal R3 (5) is simultaneously a twenty-second output 0028 connected connectable to the main memory, whereas its quarterly output 11 for the address signal R3 (1) is connected to the serial data input 9 of the fifteenth five-shift shift the register PR15 and the first input of the nineteenth two-input circuit NSDK19 of the logic product negation with the open collector and form simultaneously the 27th output 0029 of the connection, connectable to the main memory. The first data output 15 of the sixteenth five-bit shift register PR16 for address signal R3 (12) forms at the same time the thirtieth output 0030 wiring, connectable [to the main memory, while its data output 14 pro; the address signal R3 (8) simultaneously forms the thirty-first output 0031 of the wiring, connectable to the main memory. The third data output 13 of the sixteenth five-bit shift register PR16 for the address signal R3 (4) simultaneously forms the thirty-second output 0032Connection, connectable to the main memory, while the fourth data output 11 for the address signal R3 (0) is connected to serial; the data input 9 of the 16-bit shift register PR16 and the first input of the twenty-two-input circuit of the logical product negation type NSDK20 with the open collector and simultaneously form the thirty-third output connection, connectable to the main memory.

The second inputs of the seventeenth through twenty-input NSDK17 to NSDK20 circuits of the type, the negation of the logic product with the open collector, are connected to form the 37th input: 037 wiring for the R3DOR signal, a connectable timing source. The release inputs of setting 8 of the 17th and 18th five-bit sliding registers PR17, PR18 are output; twenty-sixth inverter INV26. Releasing; the setting inputs 8 of the nineteenth and twenty-five-bit shift registers PR19, PR20 are [connected to the output of the twenty-seventh inverter; INV27, the input of which is connected to the input of the twenty-sixth inverter INV26 and simultaneously forms the fourth first input 041 of the wiring for the signal Q (NAS); connectable to Time Source. Zero Inputs 16 I The seventeenth to twenty five-bit shift registers PR17 to PR20 are connected to form the 37th input 039 wiring for * 1 signal Q (NUL), connectable to time source, iHour inputs 1 to 17th [5-bit shift register PR17 to PR20] they are connected and form simultaneously the 40th input 040i of the wiring for the Q (HOD) signal, the connectable timing source. The first data output 15 of the 17-bit shift register PR17 for the signal Q (15) simultaneously forms the fifth output 005 of the connection connectable to the microprocessor control unit, while its second data output 14 for the signal Q (11) simultaneously forms the sixth output 006 of the connection connectable to the microprocessor control unit. The third data output 13 of the seventeenth five-bit sliding register PR17 for the signal Q (7) forms the 11th output 0011 of the connection, connectable to the microprocessor control unit, while the fourth data output 11 for the signal Q (3) is connected to the serial data input 9 of the seventeenth bit shift register PR17 and to the first input of the twenty-first two-input circuit of the NSDK21 type of negation of the logic product with the open collector and simultaneously form the twelfth output0012 of the wiring, connectable to the control unit microprocessor. The first data output 15 of the eighteenth five-bit shift register PR18 of the signal Q (14) simultaneously forms the thirty-fourth output0034 of the connection, connectable to the microprocessor control unit 209222, while its second data output14 for the signal Q (10) forms at the same time the thirty-fifth output 0035 of the connection, connectable to the control unit. -k microprocessor. The third data output 13 of the 18th 5-bit shift register PR18pró signal Q (6) simultaneously constitutes the thirty-thirty output connection 96, connectable to the control unit microprocessor, while its fourth data output 11 for signal Q (2) is connected to serial data input 9 of the eighteenth five-bit shift registerPR18 and on the first input of the twenty-second NSDK22 open-collector negation-type two-input circuit forming the current thirty-seventh output 0037 of the wiring connectable to the microprocessor control unit. The first data output 15 of the nineteenth five-bit shift register PR19 for the signal Q (13) constitutes at the same time the thirty-third output 0038 of the wiring, connectable to the microprocessor control unit, while its second data output 14 for the signal Q (9) forms at the same time the thirty-third output 0039 of the wiring, connectable to the microprocessor control unit. The third data output 13 of the nineteenth five-bit shift register PR19 for the signal Q (5) forms at the same time the forty-four output 0040 of the wiring, connectable to the microprocessor control unit, while its quarter-output output 11 for the signal Q (l) is connected to serial data input 9 of the nineteenth five-bit shift register PR19 and to the first input of the twenty-third two-input circuit NSDK23 of the logic product unification with open collector forms at the same time the forty-first output 0041 Connection, connectable to the microprocessor control unit. on the microprocessor control unit, while its second data output 14 for the signal (8) forms at the same time the forty-fourth connection, connectable to the microprocessor control unit. 13 of the twenty-five-bit sliding register PR20 for the signal Q (4), at the same time the forty-fourth output 0044 of the wiring, connectable to the microprocessor control unit, while its fourth data output 11 for the Q (0) signal is connected to serial data input 9 of the twenty-bits shift register PR20 and the first input of twenty-fourth. the logic product negation of the two-input circuit NDD24 with the open collector and simultaneously form the 45th connection 0045, connectable to the microprocessor control unit. The second inputs of the twenty-first to twenty-fourth two-input circuit of the open collectorNSDK21 to NSDK24 are connected and form simultaneously the forty-second input 042 of the wiring for the QDOR signal, connectable to the time source. output of the 28th inverter INV28. Release Inputs Setting 8 Twenty-Second and Twenty-P 16

209222 of the fourth five-bit shift register PR23, PR24 are connected to the output of the twenty-second inverter INV29, the input of which is connected by the 28th inverter INV28 and at the same time forms the forty-fifth input 045 wiring for the signal, NAS, connectable to the time source. Zeroing inputs 16 of the twenty-first to twenty-fourth, five-bit shift registers PR21, PR24 are connected and form at the same time the forty-third input 043 of the wiring for the P (NVL) signal, connectable to the time source. Hourly inputs 1 of the twenty-first to fourth-fourth five-bit sliding regis- ter. PR21 to PR24 are connected and form at the same time forty-fourth input 044 wiring for signal 1P (HOD), connectable to Time source. The quarterly output 11 of the twenty-first five-bit sliding register PR21 for the signal P (3) is connected to the serial input 9 of the twenty-first three-bit shift register PR21 and the first input of the twenty-second two-input circuitNSDK25 of the negation of the logic product with the open collector ^ The fourth data output 11 of the twenty- the second five-bit shift register PR22 for the signal P (2) is connected to the serial input dat9 of the twenty-second five-bit sliding ^ PR22 and to the first input of the twenty-sixth input circuit NSDK26 of the non-gel product with the open collector. The four-week output 11 of the twenty-third five-bit sliding register PR23 for the signal P (1) is connected to the serial input 9 of the twenty-third five-bit shift register PR23 and to the first input of the sixth two-input circuit NSDK27 of the logic product negation with the open collector. The fourth data output 11 of the fifth-fourth quad-bit shift register PR24 for the signal P (0) is connected to the serial input of the data9 and the first open-collector negation of the twenty-second NSDK28 negation logic type. The second ninety-to-twenty-eighth open-collector NSDK25 to NSDK28 non-germinal product of the open-collector type is coupled to form the forty-eighth approach 046connection for the PDOR signal, a connectable non-timing source. The release inputs of setting 8 of the 25th and 26th of the 5-bit shift registers PR25, PR26 are connected at the output of the thirty inverter INV30. Release and input settings 8 of the 27th and 28th 5-bit shift registers PR27, PR28i are connected to the output of the thirty-first inverse of INV31, the input of which is connected to the input of the thirty-fifth inverter INV30 and connected to the output of the second three-input circuit NST2 of the non-glogic product for the signal K (NAS), the first input of which for the TC signal is simultaneously the forty-eighth connection 048, connectable to a time source, the second input of which for the TE signal is the 43th input 049 of the connection, connectable to a time source. The third input of the second and the first three-input NST2 and NST3 of the logical product negation is connected to form the 50th input 050 of the connection for the signalROM (22) connectable to the ROM control memory. ; The second input of the third logical product negation NST3 of the third logical product negation circuit for the ID signal constitutes at the same time the fifty-first input 051 of the wiring, the time source being connectable, while the third input signal, the TOSC simultaneously forms the wiring of the 52 wiring, connectable to the time source. The output of the third three-input NST3 non-negogenic product circuit for the K (NUL) signal is connected to the reset inputs 16 of the 25th to dyacate-eighth shift five-shift shift register PR25 'to PR28. The clock inputs 1 of the 25th to 28th 5-bit sliding registers PR25 to PR28 are connected to form a 43th input 047 connection for the iT1 signal (HOD), connectable to a time source. The first setting input 2 of the 24th 5-bit sliding register PR25 for the ROM signal (2f simultaneously forms the fifth input 054 of the connection, connectable to the ROM control memory, while the second setting input 3 for the ROM17 signal is connected to the second input of the sixth three-input circuit NST6 of the logical product negation and the first input of the twenty-second the logical-product negation of the two-input circuit NSD21, and at the same time, the fifty-fifth input055 connection, connectable to the ROM control memory The third set-up input 4 of the 25th 5-bit slider PR25 for the ROM signal (13) constitutes at the same time the fifth input 056 of the wiring, connectable to: ROM control memory , while its fourth setting input 6 for the ROM signal (9) forms the 7th input 057 of the wiring, the connectable directing memory of the ROM type and its fourth data output 11 for the signal K (3) is p vstupdvacátéhodevátého connected to the first two-input circuit; NSDK29 type negation of a logical product with open-collector Nym. The second setting input 3 of the two-sixth six-bit shift register iPR26 for the ROM signal (16) is connected to the first input of the fourth three-input circuit NST4 of the logical product type, and the second input of the two-input dual input circuit NDD21 of the logical product negation and forms the current input 060 wiring, controllable control memory ROM type, while its third set input 4 for ROM signal (12) forms simultaneously the sixty-first input 061 of the wiring, connectable to the ROM control memory, and its quarterly input 6 for the ROM signal (8) forms the sixty-second wiring input 062 connectable to the control a ROM type memory, the fourth data output 11 for the K (2) signal being connected to the first input of the 30th logical product negation circuit NSDK30 with the open loop. The first setting input 2 of the twenty-seventh five-bit shift register PR27 for the ROM signal (19) is simultaneously sixty: the third input 063 of the wiring, connectable to the ROM control memory, while its second setting • 17 ί input 3 for the ROM signal (15) it simultaneously constitutes the sixty-fourth input 064 of the wiring, connectable to the ROM control memory, and its third input input 4 for the ROM (11) simultaneously forms a 60th wiring output 065, connectable to the ROM control memory. The fourth setting input 6 of the twenty-seventh five-bit shift register PR27 for the ROM signal (7) simultaneously constitutes the sixty-sixth connection 066, connectable to the ROM control memory, whereas its fourth data output 11 for the K (l) signal is connected to the first input of the thirty-hop NSDK two-input circuit The first setting input 2 of the 28th 5-bit shift register PR28 for the signalROM (18) simultaneously constitutes the 67th input 067 of the connection, connectable to the ROM control memory, while its second setpoint 3 for the signal RQM (14) forms at the same time the 60th input 068 of the wiring, connectable to the ROM control memory, its third input input 4 for the signalROM (10) is simultaneously the sixty-sixth input 069 of the wiring, connectable to the ROM control memory. the shift register PR28 for the signalROM (6) simultaneously forms the seventyth input 070 of the connection, connectable to the ROM control memory, while its fourth data output 11 for the signal K (0) is connected to the first input of the thirty-second random input circuit NSDK32 of the open-collector type. The second logical-to-product-type three-input NST4 circuit three-input circuit for the ROM signal (17) is connected to the first input of the fifth three-input NST5 logical product negation circuit, and simultaneously constitutes the seventy-seventh input 077connectable to the ROM control memory, whereas its output is connected to the thirty-fifth inverter INV35 input whose output for the 1DOS signal is connected to the second input thirty-third! two-input circuit NSDK33 of negation of open-collector logic product and input of first to fourth inverter INVK1 to: INVK4 with open collector. The output of the first open-collector INVK1 is connected to the output of the twenty-second NSDK29 double-input open-collector negation type. The output of the second open INVK2 inverter with open collector is connected to the output of the thirty-two-input circuit of the NSDK30 type of negation by the open collector. The output of the third open-collectorINVK3 inverter is connected to the thirty-first two-input circuit of the NSDK31 of the logic product negation with the open collector. The output of the fourth open-collectorINVK4 inverter is connected to the thirty-second two-input circuit of the NSDK32 of the logic product negation with the open collector. The second input of the fifth three-input circuit NST5 of the logical product negation type ROM (16) is connected to the first input 209222 of the sixth three-input circuit NST6 of the negogenic product type and forms simultaneously the seventh input 078 of the connection, connectable to the ROM control memory while its output is connected to the input of the thirty-sixth inverter INV36, whose output for the ODOS signal is connected to the second input of the thirty-fourth of the two-input circuit NSDK34 of the logic product negation with the open collector. The output of the sixth input circuit NST6 of the logical product negation is connected to the input of the thirty-seventh inverter INV37, whose output for the signal T1DOS is connected to the input of the fifth inverter INVK5 with the open collector and to the second inputs of the second, fourth, sixth and eighth two-input circuit NSSK2, NSDK4, NSDK6 and NSDK8 open collector. The output of the twenty-first two-input circuitNSD21 of the logic product negation is connected to the first input of the twenty-two-input circuit NSD20 of the logic product negation, whose output for the KDOS signal is connected to the first input of the thirty-third two-input circuitNSDK35 of the negation of the logic product with the open collector and to the other inputs of the twenty-second. up to the thirty-second two-input circuitNSDK29 to NSDK32 of the open-collector logic type. The outputs of the thirty-third to thirty-two two-input circuit NSDK33 to NSDK35 of the open-collector logic type and the fifth-inverter INVK5 open-collector are connected and connected via the twenty-fifth resistor R25 to the positive + power source, and to the input 21 of the second AT2 flip-flop. (15) of type D whose zero output 202j for signal T2 (15) is connected to the first input of the thirty-third two-input circuit NSDK33 of the logic product negation with open collector, to serial input 9 of the twenty-ninth five-bit shift register PR29, to the fourth input the sixteenth four-input sum of the product gate SSHC16 and the first input of the fourth two-input circuit NSD4 of the non-logical product type. Hourly Entry 22 Second-; AT2 (15) type D flip-flop for T2 (HOD) signal is connected to clock inputs 1 of twenty-thirty to thirty-five five-bit sliding register PR29 to PR31 and at the same time forms input 053 of wiring, connectable timing source. The zeroing inputs 16 of the twenty-thirty-to-thirty-five five-bit shift register PR29 to PR31 for the signal T2 (NUL) are connected and connected to the setting input 24 of the second flip-flop AT2 (15) of the type D and form the fifty-fifth input 058 of the wiring connectable to the time source. The inputs of the thirty-second and thirty-third inverter INV32 and INV33 signal T2 (NAS) are connected and make up the seventy-first 071 wiring, a connectable timing source. The output of the thirty-second inverter INV32 is connected, on the one hand, to the first input of the third 209222 18 of the two-input circuit NSD3 of the logic product negation, the output of which is connected to the reset input 23 of the second AT2 (1S) flip-flop typeD, and to the release input of the twenty-fifth five-bit shift registerPR29 . The output of the thirty-third inverter INV33 is connected to the release inputs 8 of the thirty and thirty-hop five-shift shift register PR30a PR31. The first data output 15 of the 28th 5-bit shift register PR29 of the signal T2 (14) is connected to the fourth input of the twelve four-input additive product gate SSHC12 and the first input of the fifth two-input circuit NSD5 of the logic product negation whose output for the data signal T2 (14 ) M forms the currently forty-eight output 0049 wiring, connectable to main memory. The output of the quarter-time input circuit NSD4 of the logic product negation type for data signal T2 (15) M constitutes at the same time the forty-eighth output 0048 of the wiring, connectable to the main memory. The second data output14 of the 28th 5-bit shift register PR29 for the signal T2 (13) is connected to the fourth input of the eighth input four-input sum gate SSHC8 and to the first input of the sixth input circuit of the NSD6 of the logic product negation, whose output for data signal T2 (13) M forms simultaneously 50th output 0050connection, connectable to main memory. The third data output 13 of the 28th 5-bit shift register PR29 for the signal T2 (12) is connected to the fourth input of the fourth sum coefficient SSHC4 and to the first input of the seventh double-input circuit NSD7 of the negation of the logical origin whose output for the data signal T2 (12) At the same time, the fifty-first output 0051 is connected to the main memory. The fourth data output 11 of the 28th 5-bit shift register PR29 for the signal T2 (II) is connected to the fourth input of the fifteenth four-input sum of the product gate SSHC15 and to the first input-input dual input circuit NSD8 of the logical product type whose output for the data signal T2 (11) M forms simultaneously the fifty-second output 0052 of the wiring, connectable to the main memory. The fifth data output 10 of the 28th 5-bit shift register PR29 for the signal T2 (10) is connected to the fourth input of the eleventh four-input sum gate SSHC11, serial data input 9 the thirtieth five-bit shift register PR30 and, at the first input of the ninth-input logical product negation NSD9, whose output for the data signal T2 (10) M simultaneously forms the fifty-third output 0053 of the connection, connectable to the main memory. The first data output 15 of the thirty-five-shift slider P30 for the signal T2 (9) is connected to the fourth input of the seventh sum of the product gate SSHC7 and the first input of the tenth two-input circuit NSD10 of the logic product negation, whose output for the data signal T2 (9) M is simultaneously the fifty-fourth output 0054 wiring, connectable to main memory. The second data output 114 of the thirty-bit shift registerPR30 for the signal T2 (8) is connected to the fourth input of the third four-input sum coefficient SSHC3 and to the first input of the eleventh input circuit NSD11 of the logical product negation type whose output for data signal T2 (8) simultaneously forms fifty-fifth output Wiring, connectable to main memory. The third data output 13 of the thirty-five-bit shift register PR30 for signal T2 (7) is connected to the fourth input of the fourteenth four-input cumulative gate SSHC14 and to the first input of the second two-input circuit NSD12 the logic product type whose output for the data signal T2 (7) M forms simultaneously the fifty-fifth output0056 The fourth data output 11 of the thirty-five-bit sliding register PR30 for signal T2 (6) is connected to the fourth input of the tenth four-input product gate SSHC10 and to the first input of the thirteenth two-input circuit NSD13 of the logic product negation whose output signal T2 (6) M at the same time they form the fifty-seventh output 0057 of the wiring, connectable to the master memory. The fifth data output 10 of the thirty-five-bit shift register PR30 for the signal T2 (5) is also connected to the fourth input of the sixth four-input sum gate SSHC6, to serial; the data input 9 of the thirty-first five-bit shift register PR31 and the first input of the fourteenth of the two-input circuit NSD14 of the logical product negation, the output of which for the data signal T2 (S) simultaneously forms the fifty-eighth output 0058 of the connection, connectable to the main memory. The first data output 15 of the thirty-first five-bit shift register PR31 for the signal T2 (4) is connected to the fourth input of the second four-input additive gate SSHC2 and the first input of the fifth two-input circuit NSD15 is the logic product type whose output for the data signal T2 (4) M forms simultaneously the fifth output 0 <V59 connection, connectable to the main memory. The second data output 14 of the thirty-first five-bit shift register PR31 for the signal T2 (3) is connected to the fourth input of the thirteenth four-input product gate SSHC13 and the first input of the 16th two-input circuit NSD16type of the logic product negation , whose output signal T2 (3) M forms at the same time the 60th connection 0060, connectable to the main memory. The third data output 13 of the thirty-first three-bit shift register PR31 for the signal T2 (2) is connected to the fourth input of the ninth four-speed sum gate SSHC9a to the first input of the seventeenth two-input circuit NSD17 of the negation of the logic product, whose output for the data signal T2 (2) M is the 60th output 0061 wiring, connectable to main memory. The fourth data output of the thirty-first five-bit shift registerPR31 for the signal T2 (l) is connected to the fourth input 19 209222 of the fifth four-input sum coefficient SSHC5 and the first input of the eighteenth two-circuit circuit NSD18 of the negation of the logic factor whose output for the data signal T2 (1) sixty-second output 0062 connectable to main memory. The fifth data output 10 of the thirty-first five-bit shift register PR31 for the signal T2 (0) is connected to the second input of the thirty-second two-input circuit NSDK35 of the negation of the logic product by the open collector, to the fourth input of the first four-input sum of the product gate SSHC1 and to the first input of the nineteenth two-input circuit NSD19 the type of negation of a logical element whose output for the data signal T2 (0) simultaneously constitutes the 60th output 0063 wiring, connectable to the main memory. The second input of the quarter-input NSD4 logic product negation circuit for the EXT signal (15) is connected to the positive resistor R9 to the + pole of the power supply and simultaneously forms the 80th input 081 of the wiring, connectable to external circuits. The second output of the fifth two-input circuit NSD5 of logic product unification for the EXT signal (14) is connected via the tenth resistor R10 to the positive + power source and constitutes the eighty-second input 082 of the wiring, connectable to external circuits. The second input of the sixth NSD6 double-input circuit of the logic-type negation for the EXT (13) signal is connected by a uniquely resistive Rll to the + pole of the source of electrical energy, and simultaneously forms a 083 wiring, connectable to external circuits. The signalEXT (12) is connected via the twelfth resistor R12 to the load pole + power supply and forms simultaneously the 80th input 084 wiring, connectable to external circuits. The second input of the eighth input NSD8 type of the non-negogenic product for the EXT (ll) signal is connected through the thirteenth resistor R13 to the positive + source of the electric energy and simultaneously forms the 085 wiring 085 wiring, connectable to external circuits. The signalEXT (10) is connected via the fourteenth resistor R14 of the load pole + power supply and forms simultaneously the 80th input 086 of the wiring, connectable to external circuits. The second input of the tenth coincidence NSD10 of the logic product negation for the EXT signal (9) is connected to the fifteenth resistor R15 to the + ve positive + source of electrical energy and simultaneously forms an eighty-eight input 087 wiring, connectable to external circuits. The second input of the eleventh two-input circuit NSD11 of the negation of the logical product for the signal EXT (8) is connected via the 16th resistor R16 to the positive pole + the power sources simultaneously form the 80th input 088 connect ε-πί, connectable to external circuits. The second input of the twelfth two-input circuit NSD12 of the logic product negation for the EXT signal (7) is connected via the seventeenth resistor R17 to the positive + power supply and forms the 80th input 089 of the wiring, connectable by external circuits. The second input of the 13th NSD13 logic-type negation circuit for the EXT signal (6) is connected via the 16th resistor R18 to the positive + power source, and simultaneously forms the ninety-second wiring, connectable to external circuits. The second output of the fourteenth two-input NSD14 circuit of the logic product negation for the EXT signal (5) is connected via the nineteenth R19 resistor to the positive pole + power supply and forms the 95th first input 091 wiring, connectable to external circuits. The second input of the fifteenth two-stage NSD15 circuit of the logic-type negation for the EXT (4) signal is connected via the twenty-second R20 to the + + power source and forms the 90th input092 wiring, connectable to external circuits. The second input of the 16th two-input circuit, NSD16, The signalEXT (3) is connected via the twenty-first resistor R21 to a positive pole + power source and forms the ninety-third input 093 wiring, connectable to external circuits. The second input of the seventeenth two-input circuit NSD17 of logic product unification for the EXT signal (2) is connected via the twenty-second resistor R22 to the positive pole + power supply and forms the 96th input 094 wiring, connectable by external circuits. The second input of the eighteenth input circuit NSD18 of the logical product negation type for the EXT (l) signal is connected through the thirty-third resistor R23 to the positive + source of electrical energy and simultaneously forms ninety-fifth input 095 wiring, connectable to external circuits. The logical product of the EXT signal (0) is connected via the twenty-fourth R24 to the positive + power supply and simultaneously forms the ninety-sixth input 096 of the wiring, connectable to external circuits. The second input of the thirty-sixth to thirty-sixth input circuit NSDK36 to NSDK39 of the logic product negation with the open collector for the EDOR signal is connected and simultaneously forms a 70 second input connection, connectable to a time source. The setting inputs34, 44, 54, 64 of the third to sixth flip-flop AE3, AE2, ΑΕΙ, ΑΕ0 type D for the signal E (NUL) are connected and simultaneously form a seventy-third connection 073, connectable to a time source, whereas their basic inputs 31, 41, 51 61 are connected to the + pole of the electrical power source and their clock inputs 32, 42, 52, 62 for the HOD signals are coupled to form a seventy-fourth wiring input 074, connectable to a time source. The zero output 302 of the D-type third AE3 flip-flop circuit for the E3 signal is connected to the first input of the logic product negation of the 36th two-input circuit 20 209222 of the NSDK36, whereas its reset input 33 is connected to the output of the twenty-second NSD22 of the logic-type negation. The zero output 402 of the fourth flip-flop AE2 type D for the signal E2 is connected to the first input of the thirty-first two-input circuit of the NSDK37 type of negation of the logic product by the open collector, whereas its zeroing input 43 is connected to the output of the second input of the input circuit NSD23 of the logical product negation. The zero output 502 of the fifth flip-flop AE1 of type D for the signal E1 is connected to the first input of the thirty-eighth double-input circuit of the NSDK38 type of negation of the logic product by the open collector, whereas its reset input 53 is connected to the output of the twenty-fourth input circuit NSD24 of the logical product negation. The one-way output 601 of the D-type six-way AEO circuit for the EO signal constitutes at the same time the forty-fourth output 0046 of the wiring, connectable to the microprocessor control unit. The input input 63 of the 6th flip-flop AEO typufc> is connected to the output of the twenty-fifth two-stage circuit NSD25 of the negation type, whereas its zero output 602 for the signal E0 is connected to the first input of the thirty-fourthhour input circuit NSDK34 of the type of the non-gel product with open collector, of the two-input NSDK39 circuit of the type of negation of the logic product by the open collector and simultaneously form the forty-, seventh output 0047 of the connection, connectable to the microprocessor control unit. The input of the thirty-fourth inverter INV34 for the signal E (NAS) consists of the seventy-fifth input 075 of the wiring, a connectable time source, whereas its output is connected to the first inputs of the twenty-second to twenty-two two-input circuit NSD22 to NSD25 of the logical product negation.

As the five-bit shift registers PR1 to PR31, a known circuit is used, which is schematically shown in Fig. 2.

The wiring of the processor for the intelligent terminal is composed of a TI battery (FIG. 1g, h), a Q condition register (FIG. 1d), a macroinstruction counter (FIG. 1e), a K register (FIG. 1f), a T2 data-register (FIG. 1, j), the transmission register E (FIG. 1k), the first working register R1 (FIG. 1a), the second working register R2 (FIG. 1b) and the address register R3 (FIG. 1c), and cooperates with arithmetic and not shown circuits logical units according to. copyright certificate No. 209221, time sources according to MS. author's certificate No. 198987a microprocessor control unit according to MS. copyright certificate no. 201557.

The first working register R1 is a serioparal six-bit register with parallel input and a four-bit serioparal output. The information is transferred from the TI accumulator in parallel to the first working register R1 by means of the signals T1 (0) to T1 (15). These signals are controlled by additional R1 (NUL), R1 (NAS) signals. The signal R1fNUL) resets the first working register R1 in time T4B (FIG. 4) and the signal R1fNAS) transfers the content of the accumulator T1 to the first working register by means of said signals T1 (0) to T1 (15). The conversion is performed according to the T microninstruction code Tbus - »R1 (Fig. 3). The serioparal output from the first working register R1 is controlled by the clock signal R1fHOD), depending on the code H in the microinstruction, i.e. 1 to 4 pulses in times T0 to T3. The clock pulses come in 027 for the RlfHOD signal only if the R code of the R1-Rbus microinstruction is Rbus. Furthermore, the clock pulses are conditionally gated depending on the condition code in the microinstruction. The output of the first working register R1 is brought to the bus R by signals RBUSf0) to RBUSf3) if the signal R1DOR is in logic 1. The signal klDOR is controlled by the code R of the microinstruction R1 -> Rbus. The bus R is connected to the input of an arithmetic logic unit (not shown) controlled by the ALJ microinstruction code. The first working register R1 operates simultaneously as a T bus switch, see signals T1 (0) to T1 (15) with a serioparal recirculation of the contents of the first working register R1. If the conditions for the presence of the clock pulses are fulfilled, the register contents are shifted through the arithmetic and logical unit to the accumulator T1a, while the original content is maintained in the first working register R1 or shifted by the selected number of four-bit words, according to the number of clock pulses given in the microinstruction. If the above conditions for converting the TI battery contents into the first working register R1 are fulfilled, then the original content of the first working register R1 is replaced by a new result of the operation that has been performed in the arithmetic and logical unit.

Analogously to the first working register R1, the second working register R2 operates, with the difference that the transfer from the accumulator T1 occurs in the state Tbus R2 of the code T microinstruction, the hourly im-pulses are enabled to set R2 -> Rbus codeR microinstruction and output of the second working register R2 is switched on R bus in R2 state - »Rbus code R.

It is possible to use address register R3 (such as registers R1 and R2, but in addition signals R3 (0) to R3 (15) perform addressing of the main memory of the processor to read data from the main memory to the accumulator T1 or write data data register T2 to the main memory of the processor Thus, all the operations as well as the contents of the other registers can be performed with the address. Clock pulses to the address register R3a to switch the output to the bus R are allowed to embed R3 - »Rbus code R and rewrite from accumulatorTI to address register R3 occurs in the status Tbus - »R3 of the T microinstruction code.

Condition register Q operates analogously to registers R1, R2, R3, but its parallel outputs for signals Q (0) to Q (15) are tested based on the condition code in the microinstruction. Every-

Claims (1)

21 of the condition register bit Q belongs to the corresponding condition code condition 0, 1, 2. . . . . 15.  The macro code instruction is recorded in the condition register Q, which is read from the main memory into the T1a accumulator in the same microprocessor cycle transferred to the Q condition register.  By testing the contents of the Q condition register, an effective microprogram branching is performed according to the macroinstruction code.  iThe macroinstrument counter P records the address' of the program entry point, either from the main memory via the TI accumulator or from any register via the arithmetic and logical unit, which can modify the previous state selected, then the result is returned to the macro macro instruction counter TI.  Similar to me, as with the above-described registers, the macroinstrument counter P is controlled by the T and R codes of the R Rbus, Tbus - »P, Tbus -» PR3.  The constant register K serves to input ROM control memory constants into the pro-register registers. The bits 0-21 of the microinstruction, see format F2, are in parallel copied to the register of constants K relative to bit 22, see time control signal ROM (22). using signals TIC, TE, TD, TOSC.  The constant from the register korisfaM ^ K is transmitted on the bus S, see signals 5BBs (0) to SBUS (3), so it is possible to operate between registers of constants K and any registers R1, R2, R3, P, Q, ΤΪ, which are switched on the bus R .  The register K is used as a stack register of the accumulator T1, because simultaneously with the output of the constant from the register of the constant constant K, the constant K gets the content from the accumulator TI using the serioparal input where the PfeDMĚT is connected. the first four-input product gate (SSHC1) simultaneously forms the first input (01) of the wiring, while the first input is connected to the third input of the second to the sixteenth four-input sum product (SSHC2 to SSHC16) and simultaneously forms the second wiring (02) of the second input of the second quadruple At the same time, the second input of the third four-input sum of the product gate (SSHC3) forms the fourth input (04) of the connection at the same time, the second input of the fourth input signal of the product coefficient.  (SSMC4) simultaneously forms the fifth wiring input (05), the clock inputs (1) of the first to fourth five-bit sliding registers (PR1 to PR4) are connected to form the sixth input (06) of the wiring, the second input of the fifth four input wedge gate ( SSHC5) at the same time form the seventh input (07) of the connection, the second input of the sixth four-input additive gate (SSHC6) forms simultaneously the eight-input (08) of the canopy, the second input of the seventh four-input sum product (SSHC7) 209222 with the signals T1 (0) to TI (3) from TI battery.  The TI battery output is switched to either the R bus using the microinstruction, see status - Rbus code R, or S bus, see status -> Sbus code S.  The TI accumulator moves the result of the operation from the arithmetic and logical unit using the ALJ (0) to ALJ (3) signals or read from the main memory using the DAT (0) to DAT (15) parallel inputs or the T2 data-register with signals T2 (0) to T2 (15).  The contents of the TT accumulator are transferred in parallel to one of the registers R1, R2, R3, Q, P, E by the T microinstruction code or to the data register T2 by the bitTi-T2 microinstruction.  Parallel transmission takes place T3, T4B.  The T2 data register also has more functions.  First, it works as a shift register that allows one to four bits of information per cycle of the microprocessor to be moved.  In this case, either the "1" or the transmission bitE0 or the lowest bit T2 (0) is the highest bit, t © is the rotation of the data-register T2 or the previous state of the highestbit is repeated, that is the arithmetic shift to the right.  One of the options is determined by the S and X code of the microinstruction. Second, it works as a temporary memory for the TI batteries, thirdly as the main memory input register. The data transferred from the memory to the T accumulator can be transferred to the T2 data register in the same cycle, moved or rotated therein, and returned to the buffer memory or T1 in the following cycle.  Transmission register E acts as a binary or non-decadic transmission memory or as a counter for decadicating execution cycles.  The invention simultaneously comprises the ninth input (09) of the wiring, the second input of the eighth four-input summing gate (SSHC8) simultaneously forms the tenth input (010) of the wiring, the second input of the ninth four-input summing gate (SSHC9) forms the 11th wiring input (011) at the same time, the second exit of the tenth four-input summing gate (SSHC10) is simultaneously a twelve-out connection (012), the second input of the eleventh four-input sum gate (SSHC11) forms the thirteenth input (013), the fourteenth input (014) of the wiring, the second input of the thirteenth four-input sum coefficient (SSHC13) simultaneously forms the fifteenth input (015) of the wiring, the second input of the fourteenth four-input wedge gate (SSHC14) simultaneously forms the sixteenth input (016) ) wiring, second output of the fifteenth four-input sum gate (SSHC15) simultaneously constitutes the seventh input (017) of the wiring, the second input of the sixteenth four input wedge gate (SSHC16) simultaneously forms the eighteenth input (018) 209222 22 wiring, the first input of the first two input circuit ( NSD1) The type of negation of the logical coincidence is simultaneously the nineteenth input (019) of the wiring, while its output is connected to the output of the second input circuit (NSD2) of the logical product negation, and simultaneously forms the first output (001) of the wiring, the second input of the first two-input circuit ( NSD1) of the logical product negation type and the first input of the second two-input circuit (NSD2) of the logical product negation are connected and form simultaneously the twentieth input (020) of the wiring, the first input of the first three-input circuit (NST1) of the logical product negation is connected to the first set entry (2) of the 24th 5th the current shift register (PR26) and form the current fourth input (021) of the circuit, while the second input is simultaneously the twenty-second input (022) of the circuit, the third input of the first three-input circuit (NST1) of the logical product negation is connected to the third inputs of the fourth to sixth three-input circuit (NST4 to NST6), then to the second output of the twenty-two-input circuit (NSD20) of the logic product negation and form the twenty-third input (023) of the wiring, the output of the first three-input circuit (NST1) of the negogenic product is connected to the input of the nineteenth inverter (INV19), the output of which is connected to the second input of the second two-input circuit (NSD2) of the logical product negation and the basic input (11) of the first flip-flop (ACT) of type D, the clock input (12) of the first flip-flop (AČT) of type D forms the current 24th input (024) wiring while its unicast output (101) is connected to the first inputs of the first to sixteenth four input input gate (SSHC1 to SSHC16) and simultaneously form the second output (002) of the connection, the output of the first four input product gate (SSHC1) is connected to the input of the first inverter (INV1) whose output is connected to the fourth input input (6) the first five-bit shift register (PR1), the output of the second four-input sum gate (SSHC2) is connected to the input of the second inverter (INV2), the output of which is connected to the third set input (4) of the first five bit shift register (PR1), the output of the third four-input additive gate (SSHC3) is connected to the third input inverter (INV3), the output of which is connected to the second setting input (3) of the first five-bit shift register (SS1), the output of the fourth four-input sum gate (SSHC4) is connected to the fourth input inverter (INV4), its When the output is connected to the first setting input (2) of the first five-bit shift register (PR1), the fifth setting input (7) of the first bit shift register (PR1) is connected to zero potential, while its fifth data output (10) is simultaneously the 60th output (0064). ) wiring, the fourth data output (11) of the first five-bit shift register (PR1) is connected to the first inputs of the first and second two-input circuit (NSDK1, NSDK2) of the open-collector logic product negation, to the quarter-set inputs (6) of the eighth, twelfth , the sixth, twentieth and twenty-fourth five-shift shift registers (PR8, PR12, PR16, PR20, PR24), and the fifth adjustment input (7) of the thirty-first five-bit shift register> (PR31), for serial data input (9) of the 28th bit shift register (PR28) and the second input of twenty-two two-input (NSD25) negac the logical product, the third data output (13) of the first 5-bit shift register (PR1) is connected to the third setting inputs (4) of the eighth, twelfth, sixteenth, twenty and twenty-fourth five-shift shift registers (PR8, PR16, PR22, PR24) and to the first setting input (2) of the thirty-first five-bit shift register (PR31), the second data output (14) of the first five-bit shift register (PR1) is connected to the second setting inputs (3) of the eighth, twelfth; the sixteenth, twentieth, twenty-fourth, and thirty-five shift registers (PR8, PR12, PR16, PR20, PR24, PR30), the first data output (15) of the first five-bit shift register (PR1) is connected to the first setting inputs (2) of the eighth, twelfth , a sixteenth, twentieth, two-fourth, fourth, five-bit shift register (PR8, PR12, PR16, PR20, PR24) and a third set input (4) of the 28th 5-bit shift register (PR29), zeroing inputs (16) of the first to fourth five-bit sliding registers ( PR1 to PR4) are connected to form the ninety-seventh input (097) of the wiring, the release inputs of setting (8) of the first and second bits shift registers (PR1 and PR2) are connected to the seventeenth inverter output (INV17), setting inputs (8 ) of the third and fourth five-bit shift registers (PR3, PR4) are output to the eighteenth inverter (INV18) whose the input is connected to the input of the seventeenth inverter (INV17) and forms at the same time the 9th input (059) of the connection, the serial input (9) of the first five-bit shift register simultaneously forms the 80th input (080) of the connection, the output of the fifth four-input concurrent gate ( SSHC5) is connected to the input inverter (INV5), the output of which is connected to the fourth setting input (6) of the second five-bit shift register (PR2), whose serial input (9) is simultaneously the seventy-fifth input (076) wiring, output of the sixth four-input coefficient the gate (SSHC6) is connected to the input sixth inverter (INV6) whose output is connected to the third setting input (4) of the second 5-bit sliding register (PR2), the output of the seventh four-input sum gate (SSHC7) is connected to the input of the seventh inverter (INV7) , the output of which is connected to the second setpoint (3) of the second set o a five-bit shift register (PR2), the output of the eighth four-input cumulative gate (SSHC8) is connected to the input 23 of the eighth inverter (INV8), the output of which is connected to the first setting input (2) of the second five-bit register (PR2), the fifth setting input ( 7) of the second 5-bit shift register (PR2) is connected to the zero potential, while its fifth output (10) is simultaneously connected to the sixty-second connection, the fourth data output (11) of the second five-bit shift register (PR2) is connected to the first inputs of the third and fourth two -input circuit (NSDK3, NSDK4) of the open-collector non logic product type, remote fourth set-up inputs (6) of the seventh, eleventh, fifteenth, nineteenth, twenty-third and thirty-first five-bit sliding registers (PR7, PRII, PR15, PR19) , PR23, PR31), then to the second input of the twenty-fourth two-input circuit (NSD24) ) of the logic-type negation and the serial input of the data (9) of the 25th 5-bit shift register (PR27), the third data output (13) of the second five-bit shift register (PR2) is connected to the third setting inputs (4) of the seventh, eleventh, fifteenth, nineteenth, the 25th 5-bit shift register (PR7, PRII, PR15, PR19, PR23), further to the fifth adjustment input (7) of the thirty-five shift register (PR30), the second data output (14) of the second five-bit shift register (PR2) is connected to the second setup inputs (3) of the seventh, eleventh, fifteenth, nineteenth, twenty-five, five-bit shift registers (PR7, PRII, PR15, PR19, PR23) and the first setting input (2) of the thirty-five shift register (PR30), first data output (15 ) of the second five-bit sliding register (PR15) is connected to the first setting inputs (2) of the seventh, eleventh, fifteenth, the nineteenth, twenty-five five-bit shift register (PR7, PRII, PR15, PR19, PR23) and the second set input (3) of the 28th 5-bit shift register (PR29), the output of the ninth four-input product gate (SSHC9) is connected the ninth inverter input (INV9), the output of which is connected to the fourth setting input (6) of the third-bit shift register (PR3), the output of the fourth four-input addition block (SSHC10) is connected to the tenth inverter input (INV10) whose output is connected to the third set input (4) the third five-bit sliding register (PR3), the output of the eleventh four-input sum gate (SSHC11) is connected to the input of the eleventh inverter (INV11), the output of which is connected to the second output input (3) of the third five-bit shift register (PR3), the output of the twelfth quadruple -potal sum product castle 1a (SSHC12) is connected to the input of the twelfth inverter (INV12), the output of which is connected to the first setting input (2) of the third 5-bit shift register (PR3), the fifth setting input (7) of the third five-bit shift register (PR3) is connected to zero potential, whereas its fifth data output (10) 209222 forms simultaneously the sixty-sixth output (0066) of the connection, the fourth data output (11) of the third five-bit sliding register (PR3) is connected to the first inputs of the fifth and sixth two-input circuits (NSDK5, NSDK6) of the negation of the logical product collector, to the fourth set-up inputs (6) of the sixth, tenth, fourteenth, eighteenth, twenty-second five-bit sliding registers (PR6, PR10, PR14, PR18, PR22), the serial data input (9) of the 26th 5-bit shift register (PR26), to the third setting input (4) of the thirty-first five-bit shift register (PR31) and to the second input of the twenty-second two-input circuit (NSD23) of the logical product type, the third data output (13) of the third five-bit shift register (PR3) is connected to the third set-up inputs (4) of the sixth, tenth, fourteenth, eighteenth, twenty-five five-bit shift register (PR6, PR10, PR14, PR18, PR22), then the fourth input input (6) of the thirty-five-shift sliding register (PR30), the second data output (14) of the third-bit shift register (PR3) is connected to the second adjusting inputs (3 ) the sixth, tenth, fourteenth, eighteenth, twenty-second five-bit shift registers (PR6, PR10, PR14, PR18, PR22) and the fifth adjustment input (7) of the 28th 5-bit shift register (PR29), the first data output (15) the third three-bit shift register (PR3) is connected the first setting inputs (2) of the sixth, tenth, fourteenth, eighteenth, dvac the first and second thirty-five shift registers (PR6, PR10, PR14, PR18, PR22, and PR29), the serial data input (9) of the third five-bit sliding register (PR3) is simultaneously a seventy-first wiring (079) wiring, output of the thirteenth quadruple sum product gate ( SSHC13) is connected to the input of the thirteenth inverter (INV13) whose output is connected to the fourth setting input (6) of the fourth five-bit shift register (PR4), the output of the fourteenth four-input additive gate (SSHC14) is connected to the fourteenth inverter (INV14) whose output is connected to the third set-up input (4) of the four-bit shift register (PR4), the output of the fifteenth four-input sum block (SSHC15), is connected to the fifteenth-inverter input (INV15), the output of which is connected to the second set input (3) of the fourth five-bit shift register (PR4), output six the four-input sum product gate (SSHC16) is connected to the input of the sixteenth inverter (INV16) whose output is connected to the rta first set input (2) of the fourth 5-bit shift register (PR4), the fifth set input (7) of the fourth five bit shift register ( PR4) is connected to the zero potential, while its serial data input (9) is simultaneously the 28th input (029) of the connection, the fifth data output (10) of the four-bit shift register (PR4) is the sixty-sixth output (0067) of the circuit, 24 209222 the fourth data the output (11) of the fourth five-bit sliding register (PR4) is connected to the first inputs of the open-collector negation of the seventh and eighth two-input circuit (NSDK7, NSDK8), the fourth set-up inputs (6) of the fifth, ninth, thirteenth, seventeenth, twenty-first five-bit post-shift register (PR5, PR9, PR13, PR17, PR21) , further to the second setting input (3) of the thirty-first five-bit shift register (PR31), the serial input of data (9) of the 25th 5-bit shift register (PR25) and the second input of the second two-input circuit (NSD22) of the logic product negation, third output (3) the fourth five-bit sliding register (PR4) is connected to the third setup input (4) of the fifth, ninth, thirteenth, seventeenth, twenty-first and thirty five-shift sliding registers; (PR5, PR9, PR13, PR17, PR21, PR30), the second chisel output (14) of the fourth-bit shift register (PR4) is connected to the second setting inputs (3) of the fifth, ninth, thirteenth, seventeenth, twenty-first five-bit shift registers ( PR5, PR9, PR13, PR17, PR21), further to the fourth setting input (6) of the 28th 5-bit shift register (PR29), the first data output (15) of the fourth 5-bit shift register (PR4) is connected to the first setting inputs (2 ) of the fifth, ninth, thirteenth, seventeenth, twenty-first five-bit shift register (PR5, PR9, PR13, PR17, PR21) and the second input of the third two-input circuit (NSD3) of the negation of the second, third, third , the fifth and seventh two-input circuit (NSDK1, NSDK3, NSDK5, NSDK7) of the logical product negation are connected and form simultaneously the twenty-fifth input (025) of the connection, the output of the first two inputs of the circuit (NSDK1) of the negation of the logical product by the open collector is connected via a second resistor (R2) to the positive pole of the power source, and to the outputs of the twelfth, sixteenth, twenty, twenty-fourth, twenty-eighth and thirty-eighth two-input circuit (NSDK12, NSDK16) , NSDK20, NSDK24, 'NSDK28, NSDK39) type of negation of a logical product with an open collector and form simultaneously a third output (003) connection, the output of the second double-input circuit (NSDK2) of the negation of the logicfunction with an open collector is connected to the first one the resistance (R1) to the positive pole of the electric energy source, and to the output of the thirty-hour two-input circuit (NSDK32), the logic product unification with the open collector forms the fourth output (004) of the connection, the output of the third two-input circuit (NSDK3) of the logic product negation with the open stamp -tor is connected via the fourth resistor (R 4) the loading pole of the power supply, and the elevation of the eleventh, fifteenth, nineteenth, twenty-third, twenty-seventh and thirty-eighth, two-input circuits (NSDK11, NSDK15, NSDK19, NSDK27, NSDK38) of the logic product negation with the open collector the seventh output (007) of the wiring, the output of the fourth two-input circuit (NSDK4) of the negation of the logic product by the open collector is connected by the output of the thirty-first two-input circuit (NSDK31) of the negation of the logic product with the open collector, and by the third resistor (R3) of the loading pole of the electrical source energy, and simultaneously forms the eighth output (008) of the wiring, the output of the fifth input circuit (NSDK5) of the type of the non-glacial product with the open collector is connected via the sixth resistor (R6) to the positive pole of the power source, and on the other side to the eighty, fourteenth, eighteenth, twenty-second , two the sixth and thirty-fifthhours of the input circuit (NSDK10 !, NSDK14, NSDK18, NSDK22, NSDK26, NSDK37) type of logic product union with open collector form simultaneously the ninth output (009) of the connection, the output of the sixth two-input circuit (NSDK6). the type of logic product with the open collector is connected via the fifth resistor (R5) of the load pole of the power supply, and the two-input two-input circuit (NSDK30) of the non logic product with the open collector forms the tenth output (0010) of the wiring, the seventh output of the two-input circuit (NSDK7) of the negation of the logic product with the open collector is connected via the eighth resistor (R8) to the positive pole of the power source, and the output of the ninth, thirteenth, seventeenth, twenty-first, twenty-sixth and thirty-sixth two-input circuit (NSDK9) , NSDK13, NSDK17, NSDK21, NSDK25, NSDK36) of the negation of the logical product with the open collector and form the current thirteenth output (0013) of the connection, the output of the eighth input circuit (NSDK8) of the type of the non-glogical product with the open collector is connected via the seventh resistor (R7) to positive pole of electric power source, poison the output of the twenty-thirteenth two-input circuit (NSDK29) of the logic product negation with the open collector and simultaneously forms the fourteenth output (0014) of the wiring, the zeroing inputs (16) of the fifth, sixth, seventh and eighth five-bit shift registers (PR5, PR6, PR7 , PR8) are connected at the same time to form the 24th input (026) of the wiring, the clock inputs (1) of the fifth to eighth five-bit shift registers (PR5 to PR8) are connected to form the 27th input (027) of the connection, release inputs of the setting (8 ) of the fifth and sixth five-bit shift registers (PR5, PR6) are connected to the output of the twenty-first inverter (INV21), the release inputs of the setting (8) of the seventh and eighth five-bit shift registers (PR7, PR8) are output to the twentieth -the second inverter (INV22) whose input is connected to the input of the twenty-first inverter (INV21) and simultaneously forms the 28th input (028) connected , the first data output (15) of the fifth five-bit shift register (PR5) forms the sixteenth output (0016) of the connection, the fourth data output (11) of the fifth five-bit shift register (PR5) is connected to the serial data input (9): the fifth five-bit the shift register (PR5) and the first input of the ninth two-input circuit (NSDK9) of the logic product negation with the open collector, the fourth data output (11) of the six-bit shift register (PR6) is connected to the serial data input (9) of the sixth five-bit shift register (PR6) ) and to the first input of the tenth two-input circuit (NSDK10) of the open-collector non logic product type, the fourth data input (11) of the seventh five-bit shift register (PR7) is connected to the serial data input (9) of the seventh five-bit sliding register (PR7) and to the first input of the eleventhhour input circuit (NSDK11) of the non-gelling product with the open collector, the quarter-day output (11) of the eight-bit shift register (PR8) is connected to the serial input of data (9) of the eighth five-bit shift register (PR8) and to the first input of the twelfth two-input circuit (NSDK12) of the open-collector negation type at the same time, the fifteenth output (0015) of the connection, the second input of the ninth to twelfth two-input flip-flop (NSDK9 to NSDK12) of the type of non-aggregate product with the open collector is connected and forms simultaneously the thirtieth input (030) of connection, release inputs of setting (8) of the ninth tenth five-bit sliding registers (PR9, PR10) are connected to the twenty-third inverter output (INV23), the setting inputs (8) of the eleventh and twelfth five-bit shift registers (PRII, PR12) are connected to the 24th inverter inverter (INV24), where the input is connected to the twenty-third inverter input (INV23) and is formed by the early thirty-third wiring input (033), the zeroing inputs (16) of the ninth to twelfth five-bit shift register (PR9 to PR12) are connected to form the thirty-first wiring input (031), the clock inputs (1) of the ninth to twelfth five-bit shift registers ( PR9 to PR12) are connected and simultaneously form the thirty-second wiring input (032), the first data output (15) of the ninth five-bit shift register (PR9) simultaneously constitutes the seventeenth wiring input, the fourth data output (11) of the ninth five-bit shift register ( PR9) is connected to the serial data input (9) of the 9-bit shift register (PR9) and to the first input of the thirteenth two-input circuit (NSDK13) of the open-collector logic product, the fourth data output (11) of the 10-bit shift register (PR10) is connected to serial data input (9) of the 10-bit shift register (PR10) and n and the first input of the fourteenth two-input circuit (NSDK14) of the open-collector logic product negation, the fourth data output (11) 25 209222 of the eleventh five-bit shift register (PRII) is connected to the serial data input (9) of the eleventh five-bit shift register (PR11) and to the first input of the fifteenth two-input circuit (NSDK15) of the open collector negation type, the fourth data output (11) of the twelfth five-bit shift register (PR12) is connected to the serial data input (9) of the twelfth five-bit shift register (PR12) and to the first input of the sixteenth the two-input circuit (NSDK16) of the type of negation of the open-collector logic, the second input of the fifth to sixteenth of the two-input circuit (NSDK13 to NSDK16) of the negation of the logicfunction with the open collector is connected and forms simultaneously the thirty-eighth input (038) of the wiring, the release inputs of setting (8) the thirteenth čtr-n The five-bit shift register (PR13, PR14) is connected to the output of the twenty-fifth inverter (INV25), the setting inputs (8) of the fifteenth and sixteenth five-bit shift registers (PR15, PR16) are connected to the 26th inverter inverter (INV26) whose input is connected to the input of the twenty-fifth inverter (INV25) and simultaneously form the thirty-thirteenth input (036) of the wiring, the reset inputs (16) of the thirteenth to the sixteenth five-bit shift register (PR13 to PR16) are connected to form the thirty-third input (034) of the wiring, the clock inputs (1) of the thirteenth to sixteenth five-bit shift register (PR13 to PR16) are connected and form simultaneously the thirty-fifth circuit input (035), the first data output (15) of the thirteenth five-bit shift register (PR13) is simultaneously the eighteenth circuit (0018), whereas its second data output ( 14) are currently nineteen the connection output, the third data output (13) of the thirteenth five-bit shift register (PR13) simultaneously constitutes the twentieth output, while the fourth data output (11) is connected to the serial data input (9) of the thirteenth five-bit shift the register (PR13) and the first input of the seventh thirteenth input circuit (NSDK17) of the logic product type with the open collector form simultaneously the twenty-first output connection, the first data output (15) of the fourteenth five-shift shift register (PR14) forms the current one-second the wiring output (0022), while the second data output (14) simultaneously forms the twenty-third wiring output (0023), while the third data output (13) of the thirteenth five-bit shift register (PR13) forms the twenty-fourth output (0024), while the fourth data output (11) is connected to the serial data input (9) of the fourteen bit shift The first data output (15) of the fifteenth five-bit shift register (PR15) forms simultaneously the twenty-fifth output (PR15) of the eighteenth two-input circuit (NSDK18) of the logic product negation with open collector. While the second data output (14) 209222 26 forms the 27th output connection at the same time, the third data output (13) of the fifteenth five-shift shift register (PR15) forms the current eighth output (0028) of the circuit, whereas the fourth the data output (11) is connected to the serial data input (9) of the fifteenth five-bit sliding register (PR15) and to the first input of the nineteenth input circuit (NSDK19) of the open-collector negation of the logic product and forms the twenty-second output (0029) of the first data output (15) the sixteenth five-bit shift register (P R16) simultaneously forms the thirty-first wiring output, while its second data output (14) simultaneously forms the thirty-first wiring output, the third data output (13) of the sixth five-bit shift register (PR16) forms the thirty-second wiring output (0032), whereas its fourth data output (11) is connected to a serial data input (9) of a sixteenth five bit sliding register (PR16) and to a first input of a twenty two input circuit (NSDK20) of a logic product negation with an open collector and simultaneously forms the thirty third output (0033) wiring, the second the inputs of the seventeenth to twenty-second input circuit (NSDK17 to NSDK20) of the logical product negation with the open co-connector are connected and form simultaneously the 37th input (037) of the connection, the release inputs set (8) of the seventeenth to eighteenth five-bit shift register (PR17, PR18) ) are attached; the output of the twenty-sixth inverter (INV26), the release inputs of the nineteenth and the twenty-second five-bit shift registers (PR19, PR20) are connected to the output of the twenty-seventh inverter (INV27), the input of which is connected to the twenty-sixth inverter (INV26) and is the forty-first input ( 041) wiring, null-input inputs (16) of the seventeenth to twenty-bit shift register (PR17 to PR20) are connected to form the thirty-nine input (039) of the wiring, the clock inputs (1) of the seventeenth to the twenty five-bit shift register (PR17 to PR20) are the first data output (15) of the seventeenth five-bit shift register (PR17) simultaneously forms the fifth output (005) of the circuit, while its second data output (14) simultaneously forms the sixth output (006) of the circuit , a third output (13) of the seventeenth five-bit post the register (PR17) simultaneously forms the 11th output (0011) circuit, whereas its fourth data output (11) is connected to the serial data input (9) of the seventeenth five-bit shift register (PR17) and the first input of the twenty-first two-stage circuit (NŠDK21) of negation the open-collector logic product and form the twelfth wiring output at the same time, the first data output (15) of the eighteenth five-bit shift register (PR18) simultaneously forms the thirty-fourth wiring output (0034), while its second data output (14) forms simultaneously the third data output (13) of the eighteenth five-bit shift register (PR18) is simultaneously the thirty-thirty output circuit, while its fourth data output (11) is connected to the serial data input (9) of the eighteen-bit shift register (PR18) and the first entry of the twenty-second two-entry circuit (NSDK22) the pu negation of the logic product with the open collector and at the same time form the 37th connection circuit, the first data output (15) of the nineteenth five-bit shift register (PR19) simultaneously forms the thirty-eighth output (0038) of the circuit, whereas its second data output (14) forms at the same time the thirty-ninth output of the connection, the third data output (13) of the nineteenth five-shift shift register (PR19) forms the simultaneously forty-four output (0040) of the circuit, whereas its fourth data output (11) is connected to the serial input of the data (9) of the nineteen five-bit sliding The first data output (15) of the twenty-bit shift register (PR20) forms the first register (PR19) and the first input of the twenty-second two-input circuit (NSDK23) of the logical product type with open collector. - early 40th output (0042) wiring, where its second data output (14) simultaneously forms the fourth output (0043) of the circuit, the third data output (13) of the twenty five-bit shift register (PR20) simultaneously forms the fourth circuit output (0044), whereas its fourth data output (11) is connected to the serial the data input (9) of the twenty-five-shift shift register (PR20) and the first input of the twenty-fourth two-input circuit (NSDK24) of the open-collector logic product negation, and simultaneously form the 40th output (0045) of the second input of the twenty-second to twenty-fourth two-input the circuit (NSDK21 to NSDK24) of the logic product negation with the open collector are connected and form at the 44th input (042) of the connection, the release inputs of the setting (8) of the twenty-first and the 5th five-bit shift registers (PR21, PR22) are connected to the output of the twenty-eighth inverter (INV28), the release inputs (8) of the 24th and 24th 5-bit shift registers (PR23, PR24) are connected to the output of the twenty-third inverter (INV29), the input of which is connected to the twenty-eighth inverter (INV28) and forms the forty-fifth input (045) wiring, zeroing inputs (16) of the twenty-first to twenty-fourth five-bit shift registers (PR21 to PR24) are connected to form the fourth input (043) of the wiring, the clock inputs (1) of the twenty-first to twenty-fourth five-bit shift register (PR21 to PR24) ), the fourth data output (11) of the twenty-first five-bit shift register (PR21) is connected to the serial input of data (9) of the twenty-first five-bit shift register (PR21) and to the first 27th input of the 25th shift register (PR21) two-input circuit (NSDK25) negac of the logical product with the open collector, the fourth data output (11) of the 24th 5-bit shift register (PR22) is connected to the serial input of data (9) of the 5th 5-bit shift register (PR22) and the first input of the twenty-sixth of the input circuit (NSDK26) open-collector logic product negation, the quarter-quarter output (11) of the 24-bit 5-bit | shift register (PR23) is connected to serial data input (9) of the 25th 5-bit shift register (PR23) and the first entry of the twenty-seventh two-input circuit (NSDK27) of the type of logic product with open collector, the fourth data output (11) of the twenty-fourth five-bit shift register (PR24) is connected to serial data input (9) and logic product unification is the first input of the twenty-two two-input circuit (NSDK28) open collector, second inputs twentieth the fifth to twenty-eighth two-input circuit (SSDK25 to NSDK28) of the logic product negation with the open-collector are connected and form simultaneously, the forty-sixth input (046) of the canopy, the release inputs of the setting (8) of the 24th and 26th six-bit shift registers (PR25) , PRPR26) are connected to the thirty-inverter output (1NV30), the setting inputs (8) of the twenty-fifth and twenty-eighth five-bit shift registers (PR27, PR28) are connected to the output of the thirty-first inverter (INV31), whose input is also connected with the input of the thirty inverter (INV30) and connected to the output of the second trivial input circuit (NST2) of the negation of the logical product, the first input of which is simultaneously the forty-eighth circuit (048) of the circuit and whose second input is simultaneously the forty-eighth input (049) of the circuit, the third input the second and the first input of the third three-input circuit (NS) T2, NST3) The type of negation of the logic is connected and forms the fiftieth input (050) of the connection, the second input of the third three-input circuit (NST3) of the negation of the logic is the fifty-first input (051) of the connection, while its third input is simultaneously the fifty-second input ( 052) wiring, the output of the third I / O circuit (NST3) of the logic product negation is connected to the zeroing inputs (16) of the 24th to 28th 5-bit shift register (PR25 to PR28), hourly input (1) of the 24th to 28th shift register (PR25 to PR28) are connected and simultaneously form the forty-seventh input (047) of the wiring, the first setting input (2) of the twenty-five five-bit shift register (PR25) simultaneously forms the fifth wiring input (054), while its second setting input (3) is connected to the second input of the sixth three-input of the logic product negation (NST6) to the first input of the twenty-first two-input circuit (NSD21) of the logical product negation type, and simultaneously forms the fifty-fifth input (055) 209222 of the wiring, the third set input (4) of the 25th five-bit shift register (PR25) ) forming the fifty-fifth input (056) of the circuit, while its fourth set-up input (6) is the currently fifty-seventh input (057) of the wiring, and its fourth data output (11) is connected to the first input of the twenty-second two-input circuit (NSDK29) of the open collector negation, second setting input j (3) of the 24th 5-bit sliding rewinder (PR26) is connected to the first input of the fourth-quarter input circuit (NST4) of the logic product negation, then to the second input of the twenty-first two-input circuit (NSD21) of the non-germinal product type and forms simultaneously the sixtieth input (060) for bonding, while its third setting input! (4) simultaneously form the 60th input input (061) and its fourth input input (6) simultaneously forms the sixty-second input (062) of the circuit, its fourth data output (11) being connected to the first input of the 30th input circuit (NSDK30) Open Collector Negative Logic Product Negation, First Setting Input (?); Twenty-Seventh Five-Bit Sliding Register (PR27) is simultaneously a 60th input (063) wiring while its second setting input (3) forms at the same time, the 60th input (064) of the wiring and its third input (4) form the sixty-fifth input (065) of the wiring, the fourth set-up input (6) of the twenty-five five-bit shift register (PR27) is simultaneously the sixty-sixth input (066) of the wiring, while its fourth The data output (11) is connected to the first input, the thirty-first two-input circuit (NSDK31) of type n the logic product with the open collector, the first setting input (2) of the 28th 5-bit sliding register (PR28) forms simultaneously the 67th input ΐ (067) of the wiring, while its second setpoint (3) is simultaneously the 60th input (068) the wiring, and its third adjustment input (4) form the sixty-sixth input (069) of the wiring, the fourth setting input (6) of the twenty-bit shift register (PR28) forms the seventieth input (070) of the wiring, while its fourth data output (11) is connected to the first input of the thirty-second two-input circuit, (NSDK32) of the logical product negation with the open collector, the second input of the fourth three-input circuit (NST4) of the logical product negation is connected to the first input of the fifth three-input circuit (NST5) of the logical negation type součinu and is also the seventy-seventh entry (077) (engagement, kd however, its output is connected to an input thirty-third inverter (INV35) whose output is connected to the second input of the thirty-third two-circuit circuit (NSDK33) of the open-collector logic product and to the open-collector first to fourth inverter (INVK1 to INVK4) , the output of the first inverter (INVK1) with the open collector is connected to the output of the twenty-second two-input obvo- 209222 I du (NSDK29) of the negation of the logic product Is with the open collector, the output of the second inverter (INVK2) with the open collector is connected to the output of the thirty-two to the circuit (NSDK30) ) type of negation of logic product with open collector, output of third inverter (INVK3) with open collector is connected to output of thirty-first two-input circuit (NSDK31) of negation of logic product with open collector, output of fourth inverter (INVK4) with open collector is connected up tup of the thirty-second two-input circuit (NSDK32) of the negation of the logic product with the open collector, the second input of the fifth three-input circuit (NST5) of the negation of the logical product is connected to the first input of the sixth three-input circuit (NST6) of the negation of the logic product and forms the seventy-seventh the input (078) of the wiring, while its output is connected to the input of the thirty-sixth inverter (INV36), the output of which is connected to the second input of the thirty-fourthhour input circuit (NSDK34) of the non-glogic product with the open collector, the output of the sixth three-input circuit (NST6) of the negation of the logical product is connected to input of the thirty-seventh inverter (INV37) whose output is connected to the input of the fifth inverter (INVK5) with the open collector and the second inputs of the second, fourth, sixth and eighth two-input circuit (NSDK2, NSDK4, NSDK6, NSDK8) type of logical product with open ko by the lecturer, the output of the twenty-first two-input circuit (NSD21) of the logic product negation is connected to the first input of the twenty-two-input circuit (NSD20) of the logic product negation whose output is connected to the first input of the thirty-fifth two-input circuit (NSDK35) collectors on the second inputs of the twenty-thirty-thirty-second two-input circuit (NSDK29 to NSDK32) of the negation of the logic product with the open collector, outputs of the thirty-third to thirty-two two-input circuit (NSDK33 to NSDK35) of the logic product negation with the open collector and the output of the fifth inverter (INVK5) with open collector are connected both through the twenty-fifth resistor (R25) to the positive pole of the power supply and the basic input (21) of the second flip-flop (AT2 (15)) of the type D whose zero output (202) is connected to the first entry of the thirtieth the third double-input circuit (NSDK33) of the open-collector logic type, to the serial input, the data (9) of the 28th 5-bit shift register (PR29), the fourth input of the 16-input sum-gate (SSHC16), and the first input of the two-input circuit (NSD4) of the logic product negation, the clock input (22) of the second flip-flop (AT2 (15)) of type D is connected to the clock inputs (1) of the twenty-thirty-first five-shift shift register (PR29 to PR31) and forms at the same time, the 50th input (053) of the wiring, the zeroing inputs (16) of the 28th to the 30th-first 5-bit shift register (PR29 to PRPR31) are connected and connected to the adjusting input (24) of the second flip-flop (AT2 (1S)) itypu D and they simultaneously form the 50th input (058) of the wiring, the inputs of the thirty- and thirty-third inverter (INV32 and INV33) are connected ya forms at the same time the seventy-first input (071) of the wiring, the output of the thirty-second inverter (INV32) is connected to the first input of the third two-input circuit (NSD3) of the logical product negation whose output is connected to the reset input (23) of the second flip-flop (AT2) 15)) of type D, on the release input setting (8) of the 28th 5-bit shift register j (PR29), the thirty-third inverter output (INV33) i is connected to the release inputs (8) of the thirtieth and the thirty-first five-bit shift registers ( PR30 and PR31), the first data output (15) of the 28th 5-bit shift register (PR29) is connected to the fourth input of the twelfth four-input sum gate (SSHC12) and the first input of the fifth two-input circuit (NSD5) of the logical product negation , the output of which simultaneously comprises the forty-fifth output (0049) of the wiring, the output of the quarter on the two-input circuit (NSD4) of the negation of the logic product voří, simultaneously generates the forty-eighth output (0048) of the connection, the second data output (14) of the 28th bits register (PR29) is connected to the quarter input of the eighth input four-input gate (SSHC8) and the first input of the sixth input the circuit (NSD6) of the negation of the logic product, the output of which simultaneously constitutes the pad-output output (0050) of the circuit, the third data output i (13) of the 28th 5-bit shift register (PR29) is connected to the fourth input of the fourth sum gate (SSHC4) ) and the first input of the seventh two-input circuit (NSD7) of the logical product negation, the output of which simultaneously constitutes the fifty-first wiring output (4), the fourth data output (11) of the twenty-five five-bit shift register (PR29) is connected to the fourth input of the fifteenth four-input-wo sum product gate ( SSHC15) and the eighth input of the eighth input circuit (NSD8) of the logical product negation, the output of which simultaneously forms the fifty-second circuit output, the fifth data output (10) of the twenty-fifth five-bit shift register (PR29) is connected to the fourth input of the eleventh four-input sum product gate (SSHC11), to serial data input (9) of the thirty-five, bit shift register (PR30) and to the first input of the ninth two-input circuit (NSD9) of the logical product negation, the output of which simultaneously represents the fifty-third output (0053) of the circuit, the first data output ( 15) The thirtieth five-bit sliding register (PR30) is connected to the fourth quarter of the seventh four-input summing gate (SSHC7) and to the first input of the tenth! 29 i of a two-input circuit (NSD 10) of the negation of the logic product, the output of which is simultaneously the fifth-fourth output (0054) of the circuit, the second data output (14) of the thirty-five shift slider (PR30) is connected to the fourth input of the third four-input sum gate; (SSHC3) and the first input of the eleventh two-circuit circuit (NSD11) of the logical product negation, whose output simultaneously forms the fifth interface output (0055), the third data output (13) of the thirty-five shift register (PR30) is connected to the fourth the fourteenth four input input gate (SSHC14) input and the logical product negation of the twelfth two-input circuit (NSD12), the output of which is simultaneously the fifty-fifth output output, the fourth data output (11) of the thirty-five shift register (PR30) ) is the fourth input of the tenth four-input total input gate (SSHC10) and the first input of the thirteenth two-input circuit (NSD13) of the logic product negation type, whose output is the fifty-seventh output (0057) of the connection, the fifth output (10) of the thirty-five shift register. (PR30) is a pin it is connected to the fourth input of the sixth four-input sum coefficient (SSHC6), to the serial input of the data (9) of the thirty-first five-bit shift register (PR31); and the first input of the fourteenth two-input circuit (NSD 14) of the logical product negation, whose number (up to the fifty-fifth output) The connection, the first data output (15) of the thirty-first five-bit shift register (PR31) is connected to the fourth the second four input input gate (SSHC2) input and the logical product negation, the first input of the fifteenth two input circuit (NSD15), whose output is simultaneously the fifty-fifth output (0059), the second data output (14) of the thirty-hop five-bit shift register (PR31) is connected to the fourth input of the thirteenth four-input sum gate (SSHC13) and the first input of the sixteenth two-input circuit (NSD16) of the logic-type negation type whose output is simultaneously connected to the 60th connection, the third data output (13) of the thirty-first five-bit shift register (PR31) is connected n and the fourth input of the ninth-four-input total gate (SSHC9) and the first input of the seventeenth two-input circuit (NSD17) of the logic-type negation, the output of which simultaneously constitutes the sixty-first connection (0061), the fourth data output (11) of the thirty-first five-bit slider (PR31) is connected to the fourth entry of the fifth quadruple.  the sum product gate (SSHC $) and the first input of the eighteenth two-input circuit (NSD18) of the logical product negation, the output of which simultaneously forms the sixty-second connection output, the fifth data output (10) of the thirty-hop five-bit shift register (PR31) is connected to the second input of the thirty-fifth, 209222 j of the two-input circuit (NSDK35) of the type of the non-aggregate product with the open collector, to the fourth input of the first four-input sum-; ; the new gate (SSHC1) and the first input of the nineteenth two-input circuit (NSD19) is the logical product type-output whose output is simultaneously the sixty-third output (0063) of the wiring, a second resistor of the fourth two-input circuit (NSD4) of the logic product negation is connected ( Ø9) to the positive pole of the electric power source and simultaneously form the 80th first input: (081) wiring, the second input of the fifth twoInput circuit (NSD5) of the logic coefficient negation connected via the tenth resistor (R10) to the positive pole of the power supply the eight-second input (082) of the wiring, the second input of the sixth input circuit (NSD6) of the negation, the logic product is connected via the eleventh resistor (Rll) to the positive pole of the power supply and forms the 80th input (083) simultaneously The second input of the seventh two-input circuit (NSD7) of the logical product negation is only through the twelfth resistor (R12) to the positive electric power source and simultaneously forming the eight-fourth fourth input (084) of the wiring, the second input of the eighth input circuit (NSD8) of the non-homogeneous product is connected via the thirteenth resistor (R13) to the positive pole of the electrical source energiea forms at the same time 80th.  the input (085) of the input, the second input of the ninth two-input circuit (NSD9) of the logic product negation is connected via the fourteenth resistor (R14) to the positive electric power source and simultaneously forms the eighth-connected input (086), the second input the tenth -the two-input circuit (NSD10) of the non-homogeneous product is connected via the fifteenth resistor (R15) to the positive pole of the power source and simultaneously forms the 79th input (087) of the wiring, the second input of the eleventh two-input circuit (NSD11) of the negation of the logical product the load pole of the power supply is connected via the sixteenth resistor (R16) and simultaneously forms the 80th input (088) of the wiring, the second output of the twelfth two-input circuit i (NSD12) of the logic product negation is connected via the seventeenth resistor (R17) to the positive pole 'power sources and simultaneously form the eighth-sarcodal input (089) of the wiring, the second for the thirteenth The two-input circuit (NSD13) of the logic product unification is connected via an eighteen-th resistor (R18) to the positive pole of the power source, and at the same time forms the ninetieth input (090) of the wiring, the second input of the fourteenth two-input circuit (NSD14) of the logical product negation is connected via the nineteenth resistor (R19) of the positive pole of the power source and forming the one-ninety-first first input (091) of the wiring, the second input of the fifteenth two-input circuit (NSD15) of the logic product negation is connected to the 29th resistor (R20) to the positive pole of the electrical power supply the ninety-second input (092) of the wiring, the second input of the sixteenth twin-lead 30 209222 of the circuit board (NSD16) of the logic-type negation is connected through the twenty-first resistor (R21) to the positive pole of the power supply and simultaneously forms the 90th wiring input (093), the second input of the seventeenth two-input circuit: (NSD17) type n The logic product is connected via the twenty-second resistor (R22) to the positive pole of the electrical energy source and simultaneously forms the ninth-fourth fourth input (094) of the wiring, the second input of the os-i and the sixteenth two-input circuit (NSD18) is the logic product type connected via two-thirds the resistor (R23) on the positive pole of the power source and forming at the same time the ninety-fifth input (095) of the wiring, the second input of the nineteenth two-watt circuit (NSD19) of the logical product negation is connected via the 24th resistor (Ø. 24) forms the positive pole of the power source; at the same time, the ninety-sixth input (096) of the interconnection, the second inputs of the thirty-sixth thirty-sixth two-input period (NSDK36 to NSDK39) of the logic product negation with the open collector are connected and make up the seventy-second input (072) of the wiring, adjusting inputs (34, 44, 54, 64) of the third to six-hinged circuit (AE3, AE2, ΑΕΙ, AEO) of the type D are connected at the same time for the seventy-third; the input (073) of the wiring, while their basic inputs (31,41,51,61) are connected to the positive pole of the electrical energy source and their hourly inputs (32,42,52,62) are connected to form the seventy-fourth input (074) ) wiring, the zero output (302) of the third type D flip-flop (AE3) is connected to the first input of the thirty-sixth two-input; circuit (NSDK36). the type of non-homogeneous product by the open collector, while its zeroing input (33) is connected to the output of the twenty-second j two-input circuit (NSD22) of the non-germinal product type, the zero output (402) of the fourth damper circuit (AE2) of the type D is connected to the first input of the thirty-seven two-input circuit (NSDK37) ) of the type of negation of the logical product by the open collector, while its zeroing input (43) is connected to the output of the twenty-thirdhour input circuit (NSD23) of the non-germinal product type, the zero output (502) of the fifth hinged circuit (AE1) of type D is connected to the first input of the thirty-eighth two-input circuit (NSDK38) ) type of negation of the logical product by the open collector, while its zeroing input (53) is connected to the output of the twenty-fourth input circuit (NSD24) of the negacelogous type, the one output (601) of the sixth flip-flop (AEO) of the type D forms the 43th output (0046) the wiring, the zero input (63) of the sixth flip-flop (AEO) typeD is connected to the output of the twenty-fifth. the two-input circuit (NSD25) of the negation of the logic product, whereas its zero output (602) is connected to the first input of the thirty-fourth two-input circuit (NSDK34) of the negation of the logic product with the open collector, on the first step of the thirty-second two-input circuitNSDK39 ) of the logic product negation with the open collector and at the same time form the forty-seventh output (0047) of the wiring, the input of the thirty-fourth inverter (INV34) simultaneously forms the seventy-fifth wiring input (075), while its output is connected to the first inputs of the twenty-second to twenty-fifth of a two-input circuit (NSD22 to NSD25) of the negation of a logical coincidence.  14 drawings