CS208367B1 - Method of demodulation of the,by series recorded signals with the divided phase on the moving magnetic memory code and connection for executing the same - Google Patents

Method of demodulation of the,by series recorded signals with the divided phase on the moving magnetic memory code and connection for executing the same Download PDF

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Publication number
CS208367B1
CS208367B1 CS216576A CS216576A CS208367B1 CS 208367 B1 CS208367 B1 CS 208367B1 CS 216576 A CS216576 A CS 216576A CS 216576 A CS216576 A CS 216576A CS 208367 B1 CS208367 B1 CS 208367B1
Authority
CS
Czechoslovakia
Prior art keywords
phase
signal
voltage
reproduced signal
demodulation
Prior art date
Application number
CS216576A
Other languages
Czech (cs)
English (en)
Inventor
Karl-Heinz Schmelovsky
Dieter Weisse
Ulrich Engelmann
Original Assignee
Schmelovsky Karl Heinz
Dieter Weisse
Ulrich Engelmann
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Schmelovsky Karl Heinz, Dieter Weisse, Ulrich Engelmann filed Critical Schmelovsky Karl Heinz
Publication of CS208367B1 publication Critical patent/CS208367B1/cs

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/14Digital recording or reproducing using self-clocking codes
    • G11B20/1403Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
CS216576A 1975-04-09 1976-04-02 Method of demodulation of the,by series recorded signals with the divided phase on the moving magnetic memory code and connection for executing the same CS208367B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DD18533075A DD124408A3 (nl) 1975-04-09 1975-04-09

Publications (1)

Publication Number Publication Date
CS208367B1 true CS208367B1 (en) 1981-09-15

Family

ID=5499862

Family Applications (1)

Application Number Title Priority Date Filing Date
CS216576A CS208367B1 (en) 1975-04-09 1976-04-02 Method of demodulation of the,by series recorded signals with the divided phase on the moving magnetic memory code and connection for executing the same

Country Status (6)

Country Link
CS (1) CS208367B1 (nl)
DD (1) DD124408A3 (nl)
DE (1) DE2610687A1 (nl)
FR (1) FR2307400A1 (nl)
NL (1) NL7603667A (nl)
SU (1) SU665319A1 (nl)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ZA81781B (en) * 1980-02-13 1982-03-31 Int Computers Ltd Digital systems
HU183139B (en) * 1980-05-14 1984-04-28 Magyar Optikai Muevek Electronic decoding circuit arrangement for systems with self-synchronization

Also Published As

Publication number Publication date
FR2307400A1 (fr) 1976-11-05
NL7603667A (nl) 1976-10-12
SU665319A1 (ru) 1979-05-30
DD124408A3 (nl) 1977-02-23
FR2307400B3 (nl) 1979-07-13
DE2610687A1 (de) 1977-01-20

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