CS199407B1 - Injection integrated circuit - Google Patents

Abstract

The circuit exhibits a current source formed by bipolar transistor (1). The emitter (2) of the bipolar transistor (1) is connected to a feed source, not shown. A field-effect transistor (8) has its drain electrode (10) connected to an output terminal (11), its source electrode (9) to the earth terminal (5) and to the base electrode (4) of the bipolar transistor (1), and its gate electrodes (12, 12') connected to input terminals (7, 7') and to collector electrodes (6, 6') of the bipolar transistor (1). Depending on its design, the circuit is used as NOR or NAND gate. Non-injecting rectifier contacts of the gate electrodes (12, 12'), which are also constructed as metal semiconductor junctions or respectively as Schottky diodes like the collector electrodes (6, 6'), result in shorter switching times of the circuit. <IMAGE>

Description

The invention relates to an injection integrated circuit comprising a current generator and an n-channel transistor ^{controlled by an} electric field. · its gate connected to the current generator and the input electrode of the circuit electrodes with the iizemněna and electrode D connected to ^the output ele tro ^{d b} ou of water.

In ^y finding a relationship. ^the zone of the m ROEL ^{also to ysics} tron and th ^{Ka par} exact words · ^· injection. ^and circuitry ntegrovanýc ^{h d} s s hair dryers ^to YM s ^t u ^p nem ^integration. is-F are intended to předevéím ^{y p i} T ⁱ OUZ in WslZových devices.

They are known for injection integrated circuits involving current generator and the n-channel transistor ^{of manufacture} women eleVrZkým ^p ol. ^h o is ^{from H} Radl is connected to the electrical ener ^{g s} motor and a ga ^p n ^s ele ^{kt d} ou ro circuit. ELE ^kt Rodas is grounded and the electrode D is connected to the output electrode of the circuit.

Known ^and njekčn ^{s i g} NTE Rovan ^e o ^{y b} water jsoupoměrně slow. which is creating excessive accumulation ^D Yes ^No N ^y te ^s noettelů charge it. injeVovaných pn ^EXAMPLE ec ^h o <3em game ^d lo ^electro-d and ^S. in the area of elelctro ^{dy S. * V s} m ^d n ^d u circuitry at ^EZ r ^and prices ^{for i <y} 3ob nabZ only structures ^and capacity increase naMjecZo otřebném ^{yp p} Roudou nátoj increases. nahroma ^ga NY in the area elelrtroty Ό. and ^they both ^d m increases. Vera The required ^p ro ^s in his disappearance. i.e., increase, ^and the total of ^b and ^{d p} oz ^ga in the circuitry switching ^{and d} in. In ^dl e, it is ^{characterized} in such a obvocl ^brand U is t om ^{P ez of the} sizes rn ^{of p} ou ^H ou loc. defined bočnZ kill ^of movement ^and the m ^p by m ^{and I} C ^s Skuja tyattčník ^BC COMES ^{monthly p} s ^{f ck} ormov tranurietoru gate ^{of p} ízeného elektriclcým ol. and also the necessity ^to reserve potřetaé es Ojen ^{p s} O ^towards fotošablony not ^to contact with the gate region and electrode region D and window fotošablorxy.pro impurity diffusion region in the gate electrode when forming region D.

The basic object of the present invention is to increase the speed of operation of the injection integrated circuit.

A second object of the present invention is to increase the construction density of the injection integrated circuit.

According to the invention-that the injection integrated circuit include ^í • The more rou ^{p d} AC generator and n-Vnátavý. taanztatar ^management eZVrZkým field whose gate is connected to the current generator and the input 'circuit electrodes, electrical earthing ^D and ^E on the electrodes' D. Ojen with ^p with t ^p u ^t n ^e eleHrofou circuit according 'to ^Y n and ^{l h} Cutting rac! la taanz.Ztoru ^management field ^H o eleVrZkým performed both VP ^ NEJM Step ^{E d} is no ^H on neZjeVujtaZo usmeróujtáho. contact. *>

The expansion ^of en ^{l f} un ^to Cioni ^L N ^I CH possibility ^ water is ^expedient b ^y tranzZtar control electr ^{ic to} YM ^p o ^l EM ^was carried ^d en DV ^E has neinjeVujícími ^'to ONTAK ^ones and were, introduced supplementary an input electrode, the second contact being connected to this additional input electrode.

To increase the density of integrated circuit structures injection is expedient to use in place of the current generator, a bipolar transistor with a metal collector joint 's ^H r ^dl em' ^s steering tranzZtaru ^{of manufacture} it elektoiclcýin field.

It is also ^{EZ 'Prior} Eze Provit Ztagrovaný. a ^{b d} j and ^k in the semiconducting ^^ ou staukturu with current enerátorem ^g of ^p ODD ^runs bipolářtího planárntoo ranzistoru ^t and ^p lanárnZ trenzZZrem ^{of manufacture} of women elelctrickým ^{p l h} r em ^dl verifies' obílast umtatanou ^ ^{P h} u ovrc pads as ^for ovovým ^and combined inside ^'b of the water masses at ^the rozZženými uj ^{i s} c m r ^d iele ^{kt also} at; game ^dL b ^s area taanzZtoru ^{of manufacture} zen ^eh of electric ^p o ^l EM as ^p Eq ^E ST the following ^d about ^{BE Ú to} U-h ^ no permanent o ^ odových joints umZtený ^ to nemaskovanýc ^h Ilse ^ ch ^p ovrc ^h at ^p deferred ^clippers and ctoánených with Ora ^h i ^l e ^{d kt} ri ^to em to ^d dying region is NZZ electrodes d Dad's ^PU with ^{b am,} and ^would create a mic ^{for h} ý account ^kt sp ^ lo ^ ou. in ^{official to} at covering. o ^ astml prostarov ^ he ^ ^and combating neZjeVuj CPP. USM uj ^{of n} r ^s c ^s c ^h kontaVů hradlovýZ areas.

To simplify the technology is expedient to place the pad of the integrated otoodu in vz ^ laziness from ^{above, the} now obsolete exceed ^TL ou ^MOT at layer ^p rostarové ^h on ^ÁB drawbar neZjeVujZZo USM ^{of n} r uj ^and C ^iH contact hradZvé area Držkov region of opposite type conductivity than the type of conductivity of the pad, and such. accordingly, these b ^{y p} L ^N to the metal ^and the ^BL AST completely covered ohmZ-contact electrodes D washer.

^Further text. is tanto invention is explained ^ETL eh 'popZem konkrátnZh varZnt its Will you and' ^EXAMPLE Bulk ^and drawings' to NZH ^Z in ^Y finding pOdstavuje FIG. 1 shows a basic electrical diagram of the injection of the integrated circuit, - a logical gate OR-NO "FIG. 2 schematically semiconductor. the structure of the same valve as in Fig. ^1, after poUedu above for R ^b. 3rd sdíematacky potavo ^ fovou struVuru ^Teh oz Vent ^il u as in FIG. ^1, and P & iodate section, FIG. 4 scliematZky rlovo ^ Côvo struVuru valve with 'two inputs, with Prou ^d ew ^g enerátcram designed as ^a bipolar transistor smetalickým collector Fig. 5 schematically shows a planar semiconductor structure of a transistor controlled by an electric field 3 in the form of sections of inner peripheral connections, in cross section, Fig. 6 schematically a semiconductor structure of the transistor electric field-controlled with an additional region of the conductivity of the conductor opposite to that of the substrate, in cross-section.

Fig. 1 shows a basic electrical diagram of one variant of the invention of the proposed logic integrated circuit - a logic valve.

The logic valve comprises a current generator made as a bipolar transistor 1J whose emitter 2 is connected to the electrode Д of the supply circuit (not shown in Fig. 1), the base Д is connected to the ground electrode g and the collectors 6 а в 'are correspondingly connected to the input electrodes 1 and the logic valve. The logic valve further comprises an n-channel transistor controlled by an electric field S with an electrode region S connected to the ground electrode g, with an electrode region D connected to the output electrode 11 and gate regions 12 and 12 /, designed as ninject rectifying contacts. and connected correspondingly to the input electrodes 7 and 7 ^{of the} logic valve.

In the variant of the circuit according to FIG. 1, the gate of the regions 12 and 12 ^{of the} transistor 8 controlled by the electric field is designed as two non-injecting rectifying contacts, the second contact being connected to an additional input electrode 2 ^Z ·. FIG. 2 is a schematic illustration of the semiconductor structure of the same logic valve as in FIG.

The designation of the basic elements in FIG. 2 is identical to the designation in FIG. 1. The current generator, formed as a bipolar transistor 1 and an electric field controlled transistor 8, is formed in a common semiconductor substrate.

13. having an n-type conductivity, wherein the base region 6 of the transistor 1 and the electrode region 2 of the n-channel transistor 8 controlled by the electric field are common.

FIG. 3 is a schematic representation of the same semiconductor structure as in FIG. 2; the designation of the base elements is identical to that of FIG. 2. The electrode region 10 of the electric field-controlled transistor 8 is located between the non-injecting rectifying contacts of the gate regions 12 and 12. ^z , the boundaries of the spatial charge layers of the rectifying contacts of the gate regions 12 and 12 'in the substrate 13 are shown in dashed lines. »

Fig. 4 schematically illustrates a semiconductor structure of a logic valve with two inputs, an 8 current generator in the form of a bipolar transistor and metallic collectors that are common to the gates of an electric field controlled transistor. In the structure, the metallic collectors of the bipolar transistor are common to the gate regions 12 and 12 ^z , in the form of Schottky diode metal-semiconductor transitions.

’199407

The increase in the density of the integrated circuit is achieved in a given structure by the fact that the above-mentioned collector regions 6, в 'and the gates 12, 12' are common and thus the joints between the collectors 6 and 6 'with the gate regions 12 are removed. and 12. It should be noted that such realization of common areas is possible due to the realization of a current generator in the form of a bipolar transistor with a metallic collector. '

FIG. 5 is schemaHcky representation ^of at planar after-treatment ^ ew stru ^ ura 'n-channel ^é it trance ^and Stora 8 ^{of manufacture} zen ^eh about dyna ^to YM ^{p ol, p ATR} projecting to the assembly of integrated circuit logic valve whose the basic electrical diagram is shown in Fig. 1. The remaining part of the circuit can be executed as shown in Fig. 4.

In finding ^{y h} Return ^to Maintenance ^and onstruk CE int.egrovan ^ oo ^{d b} in US women transistor ^{of manufacture} by an electric field to the gate regions in the form of contacts neinjektujících permitted transfer gate region '12 and 12 / in the form of sections with internal metal circuit board 14 This construction provides the possibility of constructing the gate regions 12 and 12 'at the same time as the first layer of joints is formed within the periphery of the integrated circuit.

Positioning ^of the ^BL AST ^and about 10 e ^l e ^kt genus ^y D ^dd tr purpose ^for which ^also the 16th EM · chrtoZZ connection 14 within the circumference, allows to place the area. 10 electrodes. D at the same time as the second layer of connections is formed inside the circuit (not shown in FIG. 6) of the integrated circuit.

FIG. 6 is a schematic Zorn ^of Zn ^and lead to ^p and ^d s ^{s No} stouUura ^STE is one ^e variant řízeného'elektrickým transistor array, which is part of the structure of the proposed integrated circuit according to the invention. The structure differs from that described and illustrated above. 5 in FIG. that it has an additional area

17th arranged on the substrate 13 - and at a distance from the surface ·, · and this model ^{can be} lazy ^t not exceed ^p. Lou ^{T W T} TKU VRS in ^YP rostorov it ^é n ^ÁB drawbar nezjevujícího usmerňujZZo ^to ontact Rádlová ^{h e} o ^{b and} 12. The ^{last-BL t} and t ^ype 17. conductance which is a ^p by ^p those ation. conductivity. su ^{b STR} 13. In the given ^{d or} e and p ^type with a ^di bility. . ^Area 17 is. placed by Ztovým. in a way, and ^would . ohmZký contact 18 covering the area D with substrate 13 · introduction of an additional field 21 ^enables uje.zv ^E t ^network education ^and Lena limit ^and game ^{dL i} ew 'regions 12 and 12', and Z ^{d d} u no ^IT tec ^h no ^L of ^GII of ^h o ^{s t} oven Ztegrovan ^ of UV circumferential ^{d d d} to mitigate USLE ^{of both} N ^{and P d} Oza AVK otoSablonu ^{of F,} wherein ^a is. used in the ^{runs and p s} hrabových shaped areas.

The injection IC (logic valve) operates as follows. The emitter region 2 of the bipolar transistor 1 injects holes into the base region 4, which is for the base region 6. appears as minor carriers of ^drawers . ^Those that n holders ^ÁB drawbar ^to omuZjí oWastmi ^{to the} olefin ^of 6 Torr, and '6'. By voltage to. ga ^p n ^I CH electronics ^gives C ^H 2 and 1 ^'b m№e yl ^ Z CKY valve is ^d nom of the following conditions.

^If Buůe- to about ^BE ga ^p n ^and the electrodes 2 ^and 2 * Povedené nhke voltage ^EIT bed, couch ^b poZncZlu ground ^^ ^p and n nosheW ^{ÁB drawbar} VmuZjící the ^straight ec ^h o ^dy of ^{b! T} and s

5 199407 collectors 6 and 6 ',. run down on. earth *. The output electrode 11 does not have a galvanic bond to the ground electrode 2, and if the valve is connected to an analog valve (not shown in FIG. 1), then a high voltage will be present at the electrode 11 equal to the release voltage of the transition between the gate regions. 12 and 12 '

The interruption of the galvanic coupling occurs as a result of the presence of a portion of the substrate 13 located between the electrodes 11 and 2, namely by the spatial charge layers, the closed transitions between the gate regions 12, 12 'and the electrode region S'. shown in Fig. 3 with dashed lines). .

A high voltage is applied to the input electrodes 2 and 1 ', exceeding the release voltage of the transitions between the gate regions 12, 12' and the electrode region 2, then there is a galvanic coupling between the electrodes 11 and 2. electrode 2 earth. Said galvanic coupling is provided by reducing the dimensions of the spatial charge region of the transitions between the gate regions 12, 12 'ΘΜ. i a

If a low voltage is applied to one of the input electrodes 2 or 2, then there are two possibilities. First - if the resistivity obb-asli · 10 and the distance L · between the gate regions · 12 and 12 '(Fig. 2) are chosen so that the space charge layer of the transition · between the gate regions 12 and 2 is greater than or equal to the distance L The second, if the spatial charge layer width of said transition is less than the distance L. In the first case, there is an electrical galvanic coupling between electrodes 11 and 2, in the second case there is no galvanic coupling between electrodes 11 and ground (electrode 5). .

In this way, the proposed logic can, depending on the structural-topological parameters (L-value and resistivity 10), perform the OR-NO or A-NO logic function. ·

The increase in the speed of the logic element is achieved by the use of non-injecting smear contacts - metal-semiconductor transitions as gate portions 12 and 12 'and collector greases 6 and 6'. By not injecting minor charge numbers from gate embraces 12 and 12, there is no accumulation of excess charge in the .alpha.-12 portion, thereby significantly reducing the transition time in the logic outboard when transitioning from an open to a state. closed.

The special feature of the electric circuit-driven integrated circuit integrated circuit shown in FIG. 6 is the following. The additional region 'prevents current flow from the output electrode 11 to the electrode region 2'

It is perpendicular to the surface of the IC and ensures that the current path extends parallel to the surface. If a low potential is present on the gate regions and 12 '·, the spatial charge layer overlaps the path · current passage, since the additional 17 · completely overlaps the ohmic con199407

- 6 bars of area 10. The area 17 may be connected to or on the ground. may, -flats pří.vedeno ^p osunutí voltage - preload from ^the supplementary source • ^j e voltage.

The invention proposed is characterized by the integrated circuit and the technological aspects of ^{h b} YT otoven ^pl enárn ^and TEC ^{h l} o ^{g amino-II} as with ^uses m '^ ephaxn Folo d ,. and without them. ,.

^shi MA ^{for functionalized and} the possibilities he ^AL and ^y with ^{y ka} r c ost ^or to structure the ^hl. unwinding the wide angle vvuž ^é ^ s ⁱ n ^{g t h} e ^b oo ^eh Rovan water after ^dL ev ^y to ^l cut ^when assembling the large-tegrovaných circuits vysokou.hustotou elements on. crystal.

The object of the invention

Claims (5)

The object of the invention First Inje ^{CZK nus} wtegrovaný of water ^b · ^{h b} is about uj ^s c ^{s g} enerótor sorghum and N- ^to análový transistor ^- women ^{of manufacture} Elekta ^ lcým pólemj whose ^h lo r ^d is connected to the current generator and the input ^and ele ^kt ro ^d ou a ^b a ^d u ele ^to tro ^d and ^- an earthed ^- e ^l ektroda b connected to the output 'electrode circuit, characterized in that the gate (12), trance ^and Area (8) ^R Zen ^é it electroencephalogram yM-field is carried in en.o ^{d f} orm ^of at ^{least d} is no ^H on the non-jektujícíto USM rtovac ^ ^ o ^ ^ u ONTAK. 2. An injection integrated circuit according to claim 1, wherein the transistor. ^{(8) n} women e ^l e ^kt generally proved after ^L em o ^B is ^H, U is ^d va neinjek ^t uj ^I C ^s The contacts and ^d o ^p ln ^k verifies vs ^t for ^p n ^s ele ^kt ro ^d u (7 ^{') EXAMPLE Identification of d} em ruhý ^to ontact is ^p Ojen ^- with ^{d PLN} metal vs. ^{T p} u n ^{e kt} ele ro ou ^{d (1} '). 3. Injectable A integrated circuit according to claim 1, ..vyznačující in that a current generator is a bipolar transistor (1) having a metallic collector ^{(б, '6'),} with ^p a ^l ečným ^dl game with Em (1 ^ ¹² ') of the transistor ^{I8) management} of ^eh ^ · e ktrickým field. ' 4 · Injection integrated circuit according to Item 1, characterized by: se'tím that ^p ovrchu substrate, ^and the (3 ¹⁾ positioned ^{é é} hra.dlov otoasti (1 → ¹²⁾ of the transistor ^{(8) management é} ^ ele it nckým field, perform en ^{d eh} of a planar sensors. are ^p rove ^d enes in after ^d o vv BE-metal portions, for masking the dielectric (15) disposed, the internal connections circumferential ^d u (14-in. that ^at the ^{ing straight} aces ^h uj ^and smell to nemas ^the crosslinked with ^{e. determining for} the ^{ky p} ovrc ^h in su ^b p ^and TU ⁽¹ 3). a. ^Chr n ^{e d} 'above ^di elec ^tri ek ⁽¹⁶ ^ above NUR is Uras ^ in ^- oWast (10} of the electrode. D forming an ohmic contact ( 18) of the substrate (13) ^for check ^BC e ^k RYVAN ^é m the spatial ^é him n ^ÁB drawbar n ^ n ^ both stages ^ h UAM ^{of Rn} UJ ^I C ^I CH account ^{TU h} a ^d-target zone of the (1 → L ² '^ ^{when CEM} Prou ^d or AC gener ^. is carried in the en ^d of ^{d p p Both} LAN ^and a ^¹H RN ^BIP ol ^{a ry} him transistor ^(1). 5. An injection integrated circuit according to claim 4, characterized in that in the substrate, ^{and (3 1)} is lazy mod ^ ^ ^{(A) p} of surface to be ^{treated,. BC} no evyšuj ^I C ^I ^ oušťku layer ^P ros ^t he ^eh orov ^ÁB ojejneinjektujíctao USM ^{of Rn} UJ ^I C ^¹H ko ^ ^é act gate electrode area S is disposed complementary region. (17) conductivity type which is opposite in type ^No. Nu ^d emissivities ^and substrates ^PRICE em ^{from D} L ^{N P} of the metal ^and the region ^{of L} chain and. e ^{BC to} jerk ^and ohmic contact (18) area (10) of the electrode · D 'with the substrate (13) · " REPAIR '' '' I will describe the invention to author's certificate No. 199 407 ~ (51) Hlt. СР - H 911 27/00 In the description of the invention for the author's certificate No. 199 407 should be ₄ in the heading: Correctly: '(32) (31) (33) Right of priority From 08 01 77 (2441385). . · From 01 11 77 (2537101) From 11 11 77 (2537006) Soviet Union" CKAD PROVYNAI.EZYA DISCOVERIES