CH616276A5 - Integrated injection circuit - Google Patents

Description

The invention relates to an integrated injection circuit with a current source and a normally blocked n-channel field effect transistor, in which the gate is connected to the current source and the input electrode of the circuit, the source is grounded and the drain is connected to the output electrode of the circuit.

Integrated injection circuits are known which include a current source and a normally blocked n-channel field effect transistor in which the gate is connected to the current source and the input electrode of the circuit, the source is grounded and the drain is connected to the output electrode of the circuit Has.

However, the known integrated injection circuits have a relatively low operating speed, which is a result of the accumulation of excess charge carriers in the source region, which are injected through the gate-source-pn junction. When the feed current is amplified to shorten the charging time of capacities of the structure, the charge generated in the source region increases in these circuits and consequently the time required for their dissipation increases, so the total time of the switching delay increases. In addition, the circuits have a relatively large area, which is caused by the lateral penetration of additives under the masking oxide layer when the gate is formed and by the need for additional covers in the photo stencil windows, which is necessary for the formation of contacts with the gate and drain regions and for the diffusion of admixtures into the gate region in the formation of the drain region.

The invention has for its object to develop an integrated injection circuit with a normally blocked n-channel field effect transistor, the structure of which results in a significant increase in the operating speed and a smaller area of the circuit, without the requirements for the dimensions of the stencil window and the accuracy of the photolithographic processes are increased.

The invention aims to increase the operating speed of the integrated injection circuit.

In an injection integrated circuit with a current source and a normally blocked n-channel field effect transistor, in which the gate is connected to the current source and the input electrode of the circuit, the source is grounded and the drain is connected to the output electrode of the circuit, this goal becomes achieved according to the invention in that the gate of the field effect transistor is designed as at least one non-injecting rectifier contact.

To expand the functional possibilities of the circuit, the field effect transistor can expediently be designed with two non-injecting contacts and an additional input electrode, the second contact being connected to this additional input electrode.

To increase the packing density, a bipolar transistor with a metal collector is expediently used as the current source, the metal collector being connected to the gate of the field effect transistor.

The integrated circuit is expediently designed with a bipolar planar transistor as the current source and with a planar field-effect transistor in which the gate region lies on the surface of the substrate, while the internal metal conductor connections are arranged on the masking dielectric, the gate regions of the field-effect transistor are expediently designed as sections of the internal conductor connections which lie on unmasked sections of the substrate surface and are protected from above with a dielectric, and the drain region is arranged above this dielectric in such a way that it forms an ohmic contact with the substrate on a surface, which is smaller than the space charge regions of the non-injecting rectifier contacts of the gate regions.

In the substrate of the integrated circuit, at a distance from the surface which is smaller than the thickness of the space charge layer of the non-injecting rectifier contact of the gate region, an additional region of the opposite conductivity type is expediently formed in such a way that this region is larger than the area of the ohmic contact of the drain region with the substrate.

The invention is explained in more detail in the following description of the specific design variants and with reference to the accompanying drawings

Figure 1 is an electrical schematic diagram of the integrated injection circuit designed as a logic OR-NOT gate.

FIG. 2 shows a schematic illustration of the semiconductor structure of the same gate according to FIG. 1, top view;

Fig. 3 is a schematic representation of the gate of Figure 1 in cross section.

4 shows a schematic illustration of the semiconductor structure of a gate with two inputs and with a current source,

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which is formed by a bipolar transistor with a metal collector, which is connected to the gate of the field effect transistor (top view);

5 shows a schematic cross-sectional illustration of the semiconductor planar structure of the field effect transistor, the gate regions of which are designed as sections of the internal conductor connections;

Fig. 6 is a schematic cross-sectional view of the field effect transistor with an additional region of the opposite conductivity type. io

In Fig. 1, an electrical schematic diagram of a variant of the integrated circuit designed as a logic gate according to the invention is shown.

The gate contains a bipolar transistor 1 which forms a current source, in which the emitter 2 is connected to the electrode 3 of the supply circuit not shown in FIG. 1, the base 4 is connected to the ground electrode 5 and the collectors 6 and 6 'to the input electrodes 7 or T of the gate. In addition, the gate contains a normally blocked n-channel field-effect transistor 8, in which the source region 9 with the earth electrode 5, the drain region 10 with the output electrode 11 and the gate regions 12 and 12 ′, which are designed as non-injecting rectifier contacts the input electrodes 7 and 7 'of the gate are connected.

Thus, the gate of the field effect transistor 8 in the circuit variant shown in FIG. 1 25 is designed as two non-injecting rectifier contacts (regions 12 and 12 '), the second contact being connected to the additional input electrode T.

FIG. 2 shows a schematic representation, not to scale, of the semiconductor structure of the same logic gate according to FIG. 1, the designations of the most important elements from FIG. 1 being retained.

The current source consisting of a bipolar transistor 1 and the field effect transistor 8 are embodied in the common n-type semiconductor substrate 13, the base region 4 of the transistor 1 and the source region 9 of the n-channel field effect transistor 8 being connected.

FIG. 3 schematically shows the semiconductor structure according to FIG. 2 with the same designations. The drain region 10 of the field-effect transistor 8 lies between the non-injecting rectifier contacts of the gate regions 12 and 12 ', the broken lines show the boundaries of space charge layers of the rectifier contacts of the regions 12 and 12' formed with the substrate 13. 45

4 schematically illustrates the semiconductor structure of a logic gate with two inputs and with a current source realized by means of a bipolar transistor, the metal collectors of which are connected to the gates of the field effect transistor. In this structure, namely, the metal collectors 6 and 6 'of the bipolar transistor 1 are brought together with the gate regions 12 and 12', which are designed as metal-semiconductor junctions of the Schottky diode type.

In this circuit structure, the increase in the packing density is achieved by combining the collectors 6, 55 6 ′ and the gate regions 12, 12 ′, that is to say by removing the conductor connections between the collectors 6, 6 ′ and the gate regions 12 and 12 ′ . It should be noted that this unification of the regions was made possible by designing the current generator in the manner of a bipolar transistor with a metal collector 6o.

FIG. 5 schematically shows the semiconductor planar structure of a normally blocked n-channel field effect transistor 8, which belongs to the integrated circuit of the logic gate, the basic circuit diagram of which is shown in FIG. 1. The remaining part of the circuit can be constructed in the same way as in FIG. 4.

The proposed structure of the integrated circuit, which includes a field effect transistor with the gate regions in the manner of non-injecting contacts, enables the gate regions 12 and 12 'to be implemented in the form of sections of the inner metal conductor connections 14 which are exposed to the masking dielectric 15 uncovered sections of the substrate 13 lie. This structure enables the gate regions 12 and 12 'to be produced simultaneously with the formation of the first layer of the inner conductor connections in the integrated circuit. The arrangement of the drain region 10 over the dielectric 16, which protects the inner conductor connections 14, enables the production of the drain region 10 simultaneously with the formation of the second layer of the internal conductor connections of the integrated circuit, which are not shown in FIG. 6.

6 schematically shows the semiconductor structure of a further embodiment variant of the field effect transistor, which is part of the structure of the proposed integrated circuit. This structure differs from the type described and shown in FIG. 5 by the presence of an additional region 17, which lies in the substrate 13 at a distance a from the surface, this distance a not greater than the thickness of the space charge layer of the non-injecting rectifier contact of the gate - Area 12 is. The area 17 has the opposite conduction type to the substrate 13, possibly the p-conduction type. This region 17 is arranged such that it is larger than the area of the ohmic contact 18 of the drain region with the substrate 13. The introduction of the additional region 17 makes it possible to increase the distance between the gate regions 12 and 12 ′ from one another and to simplify the manufacturing technology of the integrated circuit as a result of less stringent requirements for the photo template intended for forming the gate regions.

The integrated injection circuit designed as a logic gate works as follows. The emitter region 2 of the bipolar transistor 1 injects 4 holes into the base region, which holes appear for the region 4 as minority charge carriers. These charge carriers are collected by the collector areas 6 and 6 '. Depending on the voltage at the input electrodes 7 and 7 ', one of the states described below can be set in the logic gate.

If there is a low voltage at the two input electrodes 7 and 7 ', which is close to the “earth” potential, the charge carriers collected by transitions of the regions 6 and 6 ′ flow to the “earth”. The output electrode 11 has no conductive connection to the earth electrode 5. If the gate is loaded with a similar gate, not shown in FIG. 1, a higher voltage builds up on the electrode 11, which is the threshold voltage of the transition between the regions 12 , 12 'and 9 corresponds.

The aforementioned conductive connection is interrupted as a result of the overlap of the portion of the substrate 13 lying between the electrodes 11 and 5 by the space charge layers of the blocked junctions between the regions 12, 12 'and 9 (the space charge layers are indicated by dashed lines in FIG. 3).

If the input electrodes 7 and T carry a higher voltage, which is higher than the threshold voltage of the transitions between the regions 12, 12 'and 9, then there is the conductive connection between the electrodes 11 and 5, and the voltage is at the output of the logic gate near the voltage at the ground electrode 5. The conductive connection mentioned arises as a result of the reduction in dimensions of the space charge region of the transitions between the regions 12, 12 'and 9, with the increase in the voltage at the input electrodes 7 and 7'.

If a lower voltage is applied to one of the electrodes 7 or 7 ', there are two possibilities. In the first case, - if the specific resistance of the area 10

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and the mutual distance L of the regions 12 and 12 '(FIG. 2) are selected such that the width of the space charge layer of the transition between the regions 12 and 9 is greater than or equal to the distance L. The second possible state arises when the width of the space charge layer of the transition mentioned is smaller than the distance L. In the first case there is no conductive connection between electrodes 11 and 5, and in the second case there is a conductive connection between electrode 11 and the “earth” (electrode 5).

The logical element constructed according to the invention can therefore perform the logical functions “OR-NOT” and “AND-NOT” depending on its structural topological parameters (depending on the size L and the specific resistance of the region 10).

The increase in the operating speed of the logic element is achieved in that the non-injecting rectifier contacts (the metal-semiconductor junctions) are used for the gate regions 12 and 12 'and for the collector regions 6 and 6'. Failure to inject minority carriers from gate regions 12 and 12 '

causes the lack of excess charge in region 13 and results in a large reduction in the duration of transitions in the logic gate during the transition from the conductive to the blocked state.

5 The peculiarity of the work of the integrated circuit shown in FIG. 6 with the field effect transistor is that the additional region 17 prevents the current flow from the output electrode 11 to the source region 9 in the normal direction to the surface of the integrated circuit and io the parallel to the surface directional current flow. At the lower potential at the gate regions 12 and 12 ′, the space charge layer blocks the current flow away, since the area of the ohmic contact of the drain region 10 with the substrate 13 is smaller than the additional region 17. Area 17 can be connected to “earth” or it can be biased by an additional voltage source.

The proposed integrated circuit is right in terms of production and can be produced on the basis of planar technology with and without epitaxial layers.

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2 sheets of drawings

Claims (5)

616276 PATENT CLAIMS 1. Integrated injection circuit with a current source and a normally blocked n-channel field effect transistor, in which the gate is connected to the current source and the input electrode of the circuit, the source is grounded and the drain is connected to the output electrode of the circuit, thereby characterized in that the gate (12) of the field effect transistor (8) is designed as at least one non-injecting rectifier contact. 2. Integrated injection circuit according to claim 1, characterized in that the field effect transistor (8) is designed with two non-injecting contacts and an additional input electrode (7 '), the second contact being connected as a gate (12') to this additional input electrode (7 '). 3. Integrated injection circuit according to claim 1, characterized by a bipolar transistor (1) with a metal collector (6,6 ') as a current source, the metal collector (6,6') being connected to the gate (12,12 ') of the field effect transistor (8) is. 4. Integrated injection circuit according to claim 1 with a bipolar planar transistor as a current source and with a planar field effect transistor in which the gate region lies on the surface of the substrate, and with internal metal conductor connections which are arranged on a masking dielectric, characterized in that the gate regions (12, 120 of the field effect transistor (8) are designed as sections of the internal conductor connections (14) which lie on unmasked surface sections of the substrate (13) and are protected from above with a dielectric (16), and that the drain Region (10) is arranged such that it forms an ohmic contact (18) with the substrate (13) on an area which is smaller than the space charge regions of the rectifier contacts of the gate regions (12, 12 '). 5. Integrated injection circuit according to claim 4, characterized in that in the substrate (13), at a distance from the surface which is smaller than the thickness of the space charge layer of the non-injecting rectifier contact, an additional region (17) is formed with the opposite conductivity type to the substrate (13) that this area (17) is larger than the area of the ohmic contact (18) of the drain area (10) with the substrate (13).