GB1565918A - Integrated injection circiut devices - Google Patents
Integrated injection circiut devices Download PDFInfo
- Publication number
- GB1565918A GB1565918A GB39578A GB39578A GB1565918A GB 1565918 A GB1565918 A GB 1565918A GB 39578 A GB39578 A GB 39578A GB 39578 A GB39578 A GB 39578A GB 1565918 A GB1565918 A GB 1565918A
- Authority
- GB
- United Kingdom
- Prior art keywords
- zone
- gate
- zones
- electrode
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000002347 injection Methods 0.000 title claims description 15
- 239000007924 injection Substances 0.000 title claims description 15
- 230000005669 field effect Effects 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims description 24
- 230000000295 complement effect Effects 0.000 claims description 16
- 230000008878 coupling Effects 0.000 claims description 12
- 238000010168 coupling process Methods 0.000 claims description 12
- 238000005859 coupling reaction Methods 0.000 claims description 12
- 239000002800 charge carrier Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 4
- 238000012856 packing Methods 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 claims description 3
- 230000000873 masking effect Effects 0.000 claims description 3
- 239000000969 carrier Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 238000004377 microelectronic Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
- H01L27/0225—Charge injection in static induction transistor logic structures [SITL]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
- H01L27/0722—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with lateral bipolar transistors and diodes, or capacitors, or resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/091—Integrated injection logic or merged transistor logic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09403—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using junction field-effect transistors
- H03K19/09414—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using junction field-effect transistors with gate injection or static induction [STIL]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09403—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using junction field-effect transistors
- H03K19/09418—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using junction field-effect transistors in combination with bipolar transistors [BIFET]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using Schottky type FET MESFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Ceramic Engineering (AREA)
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The circuit exhibits a current source formed by bipolar transistor (1). The emitter (2) of the bipolar transistor (1) is connected to a feed source, not shown. A field-effect transistor (8) has its drain electrode (10) connected to an output terminal (11), its source electrode (9) to the earth terminal (5) and to the base electrode (4) of the bipolar transistor (1), and its gate electrodes (12, 12') connected to input terminals (7, 7') and to collector electrodes (6, 6') of the bipolar transistor (1). Depending on its design, the circuit is used as NOR or NAND gate. Non-injecting rectifier contacts of the gate electrodes (12, 12'), which are also constructed as metal semiconductor junctions or respectively as Schottky diodes like the collector electrodes (6, 6'), result in shorter switching times of the circuit. <IMAGE>
Description
(54) IMPROVED INTEGRATED INJECTION
CIRCUIT DEVICES
(71) We, ARTASHES RUBENOVICH
NAZARIAN, of ploschad Junosti, 3, kv.16, Moscow, USSR., VYACHESLAV
YAKOVLEWICH KREMLEV, of 103482 korpus 423, kv.81, Moscow,
USSR., VILYAM NIKOLAEVICH
KOKIN, of 103498, korpus 441, kv.115.
Moscow, USSR., VIKTOR IVANOVICH
SLADKOV, of Berezovaya alleya, 6, kv.77, Moscow, USSR., BORIS
VALENTINOVICH VENKOV, of 103460, korpus 206, kv.46, Moscow, USSR,
VADIM VALERIEVICH LAVROV, of
Moskovskoi oblasti, ulitsa 8 Marta, 7, kv.
125, Khimki, USSR., all USSR citizens, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The present invention relates to microelectronics technology and in particular to large-scale integrated injection circuits intended primarily for digital computers.
According to the invention there is provided an integrated injection device which comprises a constant current device and a normally cut-off n-channel field-effect transistor having a gate including at least one non-injecting rectifying contact connected to the constant current device and to an input electrode of the device, its source grounded and its drain connected to an output electrode of the device, wherein said field effect transistor is cut off when the, or one of, or all of said at least one contact is at a potential close to ground potential.
In order to increase the number of possible functional applications of the device a preferred embodiment comprises a field-effect transistor having two noninjecting contacts and an additional, complementary input electrode, the second said contact being connected to said complementary input electrode.
In order to increase the packing density it is preferred that the device comprises a constant current device formed by a bipolar transistor having a metal collector which is combined with a gate of the field-effect transistor.
Preferably the constant current device is a planar bipolar transistor provided with metal gate electrodes located on a masking dielectric layer, the gate zones of the fieldeffect transistor are located on the surface of the substrate and are arranged as interconnection sections located on unmasked substrate surface areas and protected with a dielectric layer from above, the drain electrode being partly located above said dielectric layer and extending therethrough to form an ohmic contact with the substrate at the area which is overlapped by space charge areas of the rectifying contacts of the gate zones.
In order to simplify the production procedure a preferred embodiment of the integrated circuit comprises a substrate wherein a complementary zone is provided at a distance from the surface which does not exceed the thickness of the space charge layer produced by the non-iniecting rectifying contact of the gate zone, the conductivity of the complementary zone being opposite to that of the substrate, while this zone overlaps completely the ohmic contact between the drain zone and the substrate.
The invention will be better understood from the following description of its embodiments given by way of example with reference to the accompanying drawings in which:
Figure 1 presents a circuit diagram of an integrated iniection circuit, according to the invention, which performs the functions of a
NOR gate;
Figurea 2 presents a diagrammatic plan of the semiconductor structure forming the integrated iRjection circuit shown in Figure 1; Figure 3 presents a diagrammatic cross section of the semiconductor structure shown in Figure 2;
Figure 4 presents a diagrammatiac plan of a semiconductor structure, according to the invention, performing the functions of a double-input gate and including a constant current device made as a bipolar transistor having a metal collector which is combined with the gate of the field-effect transistor;
Figure 5 presents a diagrammatic cross section of the planar semiconductor structure of Figure 4 arranged as a fieldeffect transistor with gate zones made as interconnection sections; and
Figure 6 presents a diagrammatic cross section of a semiconductor structure according to the invention and performing the functions of a field-effect transistor which is provided with a complementary zone with the conductivity opposite to that of the substrate.
Figure 1 is a circuit diagram of one embodiment of the integrated circuit of the present invention which performs the functions of a logical gate.
The logical gate comprises a constant current device including a bipolar transistor 1 having its emitter 2 connected to an electrode 3 for connection to a current supply (not shown in Figure 1), its base 4 connected to a ground electrode 5 and its collectors 6 and 6' connected to respective.
input electrodes 7 and 7' of the logical gate.
In addition, the gate comprises a normally cut-off n-channel field-effect transistor 8 having a source zone 9 connected to the ground electrode 5, a drain zone 10 connected to an output electrode 11 and gate zones 12 and 12' made as non-injecting rectifying contacts which are connected to the respective input electrodes 7 and 7' of the logical gate.
Figure 2 shows an unscaled diagram of the semiconductor structure of the logical gate shown in Figure 1.
The notations used in Figure 2 to denote major components of the circuit are the same as those used in Figure 1. The current generator, comprising bipolar transistor 1, and the field-effect transistor 8 are formed on the same n-type semiconductor substrate
13, the base zone 4 of the transistor 1 and the source zone 9 of the n-channel fieldeffect transitor 8 being combined.
Figure 3 shows the same semiconductor structure as shown in Figure 2, the notations to denote major components of the circuit are also the same. The drain zone 10 of the field-effect transistor 8 is located between the non-injecting rectifying contacts of the gate zones 12 and 12', dashed iines indicate the boundaries of space charge layers of the rectifying contacts between the zones 12 and 12' and the substrate 13.
Figure 4 shows a diagrammatic plan of a semiconductor structure performing the functions of a double-input logical gate which comprises a constant current device formed by a bipolar transistor with metal collectors unitary with the respective gates of the field-effect transistor. In the structure of Figure 4 the metal collectors 6 and 6' of the bipolar transistor 1 are unitary with the gate zones 12 and 12', formed as metalsemiconductor junctions of the Schottkydiode type.
The present structure makes is possible to increase the packing density due to the fact that the zones 6, 6' and 12, 12' are unitary, and hence there is no need to provide interconnections between the collectors 6, 6' and the gate zones 12 and 12'. It should be pointed out that this zone combination becomes feasible because the constant current device comprises a bipolar transistor with a metal collector.
Figure 5 shows a schematic sectional view of a planar semiconductor structure which is suitable to form the normally cut-off nchannel field-effect transistor 8 which is an element of the logical gate integrated circuit as shown in the form of a circuit diagram in
Figure 1. The remainder of the circuit is made just as shown in Figure 4.
The proposed design of the integrated circuit having a field-effect transistor of which the gate zones are made as noninjecting contacts allows the gate zones 12 and 12' to be formed by portions of metal layers 14 located on such areas of the substrate 13 that are not protected by a masking dielectric layer 15. This arrangement makes it possible to fabricate the gate zones 12 and 12' simultaneously with the first layer of integrated circuit interconnections. The fact that the drain electrode 10 is located partly above and extends through the dielectric layer 16 which protects the interconnections 14, to form an ohmic contact with the substrate at 18 allows the drain electrode 10 to be fabricated simultaneously with the second layer of integrated circuit interconnections (not shown in Figure 5).
Figure 6 shows a diagram of another embodiment of the semiconductor structure performing the functions of the field-effect transistor which forms an element of the integrated circuit structure of the invention.
The structure differs from that described above and shown in Figure 5 in that it is provided with a complementary zone 17 located in the substrate 13 at a distance "a" from the surface, the distance "a" being less than the thickness of the space-charge layer generated by the non-injecting rectifying contact of the gate zone 12. The conductivity type of the zone 17 is opposite to that of the substrate 13. In this case the zone 17 has p-type conductivity and is located so that it overlaps completely the ohmic contact 18 between the drain zone and the substrate 13. The introduction of the complementary zone 17 makes it possible to increase the distance between the gate zones 12 and 12' and to simplify the process of fabricating integrated circuits of this type since the requirements for the photomask used to form gate zones become less stringent.
The integrated injection circuit (a logical gate) described herein operates as follows.
The emitter zone 2 of the bipolar transistor 1 injects holes into the base zone 4. Thcse holes serve as minority carriers for the zone 4. The charge carriers are collected in the zones 6 and 6'. Depending on the voltage across the input electrodes 7 and 7' the logical gate will occupy one of the following states.
If there is a low, close to the "ground", voltage appled to both input electrodes 7 and 7', the charge carriers collected at the junctions of the zones 6 and 6' and constituting the current provided by the constant current device will "leak off" to "ground". In this case the output electrode II has no direct-current coupling with the "ground" electrode 5. Now, if the gate is loaded with a similar device (not shown in
Figure 1) the electrode 11 will bear a high voltage equal in magnitude to that which opens the junction between the zones 12, 12' and 9.
This direct-current coupling will be broken in case the section of the substrate 13 located between the electrodes 11 and 5 is overlapped by the space charge layers of the closed junctions between the zones 12, 12' and 9 (the space charge layers are indicated with dashed lines in Figure 3).
In case the input electrodes 7 and 7' are fed with a high voltage exceeding that required to unlock the junctions between zones 12, 12' and 9 a direct-current coupling will appear between the electrodes 11 and 5 while the voltage at the output of the logical gate will drop to a level close to that of the "ground" electrode 5. This direct-current coupling is ensured by reducing the size of the space charge zone of the junctions between the zones 12, 12' and 9 in case the voltage across the input electrodes 7 and 7' becomes higher.
If one of the electrodes 7 or 7' is fed with a low voltage there are two alternatively possible results. The first result will occur when the resistivity of the zone 10 and the distance L between the zones 12 and 12' (Figure 2) are selected so that the width of the space charge layer of the junction between each of the zones 12, 12' and the zone 9 is greater than or equal to, the distance L. The second result will occur when the width of the space charge layer of this junction is less than the distance L. In the first case there will be no direct-current coupling between the electrode 11 and the "ground9 electrode 5 so that a NOR action is obtained. In the second case the direct current coupling is interrupted only when both electrodes 7 and 11 are at a low voltages, so that a NAND action is obtained.
Hence, the logical gate described herein can perform NOR and NAND logical functions depending upon its constructional
Darameters and topology (the magnitude of
L and the resistivity of the zone 10).
The speed of the logical gate is high due to the use of non-injecting rectifying contacts (metal-semiconductor junctions) which serve as the gate zones 12 and 12'
and as the collector zones 6 and 6'. Since there is no injection of minority charge
carriers from the gate zones 12 and 12' there
will be no excess charge in the zone 13.
Hence, when the logical gate switches over from the open state into the closed state the
duration of the transients will be sharply
reduced as compared with devices using
injecting contacts.
The operation of the integrated circuit provided with field-effect transistor as
shown in Figure 6 is as follows. The complementary zone 17 prevents current from flowing from the output electrode 11 to the source zone 9 in the direction orthogonal to the surface of the integrated circuit and makes it flqw along a trajectory parallel to this surface. When a low voltage is applied to the gate zones 12 and 12' the space charge layer will block the current path since the complementary zone 17 completely overlaps the ohmic contact of the drain zone 10. The zone 17 can be either connected to "ground" or fed with a bias voltage form an additional power supply.
The integrated circuit described herein is easy to produce and can be manufactured with the use of planar technology with or without resorting to epitaxial films.
A broad field of functional applications and a high speed of operation make the integrated circuit proposed herein quite useful in the design of large-scale integrated devices having a high packing density of components on the chip.
WHAT WE CLAIM IS:
1. An integrated injection device which comprises a constant current device and nchannel field-effect transistor having a gate
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (6)
1. An integrated injection device which comprises a constant current device and nchannel field-effect transistor having a gate
including at least one non-injecting rectifying contact connected to the constant current device and to an input electrode of the device, its source grounded and its drain connected to an output electrode of the device, wherein said field effect transistor is cut off when the or one of or all of said noninjecting rectifying contacts is at a potential close to ground potential.
2. An integrated injection device as claimed in claim 1, wherein the field-effect transistor comprises two non-injecting contacts and has an additional complementary input electrode, the second contact being connected to said complementary input electrode.
3. An integrated injection device as claimed in claim 1 or 2, wherein the constant current device is a bipolar transistor having a metal collector which is combined with a gate of said field-effect transistor.
4. An integrated injection device as claimed in claim 1 or 2, wherein the constant current device is a planar bipolar transistor provided with metal gate electrodes located on a masking dielectric layer, the gate zones of the field-effect transistor are located on the surface of the substrate and are arranged as interconnection sections located on unmasked substrate surface areas and protected with a dielectric layer from above, the drain zone being located partly above said dielectric layer and extending therethrough to form an ohmic contact with the substrate at the area which is overlapped by space charge areas of the rectifying contacts of the gate zones
5. An integrated injection device as claim in claim 4, wherein the substrate is provided with a complementary zone of the conductivity type opposite to that of the substrate, the complementary zone being located at a distance from the surface which does not exceed the thickness of the space charge layer of the non-injecting gatesource rectifying contact and being arranged so as to overlap completely the ohmic contact between the drain zone and the substrate.
6. An integrated injection device substantially as hereinbefore described with reference to the accompanying drawings.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SU772441385A SU602055A1 (en) | 1977-01-06 | 1977-01-06 | Integral logic element |
| SU772537101A SU646391A1 (en) | 1977-11-01 | 1977-11-01 | Field-effect transistor |
| SU2537006 | 1977-11-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1565918A true GB1565918A (en) | 1980-04-23 |
Family
ID=27356306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB39578A Expired GB1565918A (en) | 1977-01-06 | 1978-01-05 | Integrated injection circiut devices |
Country Status (9)
| Country | Link |
|---|---|
| JP (1) | JPS53108291A (en) |
| CH (1) | CH616276A5 (en) |
| CS (1) | CS199407B1 (en) |
| DD (1) | DD136907A1 (en) |
| DE (1) | DE2800335A1 (en) |
| FR (1) | FR2377123A1 (en) |
| GB (1) | GB1565918A (en) |
| NL (1) | NL7800046A (en) |
| PL (1) | PL119495B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2130790A (en) * | 1982-10-26 | 1984-06-06 | Plessey Co Plc | Integrated injection logic device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5540051A (en) * | 1978-09-12 | 1980-03-21 | Mitsubishi Electric Corp | T-joint and production thereof |
| JPS573651Y2 (en) * | 1979-10-08 | 1982-01-22 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2321796C2 (en) * | 1973-04-30 | 1982-07-29 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Field effect transistor |
| JPS5811102B2 (en) * | 1975-12-09 | 1983-03-01 | ザイダンホウジン ハンドウタイケンキユウシンコウカイ | semiconductor integrated circuit |
-
1977
- 1977-12-29 CS CS900577A patent/CS199407B1/en unknown
-
1978
- 1978-01-02 NL NL7800046A patent/NL7800046A/en not_active Application Discontinuation
- 1978-01-04 DD DD20309578A patent/DD136907A1/en unknown
- 1978-01-04 DE DE19782800335 patent/DE2800335A1/en not_active Ceased
- 1978-01-04 CH CH9178A patent/CH616276A5/en not_active IP Right Cessation
- 1978-01-05 FR FR7800244A patent/FR2377123A1/en active Granted
- 1978-01-05 GB GB39578A patent/GB1565918A/en not_active Expired
- 1978-01-05 PL PL20382778A patent/PL119495B1/en unknown
- 1978-01-06 JP JP48078A patent/JPS53108291A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2130790A (en) * | 1982-10-26 | 1984-06-06 | Plessey Co Plc | Integrated injection logic device |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2377123A1 (en) | 1978-08-04 |
| PL119495B1 (en) | 1982-01-30 |
| CH616276A5 (en) | 1980-03-14 |
| NL7800046A (en) | 1978-07-10 |
| PL203827A1 (en) | 1978-10-23 |
| DE2800335A1 (en) | 1978-07-13 |
| DD136907A1 (en) | 1979-08-01 |
| CS199407B1 (en) | 1980-07-31 |
| FR2377123B1 (en) | 1980-05-16 |
| JPS53108291A (en) | 1978-09-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR0175277B1 (en) | Apparatus and method for manufacturing power semiconductor device with a folding fieldplate structure | |
| US3955210A (en) | Elimination of SCR structure | |
| KR100203054B1 (en) | Electrostatic protecting apparatus | |
| US3469155A (en) | Punch-through means integrated with mos type devices for protection against insulation layer breakdown | |
| US3114867A (en) | Unipolar transistors and assemblies therefor | |
| KR950030309A (en) | Protection circuit of semiconductor device | |
| US4810906A (en) | Vertical inverter circuit | |
| US4797724A (en) | Reducing bipolar parasitic effects in IGFET devices | |
| EP0396553B1 (en) | Integrated circuit with anti ''latch-up'' circuit obtained using complementary mos circuit technology | |
| JPH04332173A (en) | Planar type semiconductor device and its manufacture | |
| KR100194496B1 (en) | Semiconductor devices | |
| US3798512A (en) | Fet device with guard ring and fabrication method therefor | |
| US5323041A (en) | High-breakdown-voltage semiconductor element | |
| US5714783A (en) | Field-effect transistor | |
| CN100505260C (en) | Protecting element and semiconductor device using the same | |
| GB1565918A (en) | Integrated injection circiut devices | |
| KR0136595B1 (en) | Integrated circuit with anti-latch-up circuit in complementary mos circuit technology | |
| US4404579A (en) | Semiconductor device having reduced capacitance and method of fabrication thereof | |
| US4243895A (en) | Integrated injection circuit | |
| JPS5921170B2 (en) | MOS type semiconductor device | |
| EP0812020A2 (en) | Field effect transisor with reduced delay variation | |
| US3600648A (en) | Semiconductor electrical translating device | |
| US6512663B1 (en) | Electrostatic protection device and electrostatic protection circuit | |
| GB1569726A (en) | Planar-type semiconductor device | |
| Lin et al. | Shielded silicon gate complementary MOS integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PCNP | Patent ceased through non-payment of renewal fee |