GB1569726A

GB1569726A - Planar-type semiconductor device

Info

Publication number: GB1569726A
Application number: GB2277978A
Authority: GB
Original assignee: ATES Componenti Elettronici SpA; SGS ATES Componenti Elettronici SpA
Current assignee: STMicroelectronics SRL
Priority date: 1977-05-30
Filing date: 1978-05-25
Publication date: 1980-06-18
Also published as: IT1085486B; FR2393423B1; FR2393423A1; DE2823629A1; DE2823629C2

Description

(54) A PLANAR-TYPE SEMICONDUCTOR DEVICE (71) We, SGS-ATES COMPONENTI ELETTRONICI S.p.A., an Italian Company, of 2 Via C. Olivetti, Agrate-Brianza, 20041, Milton, Italy, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: - The present invention relates to planarjunction semiconductor devices, more particularly to monolithic integrated circuits operating at relatively high voltages.

It is known that a negligible current passes through a reverse biased PN junction. However, if the voltage applied thereto reaches a given value (avalanche or breakdown voltage) suddenly a high current flows through the junction. Such a value mainly depends on impurity concentrations in regions of opposite conductivity which form the junction, since such concentrations govern the thickness of the layer deprived of mobile charges (depletion layer) which is formed at the sides of the junction when the latter is reversed biased. The fixed charges of the depletion layer, which are positive in the N-type region and negative in the P-type region generate through the junction an electric field whose intensity increases with the applied voltage up to a value at which breakdown of the junction occurs. It has been found that the distribution of the fixed charges in proximity of the edges of the junction, i.e.

along the line at which the junction intersects the surface of the semiconductor, is modified by external charges possibly present in the immediate vicinity of the surface. This phenomenon is particularly prevalent in the case of planar junctions, i.e.

those junctions the edges of which intersect the surface of the semi-conductor in a plane. For example, disturbing charges are normally present to a minimum but still not negligible extent in the insulating layer covering the surface of the semi-conductor.

Such charges have the effect of restricting at the surface the depletion layer and thus of reducing the breakdown voltage, or in any case of altering the characteristics of the reverse bias junction.

Should the external charges be due to the presence of a metal biased element, the distribution of the charges in the depletion layer is modified in various ways depending on the bias sign and value. Although advantage can be taken of such a phenomenon in designing a number of semi-conductor devices, for example integrated circuits of metal-insulation-semi-conductor (MIS) type, undesired effects may be caused in other types of device, i.e. planar monolithic integrated circuits with bipolar components.

In this case most of the metal strips connecting the various components inevitably pass over at least one junction on the insulating layer covering the surface of the semi-conductor, thereby altering to a greater or lesser extent the distribution of the surface charges in the semi-conductor and thus the electrical characteristics of the junctions. The disturbing effect of the biased connecting strips increases when the temperature of the device rises, during operation, to relatively high values (100 to 150"C). At these temperatures, surface conduction phenomena take place on the insulating layer and have the effect of making the effective dimensions of the strips larger than the actual ones. In this case the disturbing effect on the junction can of course be also caused by the connection strips which do not actually cross the intersection line of the junction but pass close to it. In some cases charge migration into the insulating layer can also be caused by a potential difference between surfaces in different regions of the semi-conductor.

It is known how to protect a planar junction from external electrostatic fields to improve the operational characteristics at high reverse voltage by arranging on the insulating layer covering the surface of the semi-conductor a metal shield which is in electric contact with one of the regions forming the junction and projects onto the other region beyond the edge of the junction so as to overlap at least that part of the depletion layer which extends in the latter region. Such a shield is quite effective when closed, i.e. when it overlaps the edge of the junction over its entire length.

Its application therefore is relatively simple in the case of discrete components in which connections between active zones and terminals of the device are established by means of terminals which depart almost perpendicularly from the surface of the semiconductor, but gives rise to considerable difficulty in the case of components of an integrated circuit owing to the presence of the interconnecting metal strips. The only method known at present for producing a continuous shield for the edge of a planar junction inside an integrated circuit is a metallization process designed to produce two superimposed metal layers separated from each other by an insulating layer. However, although this process can be theoretically carried out, in practice it is very difficult to carry out.

An object of the present invention is to provide a semi-conductor device with planar junctions protected against external electrostatic charges using conventional production processes.

According to the present invention there is provided a planar-type semiconductor device comprising a substrate of monocrystalline semiconductor material in which at least one first region of a first type of conductivity and a second region of a second type of conductivity are formed, the second region being adjacent to the first region so as to form a junction which intersects a major surface of the substrate along an endless line, a layer of insulating material which covers the said major surface at least in the vicinity of the endless line, and means which generates a disturbing electrical charge distribution over the insulating layer above the endless line, at least a shield of polycrystalline semiconductor material of the first type of conductivity having a first portion in contact with the first region through an opening in the insulating layer, and a second portion incorporated in the insulating layer which extends parallel to the surface while projecting over the second region above the intersection line of the junction over its entire length.

Preferably, a multiplicity of regions of the second type of conductivity are separated from one another by relatively narrow regions of the first type of conductivity, the shields of the junctions between the relatively narrow regions and the regions adjacent thereto being formed in a single piece.

An embodiment of this invention will now be described by way of example, with reference to the accompanying drawings, in which: Figures 1 and 2 show partial cross-sectional views, on an enlarged scale, of conventional semiconductor devices to show the operation of a planar junction; Fig. 3 is a diagram illustrating an electric characteristic of the junction of Fig. 2; and Fig. 4 is an enlarged cross-sectional view of a portion of an integrated structure having a planar shielded junction in accordance with the invention.

With reference to Fig. 1, a substrate 10 of a monocrystalline semiconductor material, e.g. silicon, doped with N-type impurities has a P-type region 12 produced by conventional masking and diffusion methods, and forms with it a planar junction 14.

The surface 15 of the semiconductor is covered by a layer 16 of insulating material, preferably silicon dioxide. When the junction is reverse biased by means of suitable connections, not shown, a depletion layer is formed which extends to a greater extent into the less doped region, i.e. the N-type region in the example shown. The limits of such a layer can be generally represented by surfaces parallel to the junctions, as illustrated by dashed lines 18 in Fig. 1. In practice however both the thickness and the shape of the depletion layer are modified in the vicinity of the surface for a number of reasons such as surface deformation of the crystalline lattice, ionic and molecular charges present in the insulating layer 16, and concentrations of external charges of any other nature, and thus the course of the lines 18, especially in the vicinity of the surface 15, should be considered as purely indicative.

Fig. 2 shows a structure which differs from that of Fig. 1 only because of the presence of a metal strip 20 extending on the insulating layer 16 above the intersection line between the junction 14 and the surface 15 of the semi-conductor. The metal strip 20 is at a potential of the same sign as that applied to the region 10. As one can show both experimentally and theoretically, positive charges of the metal layer cause the formation, in the vicinity of the surface oF the N-type material, of a zone termed accumulation channel having an excess of electrons, and of a zone termed depletion channel lacking in holes in the vicinity of the surface of the P-type material. Thus, for a given value of the poten tial of the metal strip 20 the thickness of the depletion layer near to the surface will be considerably reduced as indicated by dashed lines 22 in Fig. 2. The reverse characteristic I=f(V) of the diode formed by the junction of Fig. 2 will have the course shown by the diagram of Fig. 3. For a given relatively low value BVl of the voltage, localised break-down will occur in the surface region of the junction. By increasing the reverse junction, a saturation condition will be reached in this zone, which corresponds to a reverse current Il flowing therethrough until at a voltage BV2 the portion of the junction inside the mass of the semi-conductor breaks down. In a number of applications losses associated with the surface breakdown of the junction are not acceptable, and thus, when possible, an electrostatic shield of the type described in the introduction is adopted which overlaps the entire edge of the junction. As already mentioned above, this is not possible with conventional methods in t1 case of a planar monolithic integrated circuit.

We shall now consider an embodiment of the invention. In accordance with a conventional method, a planar monolithic circuit, an enlarged cross-section of which is shown in Fig. 4, comprises a silicon substrate 30 of P-type on which an epitaxial layer 32 of N-type is formed. The layer 32 is sub-divided into regions separated from one another by insulating channels 34 (only one of which is shown in the drawing) which are obtained by diffusing impurities of P-type into the epitaxial layer 32 to reach the region P in the substrate 30.

Inside the insulated regions the components of the integrated circuit are formed by masking and diffusing operations. Fig.

4 shows the structure of a NPN transistor having as its collector a portion 36 of the epitaxial layer 32, as its base a P-type region 38 diffused in the collector region and as its emitter a N-type region 40 diffused in the base region. A layer 42 of silicon dioxide covers the surface 44 of the semi-conductor material while leaving only three areas 41, 43, 45 uncovered for the contacts of the emitter E, base B and collector C, respectively. Metal elements 46, 48 and 50, for example produced by a conventional method of evaporation under vacuum, pass through the oxide to reach contact areas extending above the oxide and being in the form of strips to reach other metal connection elements of the integrated circuit. It should be noted that before forming the metal connections, the surface resistivity of the zone 47 below the contact area of the collector is decreased by diffusing N-type impurities in it. Such enriched zone is indicated by N+.

As shown in Fig. 4, the strip of the collector 50 extends above the insulation channel 34. Since the collector of an NPN transistor is normally biased by a positive voltage with respect to the sub-layer, the insulation junction between the channel 34 and the collector region 36 would have a depletion layer similar to that indicated by dashed lines in Fig. 2. To avoid alteration in the reverse characteristic of the junction shown in Fig. 3, the inventoin provides an electrostatic shield 52 consisting of polycrystalline P-type silicon having a portion 54 in contact with the channel 34 and a portion 56 completely embedded in the layer 42 of silicon dioxide and overlapping the edge of the channel-collector junction along its entire length. Owing to the present of the shield 52, the depletion layer of the junction will have an enlargement at the surface 44 as shown by dashed lines 57, whereby the breakdown voltage will be determined only by the physical characteristics of the material.

The shield 52 is formed after the diffusion phase of the insulating channel 34 when the surface of the semi-conductor is covered by an insulating layer delimited by a dashed line 58 in Fig. 4, consisting of silicon dioxide formed by thermal growing.

After having uncovered by etching an area 59 of suitable dimensions on the surface of the channel 34, preferably along its entire length, a polycrystalline silicon layer is formed by means of a conventional process, e.g. by deposition at low temperature in a silane atmosphere. The polycrystalline silicon is then selectively removed by means of conventional masking and etching methods so as to obtain the shield 52 having a desired configuration. In particular, the portion 56 is dimensioned in such a way as to project onto the collector region 36 to cover at least the entire depletion region. By subsequent processing operations (base and emitter diffusions) the shield 52 is covered, still by thermal growth, by a layer of silicon dioxide. During designing to determine the thickness of the polycrystalline layer to be deposited, one should take into account that silicon dioxide is formed at the expense of silicon contained in the lower surface and thus the shield 52 is likely to be thinned.

In the above described and illustrated embodiment no account has been taken of the disturbing effect due bo electrostatic charges present in the silicon dioxide layer 42 for this effect is negligible with respect to that due to the metal strip 50. Obviously, the shield 52 also protects the junction from these charges. Moreover, its function remains unaltered even if the disturbing field is not generated by a metal strip extending above the junction edge but by charges induced in the insulating layer by surface heat effect.

Although only one embodiment has been illustrated and described above, numerous variants and modifications can of course be made without departing from the scope of the invention. For example, the shied 52 can be formed so as to have another part similar to the part 56 projecting over the other junction of the channel when the latter is to be protected against effects of outer electrostatic fields.

WHAT WE CLAIM IS: 1. A planar-type semiconductor device comprising a substrate of monocrystalline semiconductor material in which at least one first region of a first type of conductivity and a second region of a second type of conductivity are formed, the second region being adjacent to the first region so as to form a junction which intersects a major surface of the substrate along an endless line, a layer of insulating material which covers the said major surface at least in the vicinity of the endless line, and means which generates a disturbing electrical charge distribution over the insulating layer above the endless line, at least a shield of polycrystalline semiconductor material of the first type of conductivity having a first portion in contact with the first region through an opening in the insulating layer, and a second portion incorporated in the insulating layer which extends parallel to the surface while projecting over the second region above the intersection line of the junction over its entire length.

2. A semiconductor device as claimed in claim 1, in which the multiplicity of regions of the second type of conductivity are separated from one another by relatively narrow regions of the first type of conductivity, the shields of the junctions between the relatively narrow regions and the regions adjacent thereto being formed in a single piece.

3. A planar-type semiconductor device substantially as hereinbefore described with reference to the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. by charges induced in the insulating layer by surface heat effect. Although only one embodiment has been illustrated and described above, numerous variants and modifications can of course be made without departing from the scope of the invention. For example, the shied 52 can be formed so as to have another part similar to the part 56 projecting over the other junction of the channel when the latter is to be protected against effects of outer electrostatic fields. WHAT WE CLAIM IS:

1. A planar-type semiconductor device comprising a substrate of monocrystalline semiconductor material in which at least one first region of a first type of conductivity and a second region of a second type of conductivity are formed, the second region being adjacent to the first region so as to form a junction which intersects a major surface of the substrate along an endless line, a layer of insulating material which covers the said major surface at least in the vicinity of the endless line, and means which generates a disturbing electrical charge distribution over the insulating layer above the endless line, at least a shield of polycrystalline semiconductor material of the first type of conductivity having a first portion in contact with the first region through an opening in the insulating layer, and a second portion incorporated in the insulating layer which extends parallel to the surface while projecting over the second region above the intersection line of the junction over its entire length.