CN2909520Y - Chip packing structure and chip array block for prolonging tin-ball service life - Google Patents
Chip packing structure and chip array block for prolonging tin-ball service life Download PDFInfo
- Publication number
- CN2909520Y CN2909520Y CNU2006200031034U CN200620003103U CN2909520Y CN 2909520 Y CN2909520 Y CN 2909520Y CN U2006200031034 U CNU2006200031034 U CN U2006200031034U CN 200620003103 U CN200620003103 U CN 200620003103U CN 2909520 Y CN2909520 Y CN 2909520Y
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- chip
- modulus
- young
- sticky material
- tin ball
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A chip packaging structure and a chip array block for prolonging the service lives of tin balls, relating to a packaging structure, used in packaging structure design at the time of a temperature cycling test for measuring the motherboard stratum level. The chip packaging structure comprises a base plate, a chip arranged on the first surface of the base plate, a chip sticky material arranged on the first surface and between the first surface and the chip, and a plastic sealing material coating the chip and the first surface, wherein the chip circuit face can be turned up or down. The chip packaging structure and the chip array block coat the chip sticky material on the part of the base plate surface not covered by the chip through increasing the area occupied by a chip sticky material having a relatively low Young's modulus, and reduce tin ball break and prolong the service life of the tin ball through making use of the chip sticky material having a relatively low Young's modulus to absorb the unmatched thermal stress generated during the temperature cycling test, thereby increasing the reliability of the motherboard stratum level test.
Description
Technical field
The utility model relates to a kind of encapsulating structure, particularly a kind of encapsulating structure design of considering the temperature cycling test of motherboard level.
Background technology
Along with the high development of semiconductor industry, electronic product on the IC circuit elements design towards the development of demand of multiway and multifunction, and at element in appearance also towards light, thin, short, little trend development.Therefore, also face many challenges on encapsulation procedure, problems such as the selecting for use of, encapsulating material increasingly sophisticated such as the design of substrate, slim warpage of packaging assembly distortion, thermal diffusivity and structural strength all are to encapsulate industry at present to meet with the difficult problem that anxious desire solves.
Figure 1 shows that the schematic front perspective view of the FBGA-BOC (Board-On-Chip) of prior art.With the one chip packaging body is example, groove 110 is set on the substrate 100, and has sticker coating scope 112 on the substrate 100, chip then is arranged on the sticker coating scope 112,114 in tin ball is distributed in the sticker coating scope 112, also might exceed outside the sticker scope.With reference to Fig. 2, generally speaking, after so encapsulating structure 120 sets up chip and capsulation material, the tin ball 114 of this encapsulating structure 120 can be soldered on the motherboard 130 (board), carry out the temperature cycling test (board T/C testing) of high temperature and low temperature conversion, encapsulating structure 120 each material and motherboard 130 are because the unmatched problem of material coefficient of thermal expansion coefficient is easy to generate thermal stress in the test.Tin ball 114 is the most fragile because of material own, thus tin ball 114 to break be the most normal failure mode that runs into.This moment, the resistance value of signal transmission increased, and may cause open circuit (open), even whole component failure.Therefore, how to guarantee that the reliability of tin ball in test is one of very important problem.
Summary of the invention
In order to reduce encapsulating structure unmatched problem of stress when the temperature cycling test of motherboard level, a kind of encapsulating structure is provided, the chip sticky material wire mark scope that die bonding is used extends to the whole base plate surface, can absorb unmatched thermal stress.
The technical solution of the utility model provides a kind of chip-packaging structure that promotes the tin ball life-span, wherein comprises: a substrate has the opposition side that a first surface and a second surface lay respectively at substrate; One chip is positioned at first surface; One chip sticky material is distributed on the whole first surface of substrate; And a capsulation material coating chip and a first surface, the young's modulus of its chips sticky material is less than the young's modulus of chip.
The technical solution of the utility model provides a kind of chip array block that promotes the tin ball life-span, and a plurality of chip arrays compartment of terrain is distributed on the substrate, wherein compartment of terrain a plurality of chips that distribute in each chip array; And a chip sticky material is positioned on the whole base plate.
The chip array block in above-mentioned lifting tin ball life-span, the young's modulus of its chips sticky material is less than the young's modulus of substrate.
The chip array block in above-mentioned lifting tin ball life-span, the young's modulus of its chips sticky material is less than the young's modulus of arbitrary chip.
The chip array block in above-mentioned lifting tin ball life-span, wherein substrate is a BGA Package support plate.
The chip array block in above-mentioned lifting tin ball life-span, the young's modulus of its chips sticky material is less than the young's modulus of this capsulation material.
The utility model has following beneficial effect compared to prior art: the utility model utilizes the less chip sticky material of young's modulus to be distributed in the encapsulating structure, uses the absorption thermal stress, and the problem that so can reduce the tin ball fractured produces.
Description of drawings
Figure 1 shows that the schematic front perspective view of the chip-packaging structure of existing WBGA embodiment;
Figure 2 shows that the sample side schematic construction of general motherboard level temperature cycling test;
Figure 3 shows that schematic front perspective view according to the chip array block of an embodiment of the present utility model;
Figure 4 shows that according to the circuit surface of an embodiment of the present utility model side schematic view towards lower chip packaging structure;
Figure 5 shows that according to the circuit surface of another embodiment of the present utility model side schematic view of chip-packaging structure up.
Embodiment
Figure 3 shows that schematic front perspective view according to the chip array block of an embodiment of the present utility model.A plurality of chip arrays 12 compartment of terrains are distributed on the support plate 5, wherein compartment of terrain a plurality of chips 14 that distribute in each chip array 12.In one embodiment, substrate 10 has a plurality of groove 16 corresponding each chip array 12, and the arbitrary at least chip 14 of each groove 16 correspondence is used when providing chip 14 to be electrically connected.Secondly, chip sticky material 18 also can be distributed between wantonly two chips 14 of each chip array 12 between chip 14 and substrate 10.In other words, a part of 18a and the chip 14 of chip sticky material 18 are overlapping, promptly are positioned at the below of chip 14, the surface that another part 18b of chip sticky material 18 then exposes between the chip 14 in each chip array 12.Understandable, the chip array 12 on the substrate 10 can have identical or different number of dies 14, or is positioned at two surfaces of substrate 1o opposition side.Secondly, the chip 14 that is had in the chip array 12 can be identical chip, does not also get rid of the different chip of function or form 14 and places a chip array 12.During general encapsulation procedure, carry out encapsulation procedure with chip array 12, mainly comprise coating (comprise wire mark, some glue or go up the mode of dry film) chip sticky material 18 in chip array 12 scopes, die bonding (die attach), routing, overmolded plastic package material, plant ball and cut then.Figure 4 shows that side schematic view according to the chip-packaging structure of an embodiment of the present utility model.In the chip-packaging structure, chip 14 is positioned on the first surface 101 of substrate 10 with chip sticky material 18, and its chips sticky material 18 is distributed on the first surface 101 and between first surface 101 and chip 14.20 coating chips of capsulation material 14 and first surface 101, wherein the chip sticky material 18 that is exposed by chip 14 is between capsulation material 20 and first surface 101.Moreover the second surface 102 of substrate 10 is positioned at the opposition side of first surface 101, and some conductive pads 22 that distribute on it are not covered by anti-welding lacquer 24, and 26 in tin ball is positioned on the conductive pad 22.Moreover, be example with areolar ball lock array FBGA (fine pitch BGA) or FBGA-BOC (Board On Chip), substrate 10 is provided with groove, and it is positioned at the scope of chip 14, and using provides passage ccontaining conduction connecting line 28.Conduction connecting line 28, for example gold thread is electrically connected the conductive pad 22 of chip 14 to substrate 10.
Can be applicable to the chips wire road surface or chips wire road surface ball grid array structure dress (Die Face Up or Die Face Down down up according to the novel spirit of this use, BGA), when for example being applied to up the encapsulation of chips wire road surface, 18 coatings of chip sticky material (comprise wire mark, the mode of some glue or last dry film) scope not only is the die bonding place, the part that exposes that also comprises first surface 101, as shown in Figure 5, still comprise anti-welding lacquer 24 and the conductive pad 22 that is exposed out on the first surface 101, so when wire mark chip sticky material 18 is on first surface 101, also expose conductive pad 22, will conduct electricity conductive pad 22 on conduction connection gasket 30 that connecting line 28 is electrically connected chips 14 and the first surface 101 with one or multi-channel routing step again.With regard to general material, in the time of in being applied to temperature cycling test, young's modulus, for example less than the chip sticky material 18 of 1000MPa young's modulus less than the other materials in the encapsulating structure, for example (hard material about 200000 arrives 300000MPa to substrate 10, soft substrate plate is approximately less than 15000MPa), chip 14 (100000～150000MPa) or capsulation material 20 (15000～25000MPa), therefore can absorb different materials because of the rising-heat contracting-cold thermal stress that (thermal mismatch) caused that do not match.Thus, can reduce the thermal stress that tin ball 26 is born, reduce the distortion of tin ball 26, increase the life-span of encapsulating structure in motherboard level temperature cycling test, and then promote the reliability of encapsulating products in the motherboard level.
According to above-mentioned, a kind of encapsulating structure of chip, chip are positioned at the first surface of substrate.The chip sticky material is distributed on the first surface and between first surface and chip, capsulation material coating chip and first surface, and wherein the segment chip sticky material is between capsulation material and first surface.When being applied to chip array block (block of die array), a plurality of chip arrays compartment of terrain is distributed on the substrate, compartment of terrain a plurality of chips that distribute in each chip array.The chip sticky material and is distributed between wantonly two chips of each chip array between a plurality of chips and substrate.
Above-described embodiment only is explanation technological thought of the present utility model and characteristics, its purpose makes those of ordinary skills can understand content of the present utility model and is implementing according to this, when not limiting claim scope of the present utility model with this, be that every equalization of doing according to the spirit that this creation disclosed changes or modification, must be encompassed in the claim scope of the present utility model.
Claims (10)
1. chip-packaging structure that promotes the tin ball life-span is characterized in that comprising:
Substrate, it has first surface and second surface, lays respectively at the opposition side of described substrate;
Chip, it is positioned on the described first surface;
The chip sticky material, it is distributed on the described first surface of described substrate and between described first surface and described chip; And
Capsulation material, it coats described chip and described first surface, and wherein the described chip sticky material of part is between described capsulation material and described first surface.
2. the chip-packaging structure in lifting tin ball life-span as claimed in claim 1 is characterized in that the young's modulus of the young's modulus of described chip sticky material less than described chip.
3. the chip-packaging structure in lifting tin ball life-span as claimed in claim 1 is characterized in that the young's modulus of the young's modulus of described chip sticky material less than described substrate.
4. the chip-packaging structure in lifting tin ball life-span as claimed in claim 1 is characterized in that the young's modulus of the young's modulus of described chip sticky material less than described capsulation material.
5. chip array block that promotes the tin ball life-span is characterized in that comprising:
A plurality of chips are distributed on the substrate to its array spacings, wherein compartment of terrain a plurality of chips that distribute in each described chip array; And
The chip sticky material is positioned on the whole base plate.
6. the chip array block in lifting tin ball life-span as claimed in claim 5 is characterized in that the young's modulus of the young's modulus of described chip sticky material less than described substrate.
7. the chip array block in lifting tin ball life-span as claimed in claim 5 is characterized in that the young's modulus of the young's modulus of described chip sticky material less than arbitrary described chip.
8. the chip array block in lifting tin ball life-span as claimed in claim 5 is characterized in that described substrate is the BGA Package support plate.
9. the chip array block in lifting tin ball life-span as claimed in claim 5 is characterised in that also to comprise capsulation material, and it is on described chip array and coat described a plurality of chip.
10. the chip array block in lifting tin ball life-span as claimed in claim 9 is characterized in that the young's modulus of the young's modulus of described chip sticky material less than described capsulation material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006200031034U CN2909520Y (en) | 2006-01-27 | 2006-01-27 | Chip packing structure and chip array block for prolonging tin-ball service life |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006200031034U CN2909520Y (en) | 2006-01-27 | 2006-01-27 | Chip packing structure and chip array block for prolonging tin-ball service life |
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| Publication Number | Publication Date |
|---|---|
| CN2909520Y true CN2909520Y (en) | 2007-06-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNU2006200031034U Expired - Fee Related CN2909520Y (en) | 2006-01-27 | 2006-01-27 | Chip packing structure and chip array block for prolonging tin-ball service life |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104684840A (en) * | 2012-07-31 | 2015-06-03 | 惠普发展公司，有限责任合伙企业 | Device including interposer between semiconductor and substrate |
-
2006
- 2006-01-27 CN CNU2006200031034U patent/CN2909520Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104684840A (en) * | 2012-07-31 | 2015-06-03 | 惠普发展公司，有限责任合伙企业 | Device including interposer between semiconductor and substrate |
| US9686864B2 (en) | 2012-07-31 | 2017-06-20 | Hewlett-Packard Development Company, L.P. | Device including interposer between semiconductor and substrate |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070606 Termination date: 20100301 |