CN2906924Y - High-power integrated circuit encapsulation structure - Google Patents
High-power integrated circuit encapsulation structure Download PDFInfo
- Publication number
- CN2906924Y CN2906924Y CN 200620008445 CN200620008445U CN2906924Y CN 2906924 Y CN2906924 Y CN 2906924Y CN 200620008445 CN200620008445 CN 200620008445 CN 200620008445 U CN200620008445 U CN 200620008445U CN 2906924 Y CN2906924 Y CN 2906924Y
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- pin
- layer
- integrated circuit
- chip
- substrate layer
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Abstract
The utility model relates to a big-power integrated circuit packing structure, comprising a chip (9) packed in a plastic packer (1), a copper alloy pin layer (2) and a copper alloy lining layer (3). The utility model is characterized in that the pin layer (2) and the lining layer (3) are parallel riveted; the pin layer (2) is provided holes (11) for arranging the chip, the bottom of which is provided with pins (4) extending out of the plastic packer (1); the chip (9) is fixed on the lining layer (3) in the chip holes (11) and the pins is connected with the pin layer (2); and cooling fin fixing holes (5) are arranged at the two ends of the lining layer (3). The utility model has the advantages of capacity of packing big-power integrated circuit chip, high heat radiating efficiency, reducing areas of packing body and the copper alloy and saving resource.
Description
Technical field
The utility model relates to a kind of integrated circuit package structure, especially relates to a kind of encapsulating structure of high power integrated ciruit chip.
Background technology
Substrate layer in the traditional integrated circuit package structure and pin layer many places are on same horizontal plane, substrate layer mainly plays bearing integrated IC chip, the effect of pin layer and realization conduction, therefore utilize the heat dispersion of the integrated circuit modules that this encapsulating structure makes to be very restricted, though there is the substrate layer in other encapsulating structure after the bearing integrated chip, to play thermolysis, but this substrate layer extends outside the encapsulating structure, also be equipped with the fixedly fixing hole of usefulness on it simultaneously, therefore cause the area of integrated circuit modules bigger, substrate layer is many again to be made by copper alloy, caused the waste of resource, and the radiating effect of this radiating mode is also bad when the packaged high-power integrated circuit (IC) chip, and the heat that can bear is limited equally.
Summary of the invention
The purpose of this utility model provides and a kind ofly economizes on resources, the high-power integrated circuit encapsulating structure of good heat dissipation effect.
Technical solution of the present utility model is: a kind of high-power integrated circuit encapsulating structure, comprise the chip, copper alloy pin layer and the copper alloy substrate layer that are encapsulated in the plastic-sealed body, the parallel riveted joint of pin layer with substrate layer, the pin layer is provided with the chip perforate, its bottom is provided with extends the outer pin of plastic-sealed body, chip is fixed on the interior substrate layer of this chip perforate, and its pin links to each other with the pin layer, and the two ends of substrate layer are provided with the fin fixing hole.
Pin layer and substrate layer branch are arranged, chip is fixed on the substrate layer, substrate layer is used as heat-conducting layer simultaneously, increased the heat transfer contact area, can manyly dispel the heat faster, can connect external fin by the fin fixing hole on it, the heat that produces in the time of can working integrated circuit (IC) chip fast conducts by the substrate layer of copper alloy.Offer the fin fixing hole, can reduce the substrate layer area, effectively save the copper resource.
As a kind of prioritization scheme, be provided with silver coating with the contacted described substrate layer of described chip, be used for guaranteeing that chip and substrate layer form excellent contact, increase the conductive capability and the capacity of heat transmission.
The two ends of described substrate layer are respectively equipped with louvre, the shape of described louvre can be for prolonging the polygon of described substrate layer middle part to described fin fixing hole direction taper in width, louvre is set can make heat form convection current, accelerate heat radiation, simultaneously can slow down expanding with heat and contract with cold of substrate layer, and the area of minimizing substrate layer, save the copper resource, louvre is arranged to polygon to substrate layer two ends convergent, can make heat in the louvre form convection current and eddy current and conduct to fin fixing hole direction, accelerate the transmission of heat, improve radiating effect.
Described pin layer is provided with the location hole that this pin layer can be fixed on the described plastic-sealed body when plastic packaging, during plastic packaging, the outer muscle that needs to shear pin layer bottom is provided with location hole and can utilizes fixedly pin layer of plastic packaging material to form pin, makes contraposition accurate.
Can fix the jogger hole of this encapsulating structure when described plastic-sealed body outer surface is provided with encapsulation, this encapsulating structure can be fixed on the production line, so that transmit and shear pin.
Extend the outer pin of described plastic-sealed body and be staggered front to back the straight cutting structure that is arranged in indentation in regular turn, can under identical packaging body area, effectively increase the quantity of pin.
The utility model has the advantages that: integrated circuit (IC) chip that can packaged high-power, the radiating efficiency height has reduced the area of packaging body and copper alloy, has saved resource.
Description of drawings
Accompanying drawing 1 is the front view of the utility model embodiment;
Accompanying drawing 2 is the end view of the utility model embodiment;
Accompanying drawing 3 is to encapsulate the preceding pin layer and the structural representation of substrate layer among the utility model embodiment;
Accompanying drawing 4 is the structural representation of the preceding pin layer of encapsulation among the utility model embodiment;
Accompanying drawing 5 is the structural representation of the preceding substrate layer of encapsulation among the utility model embodiment;
Accompanying drawing 6 is to encapsulate the preceding pin layer and the end view of substrate layer among the utility model embodiment;
1, plastic-sealed body, 2, the pin layer, 3, substrate layer, 4, pin, 5, the fin fixing hole, 6, jogger hole, 7, rivet, 8, louvre, 9, chip, 10, location hole, 11, the chip perforate, 12, riveted holes, 13, silver coating.
Embodiment
Embodiment: as illustrated in fig. 1 and 2, a kind of high-power integrated circuit encapsulating structure, comprise the chip 9, copper alloy pin layer 2 and the copper alloy substrate layer 3 that are encapsulated in the plastic-sealed body 1, extend described plastic-sealed body 1 outer pin 4 and be staggered front to back the straight cutting structure that is arranged in indentation in regular turn; Can fix the jogger hole 6 of this encapsulating structure when described plastic-sealed body 1 outer surface is provided with encapsulation, this jogger hole 6 is 4 and is symmetrical arranged; The two ends of substrate layer 3 are provided with fin fixing hole 5.Shown in Fig. 3,4,5 and 6, pin layer 2 before the encapsulation is provided with riveted holes 12, on substrate layer 3, be provided with rivet 7, pin layer 2 and substrate layer 3 parallel riveted joints, pin layer 2 is provided with chip perforate 11, and its bottom is provided with extends the outer pin 4 of plastic-sealed body 1, and chip 9 is fixed on the substrate layer 3 in this chip perforate 11, its pin links to each other with pin layer 2, is provided with silver coating 13 with described chip 9 contacted substrate layers 3; The two ends of described substrate layer 3 are respectively equipped with louvre 8, the polygon of described substrate layer 3 middle parts to described fin fixing hole 5 direction taper in width prolonged in being shaped as of described louvre 8, and for being symmetrical arranged, this louvre also can be used to stationary substrate layer 3 when material loading simultaneously.Described pin layer 2 is provided with the location hole 10 that this pin layer 2 can be fixed on the described plastic-sealed body 1 when plastic packaging, encapsulating structure in the present embodiment is provided with 25 pins, on 21 pins of the 5th pin to the, be respectively equipped with location hole 10, to guarantee to utilize plastic packaging material to fix after the muscle cut-out outside of plastic packaging dress back pin layer.
Claims (7)
1, a kind of high-power integrated circuit encapsulating structure, comprise the chip (9), copper alloy pin layer (2) and the copper alloy substrate layer (3) that are encapsulated in the plastic-sealed body (1), it is characterized in that: described pin layer (2) and the parallel riveted joint of described substrate layer (3), pin layer (2) is provided with chip perforate (11), its bottom is provided with extends the outer pin (4) of described plastic-sealed body (1), described chip (9) is fixed on the interior substrate layer (3) of this chip perforate (11), its pin links to each other with pin layer (2), and the two ends of substrate layer (3) are provided with fin fixing hole (5).
2, high-power integrated circuit encapsulating structure according to claim 1 is characterized in that: be provided with silver coating (13) with the contacted described substrate layer of described chip (9) (3).
3, high-power integrated circuit encapsulating structure according to claim 1 and 2 is characterized in that: the two ends of described substrate layer (3) are respectively equipped with louvre (8).
4, high-power integrated circuit encapsulating structure according to claim 3 is characterized in that: being shaped as along described louvre (8) from described substrate layer (3) middle part to the polygon of described fin fixing hole (5) direction taper in width.
5, high-power integrated circuit encapsulating structure according to claim 3 is characterized in that: described pin layer (2) is provided with the location hole (10) that this pin layer (2) can be fixed on the described plastic-sealed body (1) when plastic packaging.
6, high-power integrated circuit encapsulating structure according to claim 3 is characterized in that: the jogger hole (6) that can fix this encapsulating structure when described plastic-sealed body (1) outer surface is provided with encapsulation.
7, high-power integrated circuit encapsulating structure according to claim 3 is characterized in that: extend the outer pin (4) of described plastic-sealed body (1) and be staggered front to back the straight cutting structure that is arranged in indentation in regular turn.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620008445 CN2906924Y (en) | 2006-03-17 | 2006-03-17 | High-power integrated circuit encapsulation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200620008445 CN2906924Y (en) | 2006-03-17 | 2006-03-17 | High-power integrated circuit encapsulation structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2906924Y true CN2906924Y (en) | 2007-05-30 |
Family
ID=38115568
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200620008445 Expired - Fee Related CN2906924Y (en) | 2006-03-17 | 2006-03-17 | High-power integrated circuit encapsulation structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2906924Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388366B (en) * | 2007-07-26 | 2012-07-11 | 塞米克朗电子有限及两合公司 | High performance semiconductor module with connected substrate carrier and corresponding production method |
-
2006
- 2006-03-17 CN CN 200620008445 patent/CN2906924Y/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388366B (en) * | 2007-07-26 | 2012-07-11 | 塞米克朗电子有限及两合公司 | High performance semiconductor module with connected substrate carrier and corresponding production method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: TOYO SEMICONDUCTOR CO., LTD. Free format text: FORMER OWNER: GENNY INDUSTRIES LTD. Effective date: 20070720 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20070720 Address after: Room 2201A, 22 / f business center, 56 Lei Jie street, Mongkok, Kowloon, Hongkong, China Patentee after: Toyo Semiconductor Ltd Address before: Hongkong hung Hexiang Street No. 1 Harbour Center 1 building 402 room 4 Patentee before: Genny Industries Ltd. |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070530 Termination date: 20110317 |