CN216597562U

CN216597562U - Packaging structure

Info

Publication number: CN216597562U
Application number: CN202123009956.2U
Authority: CN
Inventors: 赵晨; 周南嘉
Original assignee: Hangzhou Silergy Semiconductor Technology Ltd
Current assignee: Hangzhou Silergy Semiconductor Technology Ltd
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2022-05-24
Anticipated expiration: 2031-11-30

Abstract

The utility model discloses a packaging structure, comprising: packaging the chip; and the heat dissipation structure is positioned on the outer surface of the packaging chip, wherein the packaging chip is completely or partially encapsulated by packaging materials, and the heat dissipation structure is completely exposed by the packaging materials. The packaging structure of the utility model fixes the heat dissipation structure on the packaging chip on the basis of not changing the prior process of packaging the chip so as to improve the heat dissipation capability of the packaging chip.

Description

Packaging structure

Technical Field

The utility model relates to the technical field of chip packaging, in particular to a packaging structure.

Background

The power management chip is limited by heat dissipation capacity for a long time, power density and conversion efficiency are further improved, heat conduction of the current power management chip is mostly realized by means of low-thermal-resistance connection between a packaging pin and a PCB (printed circuit board), part of special power-consuming chips can be additionally packaged by a chip packaging external surface mounting radiator to strengthen the heat dissipation effect between the packaged chips and air, and part of complex packaging adopts an internal heat conduction material to expose outside the packaged chip to realize the heat transfer of the internal chip to the air or the external environment such as the PCB.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present invention provides a package structure to increase the heat dissipation capability of a chip without changing the conventional chip packaging process.

According to a first aspect of the present invention, a package structure is provided, which includes: packaging the chip; and the heat dissipation structure is positioned on the outer surface of the packaging chip, wherein the packaging chip is completely or partially encapsulated by packaging materials, and the heat dissipation structure is completely exposed by the packaging materials.

Preferably, the heat dissipation structure is connected with the outer surface of the packaged chip through a sintering process.

Preferably, the heat dissipation structure is a low thermal resistance material.

Preferably, the heat dissipation structure is an integrated structure.

Preferably, the heat dissipation structure is a separate structure.

Preferably, the height of the heat dissipation structure is less than or equal to 1.5 mm.

Preferably, the heat dissipation structure is a metal or ceramic material.

Preferably, the bare chip of the packaged chips is completely encapsulated by the packaging material.

Preferably, at least a back surface of a bare chip in the packaged chips is exposed by the packaging material, the back surface of the bare chip being opposite to the active surface of the bare chip.

Preferably, the heat dissipation structure is located at least on the back side of the bare chip.

Preferably, the larger the exposed outer surface area of the heat dissipation structure is, the better the heat dissipation effect is.

Preferably, the heat dissipation structure is fixed on at least one surface of the packaged chip.

Preferably, the packaged chip includes: a bare chip; an electrode pad on an active surface of the bare chip; an encapsulation material for encapsulating the bare chip and the electrode pad; and the pins are positioned on the lower surface of the packaging material and are electrically connected with the electrode bonding pads.

The utility model discloses a packaging structure, comprising: packaging the chip; and the heat dissipation structure is positioned on the outer surface of the packaging chip, wherein the packaging chip is completely or partially encapsulated by packaging materials, and the heat dissipation structure is completely exposed by the packaging materials. The method for forming the packaging structure fixes the heat dissipation structure on the packaging chip on the basis of not changing the existing technology of packaging the chip or partially adjusting the existing technology of packaging the chip so as to improve the heat dissipation capability of the packaging chip.

Drawings

FIGS. 1a-1f are block diagrams of packaging structures including several different heat dissipation structures according to the present invention;

fig. 2a-2c are cross-sectional views of several different packaged chips in accordance with the present invention.

Detailed Description

The utility model will be described in more detail below with reference to the accompanying drawings. Like components are denoted by like reference numerals throughout the various figures. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. In the following description, numerous specific details of the utility model, such as structure, materials, dimensions, processing techniques and techniques for each component, are set forth in order to provide a more thorough understanding of the utility model. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

Fig. 1a-1f are block diagrams of package structures including several different heat dissipation structures according to the present invention. The packaging structure comprises a packaging chip and a heat dissipation structure positioned on the outer surface of the packaging chip, wherein the heat dissipation structure is connected with the outer surface of the packaging chip through a low-temperature sintering process. The heat dissipation structure can be an integrated structure or a separated structure. The larger the exposed outer surface area of the heat dissipation structure is, the better the heat dissipation effect is.

As shown in fig. 1a, which is a structural diagram of a package structure including a first heat dissipation structure according to the present invention, specifically, the package structure includes a packaged chip 101 and a heat dissipation structure 103 located on an outer surface of the packaged chip 101. The packaged chip is completely or partially encapsulated by packaging materials, and the heat dissipation structure is completely exposed by the packaging materials. The heat dissipation structure 103 is a separate structure, specifically, a plurality of dot structures, for example, a hemisphere structure. The arrangement of the heat dissipation structure 103 on the external surface of the packaged chip is not limited. The heat dissipation structure 103 is fixed on at least one surface of the packaged chip 101, for example, in the present embodiment, the heat dissipation structure 103 is located on the upper surface of the packaged chip 101. Of course, in other embodiments, the heat dissipation structure 103 may also be further located on other surfaces of the packaged chip, for example, side surfaces. The heat dissipation structure 103 may also be located on other surfaces than the surface where the pins 102 of the packaged chip are located, and is not limited herein.

The heat dissipation structure 103 is made of a low thermal resistance material to improve its heat dissipation capability, preferably, the heat dissipation structure 10 is made of a metal or a ceramic material, further preferably, the metal is copper, and the ceramic is AL₂O₃。

The heat dissipation structure 103 is connected to the outer surface of the package chip 101 through a low-temperature sintering process, and of course, may be connected through other processes as long as it can withstand the subsequent mounting processing such as high-temperature reflow soldering of the chip.

The height of the heat dissipation structure 103 is set so as not to affect the appearance of the packaged chip itself and the subsequent mounting and soldering process. In this embodiment, the height of the heat dissipation structure is set to be less than or equal to 1.5mm, and further, the height of the heat dissipation structure 103 is set to be less than or equal to 1 mm.

As shown in fig. 1b, which is a structural diagram of a package structure including a second heat dissipation structure according to the present invention, the heat dissipation structure 203 is a separated pin structure, for example, a cone structure. As shown in fig. 1c, which is a structural diagram of a package structure including a third heat dissipation structure according to the present invention, the heat dissipation structure 303 is a separate columnar structure, for example, a cylindrical structure or a prismatic structure. As shown in fig. 1d, which is a structural diagram of a package structure including a fourth heat dissipation structure of the present invention, the heat dissipation structure 403 is an integrated sheet structure, for example, a rectangular parallelepiped structure. As shown in fig. 1e, which is a structural diagram of a package structure including a fifth heat dissipation structure of the present invention, the heat dissipation structure 503 is a separate wall structure, for example, a rectangular parallelepiped structure. As shown in fig. 1f, which is a structural diagram of a package structure including a sixth heat dissipation structure of the present invention, the heat dissipation structure 603 is an integrated complex structure, for example, a U-shaped wall structure. Other structures of the package structure of fig. 1b-1f are the same as those of fig. 1a, and are not described herein. The package structure is not limited to the structures provided by the present invention, and may be any structure (without affecting the appearance of the packaged chip itself and the subsequent mounting and soldering process), for example, a combination structure of the heat dissipation structures shown in fig. 1d and fig. 1e, or a combination structure of the heat dissipation structures shown in fig. 1d and fig. 1f, that is, a wall structure is formed on the sheet structure or a U-shaped wall structure is formed on the sheet structure, which is not limited herein.

Fig. 2a-2c are cross-sectional views of several different packaged chips in accordance with the present invention. Fig. 2a shows a cross-sectional view of a first packaged chip. The packaged chip includes a bare chip 210, electrode pads 212 on an active surface of the bare chip 210, a packaging material 214, and pins 213. The encapsulation material 214 is used for encapsulating the bare chip 210 and the electrode pad 212; the pins 213 are exposed by the packaging material 214, located on the lower surface of the packaging material 214, and electrically connected to the electrode pads 212.

In the first type of packaged chip, the back side of the die 210 is completely encapsulated by the encapsulant 214, and the back side of the die 210 is opposite to the active side. The heat dissipation structure may be located on the packaging material 214 on the back surface of the bare chip 210, and further, may be located on any surface of the packaging material.

In the first packaged chip shown in fig. 2a, the die 210 is packaged in a flip-chip manner, i.e., the active surface of the die 210 faces downward. In other embodiments, the die 210 may be packaged in a face-up manner, that is, the active surface of the die faces upward, and the electrode pads on the active surface are electrically connected to the pins through the side of the die.

It should be noted that the packaged chips shown in the drawings of the present invention are simplified drawings, which can simply illustrate the problem, and the specific structure in the actual process is complicated and not shown here. However, modifications made to the drawings or the same structures as the simplified drawings of the present invention are within the scope of the present invention.

Fig. 2b shows a cross-sectional view of a second packaged chip. The second type of packaged chip has substantially the same structure as the first type of packaged chip, and is not described herein again, except that the bare chip 310 of the second type of packaged chip is packaged in an inverted manner, and the back surface of the bare chip 310 is exposed by the packaging material 314. The upper surface of the encapsulant 314 is flush with the back surface of the die 310. In this structure, the heat dissipation structure may be at least directly located on the back surface of the bare chip, so as to further improve the heat dissipation capability.

Fig. 2c is a cross-sectional view of a third packaged chip. The third type of packaged chip has substantially the same structure as the first type of packaged chip, and is not described herein again, except that the bare chip 410 of the third type of packaged chip is packaged in a flip-chip manner, and the back surface of the bare chip 410 is exposed by the packaging material 414. A portion of the upper surface of the encapsulation material 414 is removed to expose the back surface of the die 410, i.e., the upper surface of the portion of the encapsulation material 414 encapsulating the sides of the die 410 is higher than the back surface of the die 410. In this structure, the heat dissipation structure may be at least directly located on the back surface of the bare chip, so as to further improve the heat dissipation capability.

Of course, in other embodiments, the upper surface of the encapsulation material 414 may be lower than the back surface of the bare chip 410, that is, a part of the side surface of the bare chip 410 is also exposed by the encapsulation material 414.

The packaging structure provided by the utility model can directly form an additional fixed heat dissipation structure on the packaging surface of the existing chip under the condition of not changing the current packaging chip manufacturing process flow and adjusting part of the current traditional packaging manufacturing process flow links, thereby realizing the heat conduction from the surface or the interior of the packaging chip to the external environment and reducing the working temperature of the chip.

While embodiments in accordance with the utility model have been described above, these embodiments are not intended to be exhaustive or to limit the utility model to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the utility model and the practical application, to thereby enable others skilled in the art to best utilize the utility model and various embodiments with various modifications as are suited to the particular use contemplated. The utility model is limited only by the claims and their full scope and equivalents.

Claims

1. A package structure, comprising:

packaging the chip;

a heat dissipation structure located on an outer surface of the packaged chip,

the packaged chip is completely or partially encapsulated by packaging materials, and the heat dissipation structure is completely exposed by the packaging materials.

2. The package structure of claim 1, wherein the heat spreading structure is coupled to the external surface of the packaged chip by a sintering process.

3. The package structure of claim 1, wherein the heat dissipation structure is a low thermal resistance material.

4. The package structure of claim 1, wherein the heat dissipation structure is a unitary structure.

5. The package structure of claim 1, wherein the heat dissipation structure is a discrete structure.

6. The package structure of claim 1, wherein the height of the heat spreading structure is less than or equal to 1.5 mm.

7. The package structure of claim 1, wherein the heat dissipation structure is a metal or ceramic material.

8. The package structure of claim 1, wherein a bare chip of the packaged chips is completely encapsulated by the packaging material.

9. The package structure of claim 1, wherein a back side of a die in the packaged die is at least exposed by the packaging material, the back side of the die being opposite the active side of the die.

10. The package structure of claim 9, wherein the heat spreading structure is located at least on the die backside.

11. The package structure of claim 1, wherein the larger the exposed outer surface area of the heat dissipation structure, the better the heat dissipation effect of the heat dissipation structure.

12. The package structure of claim 1, wherein the heat dissipation structure is fixed on at least one surface of the packaged chip.

13. The package structure of claim 1, wherein the packaged chip comprises:

a bare chip;

an electrode pad on an active surface of the bare chip;

an encapsulation material for encapsulating the bare chip and the electrode pad; and

and the pins are positioned on the lower surface of the packaging material and are electrically connected with the electrode bonding pads.