CN216015347U - Device packaging structure and assembly - Google Patents

Device packaging structure and assembly Download PDF

Info

Publication number
CN216015347U
CN216015347U CN202122560167.1U CN202122560167U CN216015347U CN 216015347 U CN216015347 U CN 216015347U CN 202122560167 U CN202122560167 U CN 202122560167U CN 216015347 U CN216015347 U CN 216015347U
Authority
CN
China
Prior art keywords
pin
pins
device package
chip
heat sink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202122560167.1U
Other languages
Chinese (zh)
Inventor
徐洋
王其龙
施嘉颖
杨凯峰
顾红霞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JIANGSU JIEJIE MICROELECTRONICS CO Ltd
Original Assignee
JIANGSU JIEJIE MICROELECTRONICS CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JIANGSU JIEJIE MICROELECTRONICS CO Ltd filed Critical JIANGSU JIEJIE MICROELECTRONICS CO Ltd
Priority to CN202122560167.1U priority Critical patent/CN216015347U/en
Application granted granted Critical
Publication of CN216015347U publication Critical patent/CN216015347U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

The application provides a device packaging structure and a component, and relates to the technical field of device packaging. The device packaging structure comprises a radiating fin, a chip, pins, first connecting ribs and binding lines, wherein the chip is arranged on the radiating fin, the first connecting ribs are respectively connected with the radiating fin and the pins, and the chip is electrically connected with the pins through the binding lines; wherein, the heat sink and the pin are arranged at intervals. The device packaging structure and the component have the effects of reducing the occupied area of the radiating fin, avoiding solder pollution and improving bonding quality and flexibility.

Description

Device packaging structure and assembly
Technical Field
The application relates to the technical field of device packaging, in particular to a device packaging structure and a component.
Background
In recent years, with rapid development of semiconductor technology and breakthrough of material growth technology, gallium nitride (GaN) has gradually shown its advantages as a third-generation semiconductor, such as high two-dimensional electron gas density and high saturation electron mobility, and research based on gallium nitride (GaN) has been increasing. Meanwhile, the GaN HEMT device has achieved certain performance in the application fields of semiconductor illumination, power devices, microwave devices, photovoltaic cells and the like.
The lead frame, one of the main materials constituting the packaged device, plays an important role as a physical structural support and an electrical connection bridge. At present, the universal lead frame structure mainly comprises a radiating fin part and a pin part, wherein the radiating fin is a main body for carrying a chip and is used as a medium for heat transfer between the chip and the external environment, and the pin is electrically connected with an electrode of the chip through a binding line.
Referring to the conventional packaging method of power semiconductor, the lead frame is usually designed by directly connecting one of the pole pins to the heat sink (i.e., the die pad). The design concept conforms to the structure of the different surfaces of the electrodes of the chip, and the chip is attached to the chip-mounted substrate island through conductive adhesive or silver paste, namely the chip is interconnected with one electrode in the pin. Meanwhile, the source area on the front side of the chip is connected with the rest pins through binding lines. By the method, a complete electric loop can be obtained.
However, the above approach is not well suited for GaN HEMT devices. Due to the special electrode coplanar structure, all active areas are distributed on the front surface of the chip. The pin connection of a certain source region cannot be obtained by simply mounting the chip on the frame base island. Meaning that the technician performs the wire binding process for all source regions on the front side. If a lead frame with a structure in which a heat sink is directly connected to one pole of a pin is still used, one pole of the chip source region needs to be bonded to a heat sink base plate. However, in the chip mounting process, a part of the bottom plate area is inevitably sacrificed due to the solder, so that the arrangement of the bonding points is more limited. In addition, some types of solders contain soldering flux, volatile substances can be emitted and attached to the base plate in the high-temperature sintering process, and the quality of the bonding wire can be affected if the soldering flux is not cleaned in subsequent production, so that problems such as insufficient soldering and the like are caused.
In conclusion, the problems that the welding of the pins occupies the area of a heat dissipation base plate, the welding flux pollutes a base island, and the bonding quality is not high exist in the prior art.
SUMMERY OF THE UTILITY MODEL
The application aims to provide a device packaging structure and a device packaging assembly so as to solve the problems that in the prior art, a solder pollutes a pin and bonding quality is not high.
In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:
in a first aspect, an embodiment of the present application provides a device package structure, where the device package structure includes a heat sink, a chip, a pin, a first connecting rib, and a binding line, where the chip is mounted on the heat sink, the first connecting rib is connected to the heat sink and the pin, and the chip is electrically connected to the pin through the binding line; wherein the content of the first and second substances,
the heat radiating fins and the pins are arranged at intervals.
Optionally, the number of the pins is multiple, the device package structure further includes a second connecting rib, and the pins are connected through the second connecting rib.
Optionally, the second connecting rib is further connected with the first connecting rib.
Optionally, the first connecting ribs comprise transverse connecting ribs and vertical connecting ribs, one end of each vertical connecting rib is connected with the top of the corresponding radiating fin, and the other end of each vertical connecting rib is connected with the corresponding transverse connecting rib;
the transverse connecting ribs are also connected with the bottoms of the pins.
Optionally, the vertical connecting ribs comprise first vertical connecting ribs and second vertical connecting ribs, the first ends of the first vertical connecting ribs and the second vertical connecting ribs are connected with the two ends of the radiating fins respectively, and the second ends of the first vertical connecting ribs and the second vertical connecting ribs are connected with the two ends of the transverse connecting ribs respectively.
Optionally, the binding wire is connected with an end of the pin.
Optionally, when the pin and the heat sink are located on the same plane, the first connecting rib is a straight connecting rib;
when the pin and the heat sink are located on the non-same plane, the first connecting rib is provided with a bending part.
Optionally, the first connecting rib comprises a connecting rib body and a first connecting part, and the connecting rib body is connected with the heat sink through the first connecting part;
the connecting rib body and the radiating fins are arranged at intervals.
Optionally, the pin includes a pin body and a second connection portion, and the pin body is connected to the second connection portion; wherein the content of the first and second substances,
the second connecting parts are used for being connected with the binding lines, and the number of the second connecting parts is smaller than or equal to that of the pin bodies.
On the other hand, the embodiment of the application also provides a device packaging assembly, the device packaging assembly comprises a plurality of the device packaging structures, and the device packaging structures are arranged in an array mode.
Compared with the prior art, the method has the following beneficial effects:
the application provides a device packaging structure and a component, the device packaging structure comprises a heat radiating fin, a chip, a pin, a first connecting rib and a binding line, wherein the chip is arranged on the heat radiating fin, the first connecting rib is respectively connected with the heat radiating fin and the pin, and the chip is electrically connected with the pin through the binding line; wherein, the heat sink and the pin are arranged at intervals. On one hand, the first connecting ribs are used for realizing the connection between the heat sink and the pins, so that the packaging structure is relatively stable. On the other hand, the radiating fins and the pins are arranged at intervals, so that pollution caused by solder is avoided, bonding quality is improved, and product reliability is guaranteed. Meanwhile, the pins are all in a floating state, so all the pins are equivalent from the aspect of electrical connection. The chip mounting angle and the bonding scheme can be adjusted at will from the actual application of the product, and the flexibility is higher. In addition, the pins do not occupy the area of the heat dissipation bottom plate because the heat dissipation fins and the pins are arranged at intervals.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic diagram of a package structure provided in the prior art.
Fig. 2 is a schematic structural diagram of a first structure of a device package structure according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a second structure of a device package structure according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of a third structure of a device package structure according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram of a vertical connecting rib provided in an embodiment of the present application.
In the figure:
100-a device package structure; 110-a heat sink; 120-chip; 130-pin; 140-first connecting ribs; 150-a binding line; 160-second connecting rib; 141-a first vertical connecting rib; 142-transverse connecting ribs; 143-second vertical connecting ribs; 144-bending part.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
As described in the background art, the conventional universal lead frame structure mainly includes a heat sink portion and a lead portion, the heat sink is a main body for carrying a chip and is used as a bridge for heat transfer between the chip and the external environment, and the lead is electrically connected to an electrode of the chip through a bonding wire. The radiating fin of the type of package is usually directly connected with one pole of the pin, is suitable for chips with different surfaces of electrodes such as silicon controlled rectifier, diode, MOS and IGBT, takes conductive adhesive or silver paste as an adhesive, and pastes the back surface of the chip on a base island of the radiating fin, and because the radiating fin substrate is interconnected with one pole of the pin, the two can realize electrical intercommunication.
However, it has been found in practice that this package structure is not suitable for GaN HEMT devices. Firstly, the GaN HEMT device belongs to an electrode coplanar chip, and for a packaging process, the back surface of the chip provides a support function on a physical structure. Electrical communication cannot be achieved only by attaching the back of the chip to the heat sink; secondly, in order to solve the above problems, a craftsman can select to connect the front electrode of the chip with the heat dissipation bottom plate through a binding line, thereby indirectly realizing the electrical intercommunication with the pins. On one hand, a certain amount of conductive adhesive or silver paste always overflows from the back of the chip and occupies a part of bonding area; on the other hand, the soldering flux in the conductive adhesive can pollute the chip-mounting substrate island, and if the chip-mounting substrate island cannot be cleaned, the bonding quality can be affected, and the problem of cold joint can exist.
For example, referring to fig. 1, fig. 1 shows a schematic diagram of a device package in the prior art, in which 1 represents a heat sink, 2 represents a lead, 3 represents a conductive paste or silver paste, 4 represents a GaN HEMT chip, and 5 represents a bonding wire. Two devices, each comprising 3 pins, are included in fig. 1, wherein the pin in the middle is connected to the heat sink and the pins on both sides are not connected to the heat sink. In actual operation, the leads at the middle position need to be welded with the heat sink, so that the solder pollutes the substrate island, and the bonding quality is affected.
In view of this, the present application provides a device package structure, which avoids the occurrence of the situation that the solder contaminates the substrate island by disposing the pins and the heat sink at intervals.
The following is an exemplary description of the device package structure provided in the present application:
as an implementation manner, referring to fig. 2, the device package structure 100 includes a heat sink 110, a chip 120, a pin 130, a first connecting rib 140 and a binding line 150, wherein the chip 120 is mounted on the heat sink 110, the first connecting rib 140 is respectively connected to the heat sink 110 and the pin 130, and the chip 120 is electrically connected to the pin 130 through the binding line 150; wherein the heat sink 110 is spaced apart from the pins 130.
By arranging the heat radiating fins 110 and the pins 130 at intervals, the heat radiating fins 110 and the pins 130 do not need to be welded, so that pollution caused by solder is avoided, bonding quality is improved, and product reliability is guaranteed. Meanwhile, the pins 130 are all in a floating state, so all the pins 130 are equivalent from the electrical connection point of view. The chip mounting angle and the bonding scheme can be adjusted at will from the actual application of the product, and the flexibility of the product application is improved.
It should be noted that the chip 120 described herein may be a GaN HEMT chip, and certainly, may also be another chip, which is not limited herein.
The heat sink 110 can mount the chip 120 and transmit the heat of the chip 120 to the outside, but naturally, in order to achieve stable connection between the chip 120 and the heat sink 110, the chip 120 needs to be connected to the heat sink 110 through a connection layer, for example, the connection layer may be a conductive adhesive layer or a silver paste layer.
The binding wire 150 can electrically connect the pin 130 and the chip 120, and thus ensure that the pin 130 and the chip 120 can be connected even though the pin 130 and the heat sink 110 are relatively independent.
The first connection rib 140 can stabilize the pin 130, and ensure that the stability of the device package structure 100 is improved on the premise that the pin 130 and the heat sink 110 are independent.
As an implementation manner, the number of the pins 130 is multiple, and on this basis, in order to ensure the stability of the device package structure 100, the device package structure 100 further includes a second connection rib 160, and the multiple pins 130 are connected through the second connection rib 160. For example, if the number of the leads 130 is 3, the second connecting rib 160 is connected to three leads 130, and the three leads 130 are connected to the first connecting rib 140, so that the stability of the leads 130 is improved.
Of course, in order to further improve the stability of the device package structure 100, the second connection rib 160 is also connected to the first connection rib 140. On this basis, first splice bar 140 is connected between pin 130 and fin 110 as external connection muscle, and second splice bar 160 is connected a plurality of pins 130 as internal connection muscle, simultaneously, is connected between internal connection muscle and the external connection muscle, has advanced one and has promoted the inside and outside stability of whole device packaging structure 100, forms stable frame construction.
In addition, in order to ensure the stability of the whole device packaging structure 100, the vertical connecting ribs include a first vertical connecting rib 141 and a second vertical connecting rib 143, first ends of the first vertical connecting rib 141 and the second vertical connecting rib 143 are respectively connected with two ends of the heat sink 110, and second ends of the first vertical connecting rib 141 and the second vertical connecting rib 143 are respectively connected with two ends of the transverse connecting rib 142.
For example, as shown in fig. 2, the number of the pins 130 includes 3, and 3 pins 130 are located below the heat sink 110, on this basis, the left and right sides of the heat sink 110 are respectively provided with the first vertical connecting rib 141 and the second vertical connecting rib 143, the transverse connecting rib 142 is connected with the end of the pin 130, and the end of the first vertical connecting rib 141 and the end of the second vertical connecting rib 143 located on the left and right sides of the heat sink 110 are respectively connected with the left and right ends of the transverse connecting rib 142, so that the frame structure formed by the first connecting rib 140, the second connecting rib 160 and the pin 130 is integrally of an axisymmetric structure, and the stability of the whole frame structure is ensured.
In addition, in order to achieve miniaturization of the device package structure 100, although the pins 130 are spaced apart from the heat sink 110, they are actually adjacent to each other, for example, the spacing between the pins 130 and the heat sink 110 may be set to be less than 5 mm. Furthermore, the binding line 150 is connected to the end of the pin 130, which not only ensures the electrical connection between the pin 130 and the chip 120, but also ensures the shortest length of the binding line 150.
Moreover, in an alternative implementation, the pin 130 includes a pin 130 body and a second connection portion, and the pin 130 body is connected to the second connection portion; the second connecting portions are used for connecting with the binding wire 150, and the number of the second connecting portions is less than or equal to the number of the pin 130 bodies.
It can be understood that when the number of the second connection parts is equal to the number of the pin 130 bodies, each pin 130 body corresponds to one second connection part, such as the device package structure 100 shown in fig. 2. When the number of the second connection parts is less than the number of the pin 130 bodies, two or more pin 130 bodies share one second connection part, as shown in fig. 3. In fig. 3, each device package structure 100 includes 3 pin 130 bodies and 2 second connection portions, wherein a first pin 130 body from left to right is connected to one second connection portion, and a second pin 130 body and a third pin 130 body are connected to another second connection portion.
Of course, in some other implementations, a manner that 3 or 4 pin 130 bodies share one second connection portion may also be adopted, which is not limited herein.
In addition, the number of the pins 130 is not limited in this application, for example, the number of the pins 130 may be 3, or, as shown in fig. 4, the number of the pins 130 may also be 4, which is not limited herein.
Generally, the device package structure 100 further includes a plastic package body, and after the plastic package body is manufactured, the package is completed, and then a rib cutting and shaping process is performed to remove the connecting rib, so as to achieve miniaturization of the package structure. Since the molding compound has a certain shaping effect on the leads 130, the first connecting ribs 140 can be removed after the encapsulation is completed. As an implementation manner, the first connection rib 140 includes a connection rib body and a first connection portion, the connection rib body is connected to the heat sink 110 through the first connection portion, and the connection rib body and the heat sink 110 are arranged at an interval.
Through this implementation, in the first connecting rib 140, except the position of the first connecting portion, the rest positions are all at a certain distance from the heat dissipation plate 110, and when the first connecting rib 140 is removed, the removal can be more convenient.
In addition, the lead frame may be designed such that the front surface of the heat sink 110 is flush with the front surfaces of the pins 130, or the front surface of the heat sink 110 has a height difference with the front surfaces of the pins 130, according to the actual product requirements. On this basis, when the pins 130 and the heat sink 110 are located on the same plane, the first connecting ribs 140 are straight connecting ribs; when the pin 130 and the heat sink 110 are not located on the same plane, the first connecting rib 140 is provided with a bending portion 144.
For example, when the height difference exists between the pin 130 and the heat sink 110, please refer to fig. 5, the vertical connecting rib includes two portions, the first portion has the same length as the heat sink 110, the second portion has the same length as the pin 130, the two portions are integrally formed, and the bending portion 144 is disposed at the connection position, so that the first portion is horizontal to the heat sink 110, the second portion is horizontal to the pin 130, and the stability of the device package structure 100 is increased.
Based on the foregoing implementation manner, the embodiment of the present application further provides a device package assembly, where the device package assembly includes a plurality of device package structures 100, and the plurality of device package structures 100 are arranged in an array. In the actual manufacturing process, a device package assembly composed of a plurality of device package structures 100 can be manufactured at the same time, and then the device package assembly is split to obtain a plurality of independent device package structures 100.
In summary, the present application provides a device package structure and a component, the device package structure includes a heat sink, a chip, a pin, a first connecting rib, and a binding line, the chip is mounted on the heat sink, the first connecting rib is respectively connected with the heat sink and the pin, and the chip is electrically connected with the pin through the binding line; wherein, the heat sink and the pin are arranged at intervals. On one hand, the first connecting ribs are used for realizing the connection between the heat sink and the pins, so that the packaging structure is relatively stable. On the other hand, the radiating fins and the pins are arranged at intervals, so that pollution caused by solder is avoided, bonding quality is improved, and product reliability is guaranteed. Meanwhile, the pins are all in a floating state, so all the pins are equivalent from the aspect of electrical connection. Can follow product practical application and set for, adjust mounting angle and bonding scheme wantonly, the flexibility is higher to, because fin and pin interval set up, consequently the area of radiating bottom plate can not be taken up to the pin.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims (10)

1. A device packaging structure is characterized by comprising a heat radiating fin, a chip, pins, first connecting ribs and binding lines, wherein the chip is arranged on the heat radiating fin, the first connecting ribs are respectively connected with the heat radiating fin and the pins, and the chip is electrically connected with the pins through the binding lines; wherein the content of the first and second substances,
the heat radiating fins and the pins are arranged at intervals.
2. The device package structure of claim 1, wherein the number of the pins is plural, the device package structure further comprising a second connection rib, the plural pins being connected by the second connection rib.
3. The device package structure of claim 2, wherein the second tie bar is further connected to the first tie bar.
4. The device package structure of claim 1, wherein the first connection rib comprises a transverse connection rib and a vertical connection rib, one end of the vertical connection rib is connected with the top of the heat sink, and the other end of the vertical connection rib is connected with the transverse connection rib;
the transverse connecting ribs are also connected with the bottoms of the pins.
5. The device package structure of claim 4, wherein the vertical connection ribs comprise a first vertical connection rib and a second vertical connection rib, first ends of the first vertical connection rib and the second vertical connection rib are respectively connected with two ends of the heat sink, and second ends of the first vertical connection rib and the second vertical connection rib are respectively connected with two ends of the transverse connection rib.
6. The device package structure of claim 1, wherein the binding wire is connected with an end of the pin.
7. The device package structure of claim 1, wherein the first tie bar is a straight tie bar when the leads and the heat sink are in the same plane;
when the pin and the heat sink are located on the non-same plane, the first connecting rib is provided with a bending part.
8. The device packaging structure of claim 1, wherein the first connection rib comprises a connection rib body and a first connection portion, the connection rib body being connected with the heat sink through the first connection portion;
the connecting rib body and the radiating fins are arranged at intervals.
9. The device package structure of claim 1, wherein the pin comprises a pin body and a second connection portion, the pin body being connected with the second connection portion; wherein the content of the first and second substances,
the second connecting parts are used for being connected with the binding lines, and the number of the second connecting parts is smaller than or equal to that of the pin bodies.
10. A device package assembly comprising a plurality of device package structures according to any of claims 1 to 9, the plurality of device package structures being arranged in an array.
CN202122560167.1U 2021-10-22 2021-10-22 Device packaging structure and assembly Active CN216015347U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202122560167.1U CN216015347U (en) 2021-10-22 2021-10-22 Device packaging structure and assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202122560167.1U CN216015347U (en) 2021-10-22 2021-10-22 Device packaging structure and assembly

Publications (1)

Publication Number Publication Date
CN216015347U true CN216015347U (en) 2022-03-11

Family

ID=80587157

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202122560167.1U Active CN216015347U (en) 2021-10-22 2021-10-22 Device packaging structure and assembly

Country Status (1)

Country Link
CN (1) CN216015347U (en)

Similar Documents

Publication Publication Date Title
CN100362656C (en) Semiconductor die package including drain clip
WO2015043499A1 (en) Semiconductor encapsulation structure and forming method thereof
CN110429075B (en) High-density multi-side pin exposed packaging structure and production method thereof
KR20170086828A (en) Clip -bonded semiconductor chip package using metal bump and the manufacturing method thereof
JP2001196518A (en) Semiconductor device
CN218730911U (en) Double-sided heat dissipation packaging structure with internal insulation
US9666557B2 (en) Small footprint semiconductor package
US9748205B2 (en) Molding type power module
CN216015347U (en) Device packaging structure and assembly
CN216849941U (en) Novel reverse-conducting gallium nitride power device
JP2003037236A (en) Method for manufacturing semiconductor device, and semiconductor device manufactured by the same
CN111082306B (en) Semiconductor laser array and packaging method thereof
CN219917170U (en) Half-bridge module
CN107768326B (en) A kind of silicon carbide power device encapsulating structure
CN102832190B (en) Semiconductor device with flip chip and manufacturing method of semiconductor device
JP2021027211A (en) Electronic device
CN220895497U (en) Semiconductor discrete device with double-sided heat dissipation
TWI244173B (en) Semiconductor chip package structure
CN217768368U (en) SMD SO8J semiconductor chip's packaging structure
CN116705726B (en) Welding-free module packaging structure and double-sided heat dissipation module packaging structure thereof
CN219017645U (en) Packaging structure applied to planar power device
CN213212151U (en) Semiconductor packaging structure
CN220604667U (en) Frameless high-power MOS packaging module and circuit structure
CN220400580U (en) High-efficiency radiating unit type discrete device
CN218333782U (en) Electron cigarette chip foot position heat radiation structure

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant