CN2872468Y

CN2872468Y - Data collecting interface

Info

Publication number: CN2872468Y
Application number: CN 200520009738
Authority: CN
Inventors: 郑洁; 李百战; 串禾
Original assignee: Chongqing University
Current assignee: Chongqing University
Priority date: 2005-08-05
Filing date: 2005-08-05
Publication date: 2007-02-21
Anticipated expiration: 2015-08-05

Abstract

A data collection interface comprises an analog buffer, a high-speed AD converter, a data buffer storage, an address generator, a clock and a control circuit. The analog signals will be output to PC parallel port, after the processing of the analog buffer and sending out orders to the high-speed AD converter. At the same time, the analog signals send out orders to data buffer storage and read/write data after the control circuit and the address generator. The data buffer storage could exchange data with the high-speed AD converter. The control circuit is controlled by the clock circuit and also controls an analog buffer unit and the high-speed AD converter. The utility model has the advantages of concise structure, convenient for system expansion and update, mature technique, reliable performance and lower price.

Description

A kind of data acquisition interface

Technical field

The utility model relates to data acquisition technology, is specifically related to a kind of ultra-high-speed data acquisition interface.

Background technology

Catching data quickly and accurately is bases of Computer Analysis and processing, and it is the very important step that the current application digital technology solves many problems that simulating signal is carried out the digitizing conversion.In the prior art, the hypervelocity data are obtained in the application of aspects such as transient signal analysis, radar, ultrasonic inspection, mass spectrophotometry, high-speed figure storage oscilloscope and Digital Image Processing very extensive.Need handle in the application of high frequency analog signals for some,, just need utilize the high-speed sampling technology that simulating signal is carried out digitized processing in order under certain requirement, to reflect the information of original signal.It is the very important step that the current application digital technology solves many problems that simulating signal is carried out the digitizing conversion.

The A/D of domestic-developed collection at present mainly is low speed, high-precision A/D.As the synchronous 16 bit data acquisition systems of GPS of certain research institute's exploitation, though the sampling precision of this system is higher, the sample frequency that they can reach generally has only 250kHz.Also have Taiwan to specialize in the series data analog input card of company (Adlink) exploitation of data acquisition making, they are referred to as hypervelocity simulating signal input card (Ultra-High Speed Analog Input Cards) these series of products, though it can provide 256 paths, (resolution is 10bit, 12bit) but its sample frequency also has only 20MHz.What external most of company was walked also is low speed, this road of high precision, and as the DAQ-1201 series of products of quatech company, the highest sample frequency that it can reach is 400kHz, and precision is 12bit.The DA500A product of the product of high level such as signatec company, the highest sample frequency have reached 500MHz (resolution also is 8bit), but its employing is the system platform of PCI structure.Also have the more special application of a class in like product, that is exactly the data sampling technology in the digital oscilloscope, and sample frequency can reach tens GHz during this type of was used.But this class all is to have adopted the special ASIC chip technology in using, and a plurality of ADC are integrated in the chip concurrent working to improve sample frequency.This way is not only professional very strong, and cost is quite expensive, is not suitable for doing the data acquisition of general applications.

And for example Chinese patent 93110972.8 " a kind of data acquisition interface of memory device " and 200410043813.5 " based on the High-speed and Huge-capacity Data Acquisition of CPLD and SDRAM ", the former mainly is for improving picking rate, reducing interference in the work to the improvement of scsi interface circuit; The latter adopts CPLD (Complex Programmable Logic Device) to carry out the circuit design of high-speed data acquisition card, realizing the Starting mode able to programme of programmable sample clock and programmable sampling length and A/D change-over circuit, mainly is to prevent the pulse collection device that disturbs.

Because the difference of application scenario is also inequality to requirement of ultra-high-speed data acquisition interface structure and cost, and since the singularity in the design, the addressing of ultra-high-speed data acquisition system, and read-write control and data transfer must be realized by hardware.System is to the selection of device, and the printed panel wiring all has higher requirement; Existing ultra-high-speed data acquisition interface structure mostly uses parallel conversion hysteria analog to digital converter, fast data buffer storer and broadband mimic channel, has complex structure, cost problem of higher.

In sum, present high-speed sampling interface and sampling system rely on import more, or adopt complicated technology, not only cost an arm and a leg, and owing to the region reason almost can not get any after sale service; Be not suitable for doing the data acquisition of general applications.

The content of utility model

At the prior art above shortcomings, the purpose of this utility model provide a kind of simple in structure, cost is low, be suitable for doing the ultra-high-speed data acquisition interface of general applications.

The purpose of this utility model is achieved in that a kind of data acquisition interface, it is characterized in that comprising analogue buffer, high-speed AD converter, Data Buffer Memory, address generator, clock circuit and control circuit; Analogue buffer connects high-speed AD converter; Control circuit, address generator, Data Buffer Memory and high-speed AD converter are contacted successively; Clock circuit control linkage control circuit; The control end of control circuit connects simulation buffer cell and high-speed AD converter;

The input end of analogue buffer and control circuit is the input end of described data acquisition interface, and analog to digital converter is output as the output of data acquisition interface.Simulating signal exports the PC parallel port to send a command to high-speed AD converter after analogue buffer is handled after; Simulating signal sends order and read/write data, Data Buffer Memory and high-speed AD converter swap data through control circuit, address generator to the data memory buffer simultaneously; Control circuit is controlled by clock circuit, and control circuit is also controlled simulated cushioned unit and high-speed AD converter.

Described high-speed AD converter is selected the AD9048 AD transducer that walks abreast for use.

The utility model obtains this target at high-speed data, to satisfy application in fields such as transient signal analysis, radar, ultrasonic inspection, mass spectrophotometry, high-speed figure storage oscilloscope and Digital Image Processing, consider of the general requirement of this type of application to sampling precision, choose suitable modulus conversion chip, mainly considered the ratio of performance to price of hardware.So no matter from cost performance still from the technical guarantee aspect, this ultra-high-speed data acquisition interface that the utility model discloses all has fabulous DEVELOPMENT PROSPECT, it is the good computer data acquiring device of a kind of versatility at the high sample frequency design of in the above-mentioned field data being sampled, considerable benefit.

Compared to existing technology, the utlity model has following characteristics:

1, adopt the modulus conversion chip AD9048 of U.S. Analog Desive company, this device technology is ripe, and dependable performance, price are also lower;

2, simple and clear project organization very is convenient to the expansion and the upgrading of system;

3, the leading indicator of this interface: sample frequency 32MHz, data precision are 8, buffer 128K byte;

4, AFE (analog front end) is connected into inverting amplifier by a video amplifier AD848 and constitutes, and unity gain bandwidth reaches 175MHz, has very good DC characteristic;

5, the analog input scope of AD9048 is (0～-2) V, for the actual input that guarantees device is no more than ratings, has added the clamping circuit of being made up of two schottky diodes in the circuit;

6, the current expansion type constant pressure source of amplifier LM741 and 2N3906 formation provides the reference voltage of AD transducer;

7, the data buffer of system is made up of a monolithic 1M position CMOS static RAM (SRAM) MT5C1008, and the time of looking for only is 20ns;

8, the address generator of system is served as by five high speed forward-backward counters, and clock is provided by a monolithic 32MHz crystal oscillator, and the read-write operation of system is realized by some gate circuits.

Description of drawings

Fig. 1 is a functional-block diagram of the present utility model.

Fig. 2 is the utility model one embodiment circuit theory diagrams.

Fig. 3 is the built-in function structural drawing of AD9048.

Fig. 4 is the pin distribution plan of AD9048.

Fig. 5 is the pin distribution plan of MT5C1008.

Fig. 6 is TV signal peak value figure.

Embodiment

As shown in Figure 1, the ultra-high-speed data acquisition interface mainly comprises simulated cushioned unit 1, high-speed AD converter 2, Data Buffer Memory 3, address generator 4, clock 5 and 6 six funtion parts of control circuit, and analogue buffer 1 connects high-speed AD converter 2; Control circuit 6, address generator 4, Data Buffer Memory 3 and high-speed AD converter 2 are contacted successively; Clock circuit 5 control linkage control circuits 6; The control end of control circuit 6 connects simulation buffer cell 1 and high-speed AD converter 2; The input end of analogue buffer 1 and control circuit 6 is the input end of described data acquisition interface, and analog to digital converter 2 is output as the output terminal of data acquisition interface.

Simulating signal also comprises delay circuit and trigger etc. through simulated cushioned unit 1.Simulating signal exports PC parallel port (To PC Parallet Intertace) to send a command to high-speed AD converter 2 after analogue buffer 1 is handled after; Simulating signal sends order and read/write data, Data Buffer Memory 3 and high-speed AD converter 2 swap datas through

control circuit

6,4 pairs of data memory buffer of address generator 3 simultaneously; Control circuit 6 is by clock circuit 5 controls, and control circuit 6 is also controlled simulated cushioned unit 1 and high-speed AD converter 2.

As shown in Figure 2, the utility model AFE (analog front end) is connected into inverting amplifier by a video amplifier AD848 and constitutes, and the unity gain bandwidth of AD848 reaches 175MHz, and AD848 has very good DC characteristic simultaneously.The AFE (analog front end) Amplifier Gain is designed to-2.The core parts AD transducer of system is selected the AD9048 AD transducer that walks abreast for use.AD9048 is the 8 digital video ADCs of Analog Devices company than early development.This device technology is ripe, and dependable performance, price are also lower, and its key technical indexes is: the high-conversion rate of 35MHz, 8 precision, the linearity are better than 0.75LSB, all numeral outputs, go into equal TTL compatible.Consider of the general requirement of this type of application, so mainly considered the modulus conversion chip AD9048 that the performance and price of hardware is recently chosen to sampling precision.Fig. 3 and Fig. 4 are built-in function structure and the pin distribution plan of AD9048.The analog input scope of AD9048 is (0～-2) V, for the actual input that guarantees device is no more than ratings, has added the clamping circuit of being made up of two schottky diodes in the circuit.The current expansion type constant pressure source that amplifier LM741 and 2N3906 constitute provides the reference voltage of AD transducer.

The data buffer of system is made up of a monolithic 1M position CMOS static RAM (SRAM) MT5C1008.Structure is 128KX8 on the MT5C1008 sheet, 32 pin DIP encapsulation.This sheet has low-power consumption, the feature of high speed, and the time of looking for only is 20ns.Fig. 5 is the pin distribution plan of MT5C1008.The address generator of system is served as by five high speed forward-backward counters, and clock is provided by a monolithic 32MHz crystal oscillator, and the read-write operation of system is realized by some gate circuits.

Application examples 1: transient pulse is caught

In the laser medicine instrument, usually need the fast-pulse of randomness is carried out wave form analysis.Accurately catching these pulses accurately is the bases of realizing analysis.Suppose that signal has pulse width 5 μ s, occurrence frequency 50/s, conventional recording technique is difficult to this class transient signal of record.The utility model ultra-high-speed data acquisition interface can write down this class signal effectively.In order to improve the efficient of pulse capture, system need install a simple hardware trigger device (referring to Fig. 1, Fig. 2) additional.Before data acquisition, by computing machine rest-set flip-flop is resetted, the high level of rest-set flip-flop output makes the ultra-high-speed data acquisition system be in data and obtains state, and system carries out the high-speed sampling of 32MHz to signal.Input signal enters the thresholding comparer of flip flop equipment simultaneously, if the signal input is lower than the setting thresholding, rest-set flip-flop keeps its high level output, and system continues sampling.When input signal is higher than thresholding, comparer output high level.This high level is forced rest-set flip-flop output low level, systematic sampling thereby termination after delaying time.In order to ensure the integrality of signal capture, delay time should be greater than the input signal pulse width.

Application examples 2: video image digitizing

The video image digitizing is to realize Digital Image Processing, the requisite technological means of Target Recognition.This task is normally served as by the image digitazation plate.The image digitazation plate comes down to have the specialized high-speed data acquisition system (DAS) of storer on the plate.Its singularity is that the reconstruction of the data acquisition of system and digital picture determined by hardware special on the plate fully and controlled by the synchronizing pulse in the full video signal.The utility model is a universal high speed digital quantity, and it also can be used for video image is quantized.But, because this system does not have special hardware, identification and synchro system, the reconstruction of digital picture must realize by software.

As shown in Figure 6, typical black and white composite video signal has the peak value of 1V, its top 70% representative image gray scale (1V is white, and 0.3V is black), and being lower than 0.3V is synchronizing signal, for 625 cable TV systems, a complete image is overlapped by two each 312.5 lines and forms.Doing each two field picture front has a long frame-synchronizing impulse, and the appearance of this signal is the sign that piece image begins.In order to obtain a complete digital picture, must carry out necessary expansion to high-speed data acquistion system.At first need 32MHz clock signal two divided-frequency.This is that the 32MHz sample frequency will cause unnecessary wasted memory because the bandwidth of video standard signal only is 6MHz.Clock behind the two divided-frequency is 16MHz, and piece image (comprising synchronizing signal) needs are the 640KB storer at least.Therefore storer 128KB on original plate needs to increase by four static RAM (SRAM) MT5C1008.The reconstruction of image comprises by software to be redistributed to the corresponding display buffer of computing machine unit to the identification of synchronizing signal and with the pixel of digitizing.Because all with the form storage of digital value, its identification is fairly simple for synchronizing signal and vision signal.The length that it should be noted that original digitized image is than should (EGA, VGA SVGA), reorganize (interpolation, double sampling) according to different displays.In addition, effective gray scale dynamic range of reconstructed image has only 7.For black white image, 128 grades of gray scales have been much higher than human eye gray scale resolution characteristic.

Claims

1, a kind of data acquisition interface is characterized in that comprising analogue buffer (1), high-speed AD converter (2), Data Buffer Memory (3), address generator (4), clock circuit (5) and control circuit (6); Analogue buffer (1) connects high-speed AD converter (2); Control circuit (6), address generator (4), Data Buffer Memory (3) and high-speed AD converter (2) are contacted successively; Clock circuit (5) control linkage control circuit (6); The control end of control circuit (6) connects simulation buffer cell (1) and high-speed AD converter (2);

The input end of analogue buffer (1) and control circuit (6) is the input end of described data acquisition interface, and analog to digital converter (2) is output as the output of data acquisition interface.

2, data acquisition interface according to claim 1 is characterized in that described high-speed AD converter (2) selects the AD9048 AD transducer that walks abreast for use.