CN101061954A - X-ray machine image processing device - Google Patents
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Abstract
The invention discloses a X-ray production apparatus image processing device, which is characterized by the following: possessing image receiving module, FPGA(9), image sending module, clock generating and buffer module and external control signal input module; connecting the image data source mouthpiece module to image data source through the image receiving module; connecting the input end of the image data source mouthpiece module to image collecting card of chief computer through image treating module and image sending module; connecting the control module in FPGA to PCI bus of chief computer through PCI bridge; sending local clock signal of the clock generating and buffer module to FPGA and PCI bridge. This invention can finish data communication and data-handling with bigger data quantity and higher speed.
Description
Technical field
The present invention relates to technical field of medical instruments, specifically a kind of flexible, satisfy the X-ray production apparatus image processing apparatus that big data quantity, high speed processing require.
Background technology
When utilizing digital X-ray unit that human body a part is shone, after the X line is injected human body, because the attenuation rate difference of human body different tissues, can form the X line image that carries the human body internal structural information, image amplifier becomes visible image to X line video conversion, by the CCD camera signal of video signal (being optical signal) is changed into the signal of telecommunication again.The image data that the CCD camera is obtained, owing to be subjected to all multifactor influences such as resolution of quantum noise, electronic noise and the CCD self on the image link, if do not do any Flame Image Process, be difficult to obtain high-quality clearly image, be unfavorable for doctor's diagnosis, therefore, image processing apparatus is the vitals of digital X-ray unit.
In the prior art, realize that the approach of Flame Image Process has two: the one, rely on computer fully, cause the CPU burden of computer too heavy, the quality of real time imaging still can not guarantee, and brings problems such as system stability difference; The 2nd, realize Flame Image Process with hardware, speed is fast, does not take computer resource, and stability is high.Therefore, usually some algorithms Flame Image Process simple relatively, that data volume is big is realized with hardware, and the algorithm relative complex, the Flame Image Process that data volume is little is realized by software, the latter more lays particular emphasis on the post processing that does not have real-time to require simultaneously, can make system reach best performance like this.
Conventional hardware realizes that image process method has following several: the one, adopt the dedicated processes chip, the method function singleness, design underaction, cost height; The 2nd, adopt DSP (Digital Signal Processing) chip, also more and more higher to the requirement of its arithmetic speed along with the raising day by day of image resolution ratio and frame per second, dsp chip has been difficult to meet the demands; The 3rd, adopt CPLD (Complex ProgrammableLogic Device, a kind of logic element more complicated) than PLD, because its capacity is less, a plurality of chips need be coupled together, not only cost increases, and also brings the difficulty in the design.
In addition, in same category of device in the past, can design an independently graphics processing unit usually, link to each other with main control computer by the RS-232 serial ports then.Inconvenience so not only is installed, on cable connects, needs power supply and communication separately, and because the restriction of RS-232 serial ports bandwidth can only realize the simple parameters setting, and it is bigger to finish data volume, the transmission of rate request higher data.
Summary of the invention
At the problem that faces in conventional method of the prior art and the same category of device, the X-ray production apparatus image processing apparatus that the object of the present invention is to provide a kind of convenient and flexible installation, satisfy big data quantity, high speed processing requires.
For achieving the above object, the technical solution used in the present invention is:
Have image receiver module, FPGA, image sending module, clock generation and buffer module and external control signal input module, wherein the image data source interface module of FPGA inside is connected to image data source by the image receiver module, and the outfan of image data source interface module links to each other with image pick-up card in the main control computer by the image sending module of image processing module and outer setting; The control module of FPGA inside links to each other with the pci bus of main control computer by the PCI bridge, links to each other with the miscellaneous equipment of X-ray production apparatus by external control signal input module (17); The local clock signal that clock takes place and buffer module produces is connected to FPGA and PCI bridge respectively.
Described FPGA inside also has 1DCM module and 2DCM module, wherein the 1DCM module is located between image receiver module and image data source interface module, image processing module and the control module, and the 2DCM module is located between clock generation and buffer module and image processing module and the control module; The internal circuit of described image processing module strengthens module, Gamma correction module and positive and negative flip module for recursive noise reduction module, the edge that is connected in successively between image data source interface module and the image sending module, also have the image flip module, can be connected in the optional position in the foregoing circuit; Above-mentioned each module links to each other with the pci bus of main control computer through the PCI bridge by control module, and image processing module also is connected to memory set; Described recursive noise reduction inside modules has a plurality of fifo modules and computing module, the input of one of them fifo module links to each other with the image data source interface module, the outfan of another fifo module is connected to the edge and strengthens module, and computing module is located between the memorizer in a plurality of fifo and the memory set; Be provided with data temporary module, the 1st computing module and image output module in the described edge enhancing module, wherein the input of the temporary module of data is connected with the recursive noise reduction module, and outfan is connected to the image flip module by the 1st computing module and image output module; Described image flip module inside has that image is write logical block and image is read logical block, wherein image is write the logical block input and is connected to edge enhancing module, outfan is connected to the memorizer in the memory set, and image is read logical block and is located between memorizer and the Gamma correction module; Described Gamma correction inside modules is the Gamma correction LUT table of being located between image flip module and the positive and negative flip module, and the input of this Gamma correction LUT table also is connected to the LUT table and writes logical block.
Also have pre-noise reduction module and the motion detection block that is connected in successively between image data source interface module and the recursive noise reduction module in image processing module inside; Described motion detection block inside writes logical block by being located at image between the memorizer in pre-noise reduction module and the memory set, image is read logical block and is connected to the 2nd computing module, and the outfan of the 2nd computing module links to each other with the recursive noise reduction module;
The present invention also is provided with the A/D module, and its digital quantity outfan links to each other with the input of image receiver module, and the analog quantity input is connected to image data source.
The present invention has following beneficial effect and advantage:
1. it is bigger to finish data volume, and the rate request higher data is transmitted and date processing, and still has the space of continuous lifting.Because the present invention adopts the FPGA device to do picture processing chip, the bandwidth of the DSP bandwidth ratio dsp processor of FPGA will exceed several times, can realize present high-resolution, the clinical requirement of high frame per second, it is fast that memorizer adopts storage speed simultaneously, the simple SRAM of control method has effectively improved the speed of Flame Image Process;
2. function upgrading is convenient.Because the present invention adopts the FPGA device to do picture processing chip, continuous increase along with FPGA density, many modules that are used for Digital Signal Processing can be embedded into wherein, the reconfigurable function of FPGA makes function upgrading very convenient, and satisfies the requirement of growing arithmetic speed and the requirement that algorithm upgrades;
3. compact conformation, installation, power supply and communication are convenient.The present invention has designed a hardware generic structure, hardware circuit is based on the design of pci bus, combine closely with software system, make at the various algorithms of X-ray production apparatus Flame Image Process and can on this framework, realize, simultaneously, take into account and make system structure compactness, requirements such as easy communication, give full play to the advantage of hardware and software collaborative work in system, application flexibility is further strengthened.
Description of drawings
Accompanying drawing 1 is the application sketch map of the present invention in X-ray production apparatus;
Accompanying drawing 3 is image processing module block diagram of the present invention;
Accompanying drawing 4 is recursive noise reduction module frame chart of the present invention;
Accompanying drawing 5 strengthens module frame chart for edge of the present invention;
Accompanying drawing 6 is image flip module block diagram of the present invention;
Accompanying drawing 7 is Gamma correction module frame chart of the present invention;
Accompanying drawing 8 is motion detection block block diagram of the present invention.
The specific embodiment
The application of the present invention in X-ray production apparatus as shown in Figure 1, for making system have maximum motility, a hardware generic structure is provided, make at the various algorithms of X-ray production apparatus Flame Image Process and can on this framework, realize, and satisfy the requirement of growing arithmetic speed and the requirement that algorithm upgrades; Simultaneously, take into account and make system structure compactness, requirements such as easy communication.
In the present embodiment image processing apparatus 2 of the present invention is installed on the pci bus slot 43 of X-ray production apparatus main control computer 4, power supply is finished automatically by pci bus slot 43.The image input of image processing apparatus 2, output interface 5,16 link to each other with image pick-up card 3 with image data source 1 respectively.
Schematic block circuit diagram of the present invention has image receiver module 6, FPGA (field programmable gate array) 9, image sending module 15 and external control signal input module 17 as shown in Figure 2.Wherein the image data source interface module 10 of FPGA9 inside is connected to image data source 1 by image receiver module 6, and the outfan of image data source interface module 10 links to each other with image pick-up card 3 in the main control computer by the image sending module 15 of image processing module 11 and outer setting; The control module 14 of FPGA9 inside links to each other with the pci bus of main control computer by PCI bridge 19 and golden finger 20, receives external control signal by external control signal input module 17 simultaneously; Also have clock and take place and buffer module 18, the local clock signal of its generation is connected to FPGA9 and PCI bridge 19 respectively; Image processing module 11 also is connected to memory set 8; FPGA9 finishes the internal structure configuration by FPGA configuration module 7; FPGA9 utilizes the 1DCM module 12 of its inside and 2DCM module 13 to realize frequency multiplication, frequency division, functions such as clock driving.
Will finish the lot of data computing in real time, such as the recursive noise reduction of multiframe and pre-noise reduction, motion detection, the 7*7 edge strengthens, positive and negative upset, and the image upset, Gamma corrections etc. are very high to the rate request of the chip of realizing Flame Image Process.FPGA9 is made of a large amount of logic macrocells, by configuration, can form different hardware configurations, finishes different functions.Along with the continuous increase of FPGA density, many modules that are used for Digital Signal Processing can be embedded into wherein, such as: configurable RAM, DSP take advantage of and add module, flush bonding processor etc.The bandwidth of the DSP bandwidth ratio dsp processor of FPGA will exceed several times, and its reconfigurable function makes function upgrading convenient.Therefore, the FPGA device has captured increasing digital processing field.Just for these reasons, the present invention adopts the FPGA device to do picture processing chip.
Simultaneously, system is under different mode of operations, and the duty of hardware circuit is different.So need build the bridge that a hardware system and software system are linked up, to guarantee the motility of system design.Consider that current digital X line machine all has a main control computer, design a integrated circuit board based on PCI (peripheral component interconnect) bus, not only make easy communication, can realize the transmission of the look-up table of big data quantity fast, and power supply is convenient, make system structure compact more, give full play to the advantage of hardware and software collaborative work in system.In the present invention, hardware circuit is an integrated circuit board based on pci bus, is inserted in the main control computer, downloads look-up table by pci bus, carries out the setting of hardware circuit running parameter simultaneously.
Look-up table also is a method commonly used in the Flame Image Process, the content of look-up table (LUT) may need to change at any time, and the image processing function of different parameters is achieved, and the data volume of look-up table varies, the transmission requirement of look-up table data realizes fast, does not influence real-time Flame Image Process.
Operation principle of the present invention is: LVDS (Low Voltage Differential Signal) signal of image data source output, by image receiver module 6 the LVDS signal is changed into the TTL signal, FPGA9 reads in the image data source interface module 10 of FPGA9 inside with view data, sends to image processing module 11 then; The data of handling change into the LVDS signal by image sending module 15, and capture card 3 is given in final output; PCI bridge 19 changes into local bus with the pci bus signal, by the data on control module 14 these buses of reception of FPGA9 inside, downloads the LUT table, and control and answer signal is provided for PCI bridge 19, finishes the interface with pci bus; This control module 14 receives external control signal simultaneously, carries out logic synthesis according to external control signal with from the control command that pci bus receives, and produces final control signal and gives image processing module 11; Clock takes place and buffer module 18 produces local clock, and gives FPGA9 and PCI bridge 19 respectively by 2 clocks of clock buffer generation of zero propagation.That FPGA9 utilizes is inner the 1st, 2DCM module (digital dock administration module) 12,13 drives image data source clock and local clock respectively, sends to image processing module 11 and control module 14.
As shown in Figure 3, view data is finished Flame Image Process computings such as recursive noise reduction, edge enhancing, image upset, Gamma correction and positive and negative upset by the recursive noise reduction module 111, edge enhancing module 112, image flip module 113, Gamma correction module 114 and the positive and negative flip module 115 that are connected in successively between image data source interface module 10 and the image sending module 15 respectively in the mode of streamline in image processing module 11, finally exports to image sending module 15; Present embodiment is also finished pre-noise reduction and motion detection by pre-noise reduction module 116 and the motion detection block 117 be located between image data source interface module 10 and the recursive noise reduction module 111, its testing result is given recursive noise reduction module 111, like this, for stationary object, can adopt bigger noise reduction coefficient, obtain good image; And after detecting object of which movement, use not even noise reduction of less noise reduction coefficient instead, improve or avoided moving object is done recursive noise reduction and the conditions of streaking that produces.
As shown in Figure 4, in the present embodiment, recursive noise reduction module 111 inside are provided with the 1st～4fifo module 26～29 and computing module 25, wherein computing module 25 be located at the 1st, between the 1st, 2 memorizeies 23,24 in 2fifo module 26,27 and the memory set 8,3fifo module 28 is connected between 1fifo module 26 and the 1st memorizer 23, and 2fifo module 27 links to each other with 4fifo module 29 and the 2nd memorizer 24 respectively.
The work process of recursive noise reduction module 111 is: will write a fifo module 26 from the data that image data source interface module 10 obtains, after delegation finishes, read the data in the 1st memorizer 23 (input picture of storage previous frame), the 2nd memorizer 24 (output image of storage previous frame) and the 1fifo module 26 simultaneously, weighted sum in computing module 25, operation result is sent into 2fifo module 27, when from 1fifo module 26, reading data participation computing, data are write 3fifo module 28; After computing finishes, the data that read 3fifo3 module 28 are written back to the 1st memorizer 23, from 2fifo module 27, read data and be written back to the 2nd memorizer 24, give 4fifo module 29 simultaneously, purpose is that the next stage module edge enhancing module 112 that when next line begins view data is outputed in the image processing module is handled.Weight coefficient when the order that obtains from control module 14 has determined computing.If automatic mode, then recursive noise reduction module 111 is according to the testing result automatic switchover weight coefficient of motion detection block 117.
As shown in Figure 5, be provided with the temporary module 30 of data in the edge enhancing module 112, its outfan is connected to image output module 32 by the 1st computing module 31.
It in the present embodiment enhancing that neighborhood territory pixel is realized 7*7, the LineBuffer of 7 row need be set, the temporary module 30 of data utilizes the RAM piece of FPGA9 inside to realize the temporary of data, and exporting matrix to the 1 computing module 31 of a 7*7, the result after the calculating is to handle in the image flip module 113 by the next stage module that image output module 32 outputs to image processing module 11.The time-delay that the temporary and calculating of image can bring output image, image output module 32 can achieve frames synchronously and the synchronous time-delay of row.Weight coefficient when the order that obtains from control module 14 has determined computing, can realize respectively not having strengthen, 3*3 strengthens, 5*5 strengthens and 7*7 strengthens.
As shown in Figure 6, described image flip module 113 is write logical block 33 and image by its inner image that is provided with respectively and is read logical block 34 and link to each other with the 3rd, 4 memorizeies 35,36 in the memory set 8, wherein image is write the table tennis write operation of logical block 33 control the 3rd memorizeies 35 and the 4th memorizer 36, image is read the table tennis read operation of logical block 34 control SRAM memorizeies 35 and SRAM memorizer 36, by provide different sequence of addresses realize image about upset and spinning upside down.The order that obtains from control module 14 has determined its mode of operation, can realize respectively not overturning, about upset, spin upside down, up and down upset simultaneously.
As shown in Figure 7, described Gamma correction module 114 inside are Gamma correction LUT table 37, and its input is connected to the LUT table and writes logical block 38.Gamma correction LUT table 37 is the twoport ram that utilize the RAM piece realization of FPGA inside, can carry out read-write operation simultaneously, control module 14 will be sent into Gamma correction module 19 from the LUT table data that PCI bridge 19 passes over, writing logic 38 by the LUT table writes among the twoport ram, view data is connected to reading on the address port of twoport ram, the data that obtain by the read operation gained data of tabling look-up are exactly delivered in the next stage image processing module.
As shown in Figure 8, described motion detection block 117 inside have the 2nd computing module 41, write logic 39 and image by image and read logic 40 and link to each other with the 5th memorizer 42 in the memory set 8.Motion detection block 117 is done a reduction with the image of pre-noise reduction module 116 outputs, square in the middle of only getting, deposit in the 5th memorizer 42, after image has been deposited 2 width of cloth (square image just), begin reading images immediately, do the calculating that piece mates by the 2nd computing module 41, result of calculation comprises the speed and the direction of motion, gives recursive noise reduction module 111 with the noise reduction coefficient under the decision automatic mode.So finish before calculating the middle square image arrival of wanting the infra piece image.
In Flame Image Process; the multiframe computing is a kind of processing method that often can use; present embodiment is rate request and the control requirement of satisfying the multiframe computing, and the 1st～5 memorizer 23,24,35,36 and 42 adopts storage speed fast, the simple SRAM of control method (SRAM).
The present invention can be directly used in digital X line machine, as is used for non-digitalization X line machine, then needs to establish the A/D module at the input of image receiver module (6), mimic picture signal is changed into digital signal be connected on apparatus of the present invention and get final product.
Claims (10)
1. X-ray production apparatus image processing apparatus, it is characterized in that: have image receiver module (6), FPGA (9), image sending module (15), clock generation and buffer module (18) and external control signal input module (17), wherein the inner image data source interface module (10) of FPGA (9) is connected to image data source (1) by image receiver module (6), and the outfan of image data source interface module (10) passes through the image sending module (15) of image processing module (11) and outer setting and links to each other with image pick-up card (3) in the main control computer; The inner control module (14) of FPGA (9) links to each other with the pci bus of main control computer by PCI bridge (19), by external control signal input module (17) link to each other with the miscellaneous equipment of X-ray production apparatus (optional); The local clock signal that clock takes place and buffer module (18) produces is connected to FPGA (9) and PCI bridge (19) respectively.
2. by the described X-ray production apparatus image processing apparatus of claim 1, it is characterized in that: described FPGA (9) inside also has 1DCM module (12) and 2DCM module (13), wherein 1DCM module (12) is located between image receiver module (6) and image data source interface module (10), image processing module (11) and the control module (14), and 2DCM module (13) is located between clock generation and buffer module (18) and image processing module (11) and the control module (14).
3. by the described X-ray production apparatus image processing apparatus of claim 1, it is characterized in that: the internal circuit of described image processing module (11) strengthens module (112), Gamma correction module (114) and positive and negative flip module (115) for recursive noise reduction module (111), the edge that is connected in successively between image data source interface module (10) and the image sending module (15), also have image flip module (113), can be connected in the optional position in the foregoing circuit; Above-mentioned each module links to each other with the pci bus of main control computer through the PCI bridge by control module (14), and image processing module (11) also is connected to memory set (8).
4. by the described X-ray production apparatus image processing apparatus of claim 3, it is characterized in that: described recursive noise reduction module (111) inside has a plurality of fifo modules and computing module (25), the input of one of them fifo module links to each other with image data source interface module (10), the outfan of another fifo module is connected to the edge and strengthens module (112), and computing module (25) is located between the memorizer in a plurality of fifo and the memory set (8).
5. by the described X-ray production apparatus image processing apparatus of claim 3, it is characterized in that: be provided with data temporary module (30), the 1st computing module (31) and image output module (32) in the described edge enhancing module (112), wherein the input of the temporary module (30) of data is connected with recursive noise reduction module (111), and outfan is connected to image flip module (113) by the 1st computing module (31) and image output module (32).
6. by the described X-ray production apparatus image processing apparatus of claim 3, it is characterized in that: described image flip module (113) inside has that image is write logical block (33) and image is read logical block (34), wherein image is write logical block (33) input and is connected to edge enhancing module (112), outfan is connected to the memorizer in the memory set (8), and image is read logical block (34) and is located between memorizer and the Gamma correction module (114).
7. by the described X-ray production apparatus image processing apparatus of claim 3, it is characterized in that: described Gamma correction module (114) is inner for being located at the Gamma correction LUT table (37) between image flip module (113) and the positive and negative flip module (115), and the input of this Gamma correction LUT table (37) also is connected to the LUT table and writes logical block (38).
8. by the described X-ray production apparatus image processing apparatus of claim 3, it is characterized in that: also have pre-noise reduction module (116) and the motion detection block (117) that is connected in successively between image data source interface module (10) and the recursive noise reduction module (111) in image processing module (11) inside.
9. by the described X-ray production apparatus image processing apparatus of claim 8, it is characterized in that: described motion detection block (117) is inner to write logical block (39) by being located at image between the memorizer in pre-noise reduction module (116) and the memory set (8), image is read logical block (40) and is connected to the 2nd computing module (41), and the outfan of the 2nd computing module (41) links to each other with recursive noise reduction module (111).
10. by the described X-ray production apparatus image processing apparatus of claim 1, it is characterized in that: also be provided with the A/D module, its digital quantity outfan links to each other with the input of image receiver module (6), and the analog quantity input is connected to image data source (1).
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| CN103610469A (en) * | 2013-11-20 | 2014-03-05 | 刘国平 | Radiology department digital radiography system and operation method thereof |
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| US6215898B1 (en) * | 1997-04-15 | 2001-04-10 | Interval Research Corporation | Data processing system and method |
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| CN2481089Y (en) * | 2001-05-30 | 2002-03-06 | 徐伟 | Digitization x-ray image video collection device |
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| EP2511787B1 (en) * | 2003-05-23 | 2017-09-20 | IP Reservoir, LLC | Data decompression and search using FPGA devices |
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| CN103676747A (en) * | 2013-12-23 | 2014-03-26 | 华润万东医疗装备股份有限公司 | Flat finder communication control system |
| CN105763818A (en) * | 2016-04-06 | 2016-07-13 | 上海奕瑞光电子科技有限公司 | FPGA-based flat panel detector (FPD) with image correction function |
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