CN1874463A - Device of asymchronous acquisition for image in real time - Google Patents
Device of asymchronous acquisition for image in real time Download PDFInfo
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- CN1874463A CN1874463A CN 200610061478 CN200610061478A CN1874463A CN 1874463 A CN1874463 A CN 1874463A CN 200610061478 CN200610061478 CN 200610061478 CN 200610061478 A CN200610061478 A CN 200610061478A CN 1874463 A CN1874463 A CN 1874463A
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Abstract
The apparatus is designed for use in making synchronous process for the image data flow outputted from the image sensor and providing the processed data flow to the image processor. The apparatus comprises a control logic unit and a data buffering unit; the data buffering unit comprises a register file divided logically into two register groups; the image data output from the image sensor is alternatively written into the registers in said two register groups; the image processor reads the image data in the registers in two logic register group.
Description
[technical field]
The present invention relates to a kind of device of asymchronous acquisition for image in real time, particularly a kind of device of asymchronous acquisition for image in real time that is applicable to portable equipment.
[background technology]
In order to reduce system cost, the reduction equipment volume, for the realtime graphic process chip in the portable set, handled external image sensor signal generally directly enters chip in the mode of binary data stream.
A kind of general situation is an imageing sensor when the binary image data stream of output, and the clock of its output institute reference and the clock of picture processing chip operate as normal institute reference exist between the two such as differences such as frequency, phase places.Obviously, picture processing chip must include asynchronous image capture interface, correctly to read the information in the input binary picture data stream.The data that correct reading images transducer is provided are one of essential basic functions of image processing system.
See also Fig. 1, be a kind of typical construction of image processing system.Wherein, PCLK is the reference clock that the binary picture data stream of imageing sensor 11 outputs is adopted, and CLK is the work reference clock of image processing module.The binary picture data of imageing sensor 11 output non-modulated flows to device of asymchronous acquisition for image in real time 13,13 pairs of image data streams that receive of device of asymchronous acquisition for image in real time carry out Synchronous Processing, be converted into binary picture data stream, be sent to realtime graphic and handle primary module through ovennodulation.
At present, main imageing sensor comprises CCD (Charge Coupled Device, charge coupled device) and CMOS (Complementary Metal-Oxide-Semiconductor Transistor, CMOS (Complementary Metal Oxide Semiconductor)) two classes.The operation principle of imageing sensor is by light-electric transition effects, will collect to be exported by analog to digital converter after optical signalling converts the signal of telecommunication to again.The data flow of output can be original Bayer data format (a kind of raw image data form that Kodak proposes), also can be the data format after other are changed through color gamut space, as YCbCr 4:2:2 form (a kind of international transmission of video images data format).Except pixel data output, imageing sensor also can be exported and characterize in a frame synchronization clock signal (VSYNC) that a two field picture begins/finish and the frame number of pels per line according to the capable synchronous sequence signal (HREF) of beginning/end.
Fig. 2 has described the sequential relationship between a kind of clock signal and view data (DATA).But each imageing sensor manufacturer there are differences when the definition clock signal.Frame synchronizing signal shown in Fig. 2 is keeping low level, and line synchronizing signal is when keeping high level, and view data just can be effective.The frame synchronizing signal of the imageing sensor of some manufacturer production regulation may be that high level is effective, and that line synchronizing signal also may be defined as low level is effective.In addition, some producer may stipulate with the rising edge of reference clock (PCLK) view data to be sampled, and other manufacturer then regulation samples with the trailing edge of PCLK.
When the design device of asymchronous acquisition for image in real time, the sequential supposition of input signal is needed the sequential definition of the realistic imageing sensor that adopts.In hand-held portable devices was used, because imageing sensor is when the data flow of output consecutive image, its output can not be interrupted midway.In order to guarantee that the entire image processing flow process overflow error can not take place, the reference clock frequency of picture processing chip reception data can be higher than the dateout reference clock frequency of imageing sensor.Present integrated circuit production technology can satisfy the rate request of picture processing chip easily.
There are two kinds of technical schemes in the existing image asynchronous collecting interface arrangement design that is used for portable equipment:
First kind of scheme is to adopt two-stage d type flip flop polyphone.See also Fig. 3, the binary picture data stream of the non-modulated of imageing sensor output is by behind the d type flip flop 21 of two-step serial, and the binary picture data that is converted to through ovennodulation flows to into picture processing chip.Though this scheme simplicity of design, the restrictive condition of correct work is more, and the scope of application is narrow partially.Owing to need guarantee work clock territory at picture processing chip, through each signal in the synchronized images data/address bus the work of the work clock of picture processing chip trigger along (some chip setting be rising edge clock, some chip setting be the clock trailing edge) all must be effectively, the Data Receiving reference clock frequency that therefore need guarantee picture processing chip must be three times of dateout reference clock frequency of imageing sensor at least.If there is bigger distortion in reference clock signal, then the asynchronous-sampling interface can correctly work desired difference on the frequency can be bigger.Obviously, this programme existence limits than obvious speed.When picture processing chip required to handle the image of big resolution, the demand of its hardware supports was higher.Though, can not satisfy the high speed requirement of real time image collection so this programme cost is lower.
Second kind of scheme is all to adopt an asynchronous FIFO (First-In First-Out, First Input First Output) as buffer memory to each signal in the picture signal bus.See also Fig. 4, the view data of imageing sensor output writes among the FIFO 21, and image processing module is reading of data from FIFO 21.The read-write control logic must guarantee that overflowing does not appear in FIFO 21.This programme exists the read-write control logic design difficulty of two major defect: FIFO 21 higher, and the memory construction that FIFO 21 physics realizations are adopted has the bigger defective of hardware spending.And because consumer portable equipment has higher requirement to reducing cost, so though this scheme can satisfy the requirement of operating rate, because the cost defective, and be not suitable for consumer portable set.
[summary of the invention]
Technical problem to be solved by this invention is to provide a kind of device of asymchronous acquisition for image in real time, particularly a kind of device of asymchronous acquisition for image in real time that is applicable to portable equipment.
For solving the problems of the technologies described above, the technical solution adopted in the present invention is: a kind of device of asymchronous acquisition for image in real time, be used for the image data stream of imageing sensor output is carried out Synchronous Processing, read for image processing module, this device comprises control logic part and metadata cache part, its metadata cache partly is a register file, logically be divided into two registers group, the view data of imageing sensor output is the register that unit alternately writes described two logic register groups with the group, and image processing module is that unit reads the view data in the register of described two logic register groups with the group.
Device of asymchronous acquisition for image in real time of the present invention not only hardware cost is very cheap, can reach higher picking rate, and can tolerate the more reference clock input of distortion, and the operational environment accommodation of broad can be arranged.
[description of drawings]
Fig. 1 is a kind of typical construction block diagram of image processing system.
Fig. 2 is the timing diagram between image processing system clock signal and view data.
Fig. 3 is the structured flowchart that conventional images asynchronous collecting interface arrangement adopts two-stage d type flip flop polyphone scheme.
Fig. 4 is that conventional images asynchronous collecting interface arrangement adopts the structured flowchart of asynchronous FIFO as buffering scheme.
Fig. 5 is the structured flowchart of image asynchronous collecting interface arrangement of the present invention.
Fig. 6 is the schematic diagram that metadata cache partial logic of the present invention is divided.
Fig. 7 is the present invention carries out read-write operation to the registers group of data buffer memory part a flow chart.
[embodiment]
The invention will be further described below in conjunction with accompanying drawing.
The present invention is a kind of device of asymchronous acquisition for image in real time that is applicable to portable equipment, and the effect of this device is the output signal of imageing sensor is made adjustment, and it can correctly be read by picture processing chip.This device is also referred to as " Synchronous Processing " to the adjustment of image data stream.
The device that designs among the present invention at actual application environment have following special character: imageing sensor is output as binary digital signal, and analog signal need could be supported through analog-to-digital conversion; The data output speed of imageing sensor is no more than picture processing chip deal with data speed.
See also Fig. 5 to Fig. 7, device of asymchronous acquisition for image in real time of the present invention adopts pure hardware circuit, is divided into the d type flip flop of control logic part, metadata cache part and two-step serial.Wherein the logic control part is mainly finished controlled function shown in Figure 7, the switching of the reading-writing port of two registers group that while management data buffer memory part is comprised.The d type flip flop of two-step serial is used for transmission frame synchronous sequence signal and row synchronous sequence signal.
This metadata cache part physically can be the register file of an integral body, also can be two or more little register files.It comprises the even number register, is divided into two group registers group 41 and registers group 42 in logic, and the register length that wherein belongs to two logic register heaps is identical.
The imageing sensor dateout writes the register that registers group 41 and registers group 42 are comprised with the group for the unit alternating sequence.Write when full when the register of registers group 41, send the full scale will signal of registers group 41 correspondences, successive image transducer dateout writes the register of registers group 42 simultaneously.Write when full when the register of registers group 42, send the full scale will signal of registers group 42 correspondences, successive image transducer dateout writes the register of registers group 41 simultaneously.
After registers group 41 full scale will signals were effective, image processing module began to read the value of register that registers group 41 comprises.Read finish after with registers group 41 full scale will invalidating signalizations.Similarly, after registers group 42 full scale will signals were effective, image processing module began to read the value of register that registers group 42 comprises.Read finish after with registers group 42 full scale will invalidating signalizations.The full scale will signal of described two registers group is sent to image processing module work reference clock territory by the d type flip flop of two-step serial from imageing sensor work reference clock territory.
In above-mentioned flow process, it is not controlled, continuous that vision sensor data alternately writes the pair register group; It is controlled, discrete that picture processing chip alternately reads the pair register group.So its main flow is alternately write operation, alternately read operation is positioned at subordinate status.In addition, the operation of reading all data among the registers group A in proper order must be finished before the EO of next time writing full registers group B.The operation of reading all data among the registers group B must be finished before the EO of next time writing full registers group A equally, in proper order.
Because the work reference clock frequency of image processing module will be higher than the frequency of the work reference clock of imageing sensor, though the imageing sensor dateout is not subjected to the control of registers group 41 (or 42) full scale will signal when writing register file, but as long as every group register quantity rationally is set, still can guarantee that when the imageing sensor dateout newly write certain group register file, the data of storing before in this group register file were read fully by image processing module.
The quantity of every group of register is determined by the difference of image processing module operating rate and imageing sensor operating rate.Get every group of register and be made of m register, work clock length cycle time that image processing module fetches data is T
Clk, work clock length cycle time of imageing sensor dateout is T
PclkThen the register quantity m in the register file must satisfy the relation that is shown below:
According to formula (1) as can be known, when image processing module during than fast 1 times of imageing sensor operating rate, whole asynchronous interface only needs 2 * m=4 register.When image processing module than imageing sensor operating rate fast 2 times and when above, whole asynchronous interface only needs 2 registers.Simultaneously, owing to introduced the design of metadata cache in this programme design, even the work reference clock of imageing sensor and image processing module has distortion to a certain degree, data still can obtain gathering accurately.
Number of pels per line is according to the capable synchronous sequence signal (HREF) of beginning/end in a frame synchronization clock signal (VSYNC) that begins/finish for a two field picture and the frame, because these two signals that clock signal all is a bit wide adopt the d type flip flop of two-step serial to transmit and can meet the demands.In addition, also these two clock signals can be used as is extra two of pixel data, corresponding to two information that are used for storing these two clock signals of the expansion of the register bit wide in the register file.And when reads pixel data, these extra two of storage time sequence information are identified as VSYNC and HREF signal.So also can realize the asynchronous real-time collection of VSYNC and HREF clock signal.
Below be the example of a practical application: cmos image sensor is with the reference clock frequency output consecutive image signal of 27 megahertzes.This picture signal is 30fps (frame/second), and resolution is the consecutive image signal of 640 * 480 YCbCr 4:2:2 form.The multimedia process chip that imageing sensor connected is integrated realtime graphic asynchronous collecting interface of the present invention and realtime graphic processing unit.The work reference clock frequency of chip is 60 megahertzes.Imageing sensor was slightly less than 1: 2 with the ratio of the operating frequency of many matchmakers figure process chip.Comprise two registers in each register file in the asynchronous image capture interface, promptly have only 4 registers altogether.This integrated realtime graphic asynchronous collecting interface can be correct under the operating frequency of 60 megahertzes collection with the output of the cmos image sensor of 27 mhz frequencies work.
And for handheld portable devices, resolution is 352 * 288, and the consecutive image of 30fps just can be considered to real-time.The device of asymchronous acquisition for image in real time that only uses 4 registers that is operated in 15 mhz frequencies just can be supported the correct collection of this realtime graphic input.Therefore, technical scheme of the present invention can well satisfy the requirement of IMAQ.
Claims (10)
1, a kind of device of asymchronous acquisition for image in real time, be used for the image data stream of imageing sensor output is carried out Synchronous Processing, read for image processing module, described device comprises control logic part and metadata cache part, it is characterized in that, described metadata cache partly is a register file, logically be divided into first registers group and second registers group, the view data of described imageing sensor output is the register that unit alternately writes described two logic register groups with the group, and described image processing module is that unit alternately reads the view data in the register of described two logic register groups with the group.
2, device of asymchronous acquisition for image in real time as claimed in claim 1 is characterized in that, described device further comprises the d type flip flop of two groups of two-step serial.
3, device of asymchronous acquisition for image in real time as claimed in claim 1 is characterized in that, described metadata cache part physically comprises some little register files, and the register length that wherein belongs to described two logic registers heap is identical.
4, device of asymchronous acquisition for image in real time as claimed in claim 1 is characterized in that, the data of described two logic register groups write flow process and are:
The view data of imageing sensor output is write the register of described first registers group;
Write when full when described first registers group, send its corresponding full scale will signal, simultaneously follow-up data is write the register of described second registers group;
Write when full when described second registers group, send its corresponding full scale will signal, simultaneously follow-up data is write the register of described first registers group.
5, device of asymchronous acquisition for image in real time as claimed in claim 4 is characterized in that, the data read flow process of described two logic register groups is:
When the full scale will signal of described first registers group effectively after, described image processing module reads the value of described first register that registers group comprises, read finish after, with its full scale will invalidating signalization;
When the full scale will signal of described second registers group effectively after, described image processing module reads the value of described second register that registers group comprises, read finish after, with its full scale will invalidating signalization.
6, as claim 4 or 5 described device of asymchronous acquisition for image in real time, it is characterized in that the full scale will signal of described two logic register groups is sent to image processing module work reference clock territory by the d type flip flop of two-step serial from imageing sensor work reference clock territory.
7, device of asymchronous acquisition for image in real time as claimed in claim 1 is characterized in that, is m if get the register quantity of every group of described logic register group, and work clock length cycle time that described image processing module fetches data is T
Clk, work clock length cycle time of described imageing sensor dateout is T
Pclk, then described register quantity m is determined by following formula:
8, device of asymchronous acquisition for image in real time as claimed in claim 2 is characterized in that, the d type flip flop of described two-step serial is used for transmission frame synchronous sequence signal and row synchronous sequence signal.
9, device of asymchronous acquisition for image in real time as claimed in claim 1, it is characterized in that, the frame synchronization clock signal of described device and row synchronous sequence signal are as extra two of view data, it is stored among two of register expansion in the described logic register heap and transmits, when reads image data, two of storing described clock signal are identified as frame synchronization clock signal and row synchronous sequence signal respectively.
10, a kind of realtime image data stream is carried out the method for Synchronous Processing, is used for the realtime image data of imageing sensor output is handled, read, it is characterized in that, said method comprising the steps of for image processing module:
The metadata cache part of device of asymchronous acquisition for image in real time logically is divided into two registers group;
With the view data of described imageing sensor output is the register that unit alternately writes described two logic register groups with the group;
Making described image processing module is that unit alternately reads the view data in the register of described two logic register groups with the group.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103440279A (en) * | 2013-08-13 | 2013-12-11 | 江苏华大天益电力科技有限公司 | Data adapter and data adaptation method thereof in data acquisition process |
| CN108540689A (en) * | 2018-04-09 | 2018-09-14 | 珠海全志科技股份有限公司 | Image-signal processor |
| CN108632624A (en) * | 2017-12-18 | 2018-10-09 | 百富计算机技术（深圳）有限公司 | Image processing method, device, terminal device and readable storage medium storing program for executing |
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- 2006-06-29 CN CNB2006100614780A patent/CN100481913C/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103440279A (en) * | 2013-08-13 | 2013-12-11 | 江苏华大天益电力科技有限公司 | Data adapter and data adaptation method thereof in data acquisition process |
| CN108632624A (en) * | 2017-12-18 | 2018-10-09 | 百富计算机技术（深圳）有限公司 | Image processing method, device, terminal device and readable storage medium storing program for executing |
| CN108540689A (en) * | 2018-04-09 | 2018-09-14 | 珠海全志科技股份有限公司 | Image-signal processor |
| CN108540689B (en) * | 2018-04-09 | 2020-10-02 | 珠海全志科技股份有限公司 | Image signal processor, application processor and mobile device |
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