CN2833703Y - RISC microprocessor-based serial communication port - Google Patents
RISC microprocessor-based serial communication port Download PDFInfo
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- CN2833703Y CN2833703Y CNU2005200446926U CN200520044692U CN2833703Y CN 2833703 Y CN2833703 Y CN 2833703Y CN U2005200446926 U CNU2005200446926 U CN U2005200446926U CN 200520044692 U CN200520044692 U CN 200520044692U CN 2833703 Y CN2833703 Y CN 2833703Y
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Abstract
The utility model relates to an RISC microprocessor based serial communication port. An interface circuit which is used as a sub-module circuit is designed in a chip, registers of a microcontroller are arranged to realize the work of a communication module circuit and the purpose of communication is achieved through general input and output ports. The communication module circuit works with relative independence, and the mode of operation is simple and convenient. After resources of peripheral modules are reasonably matched with the communication module circuit, the communication module circuit can be integrated into various embedded systems and single chip systems (SOC), and the utility model is used in consumption electronics, communication, satellite positioning, audio fields, video fields, etc.
Description
Technical field
The utility model relates to microcontroller (MCU) field that belongs to the SIC (semiconductor integrated circuit) design field, particularly a kind of serial communication port based on the RISC microcontroller.
Background technology
Continuous progress along with deep-submicron CMOS integrated circuit production technology, at present technically can be integrated in the microcontroller of complexity (MCU) kernel on the chip piece, leave enough silicon area simultaneously and be used to realize complicated storer and peripheral hardware logic, the method for designing and the framework that are used for high-end 32 and 64 bit CPUs in the past can effectively be used for low price 8 8-digit microcontroller systems now.Utilize these powerful and cheap microcontrollers, system-wide integrated level improves constantly.And the raising of integrated level, making becomes a kind of possibility with the communication interface circuit design at chip internal.
In recent years, the chip of serial communication interface circuit has obtained to popularize widely.Though the kind of serial communication interface is a lot of now, various serial communication interfaces and serial communication protocol have also appearred in industry one after another, Micro Wire such as National Semiconductor, the usb bus of companies such as Intel, the IEEE-19394 of Apple, the CAN bus of Bosch, the SPI interface of Motorola Inc., the IIC agreement of PHILIPS Co., the proposed standard RS-232 of EIA, RS-422, RS-485 or the like are to be used for realizing technology and the standard relevant with the serial communication function; But most industry company is all with various serial communication interfaces, the independent chip that is designed to.For should the integrated serial communication interface a lot of different views of microcontroller, but being based on the following aspects basically considers: the framework of (1) microcontroller itself, can realize the possibility of serial communication interface, promptly whether micro controller frame has extensibility and operation simplification; (2) circuit of microcontroller own and serial communication module circuit complexity relatively, this respect mainly is based on the consideration of chip cost; Whether (3) microcontroller of increase serial communication module possesses the fairly perfect row surveyed design, because the test of telecommunication circuit is relatively complicated.(4) microcontroller of increase serial communication module is for the concrete influence of circuit power consumption situation.Reasonably design is adopted in the consideration of comprehensive these factors, this microcontroller, and various serial communication interfaces are integrated in chip internal, has promoted the communication interface function of microcontroller greatly, and the relative increase with power consumption of its cost simultaneously seldom.
Serial communication interface is integrated in chip internal, on production prices and application function, certain advantage is arranged.Integrated communication interface circuit comprises remote serial communication and the in-plant serial expansion of internal system between the system, and this has just saved the chip cost of external communication interface greatly.Simultaneously, every kind of serial communication interface all possesses various communication interfaces, comprises master control, driven, and is synchronous, asynchronous, and different transmission data speed or the like is set, and has quite strong compatibility, makes that the scope of its application is more extensive.Certainly, the characteristics of the communication interface under this micro controller frame itself have also determined its inevasible defective: such as for the field of independent application microcontroller nuclear or the field of using serial communication interface separately, may cause the waste of certain resource.
The microcontroller products that has a lot of companies to produce now all has certain serial communication interface, as Microchip, Motorola, NEC, Hitachi, Atmel, Holtek etc.Though the product of these companies all possesses certain serial communication interface, but do not integrate in the middle of most these products and use frequent serial communication interface, basically all be to design the serial communication interface of company separately separately, make that the scope of using is less comparatively speaking.
This product is integrated the relative merits of serial communication interfaces such as SPI, IIC, RS-232 by reasonably design, by the setting of microcontroller, realizes the serial communication interface of compatible polytype, various modes.Bring into play the advantage of microcontroller itself simultaneously, adopt the interruption of microcontroller and the mode of operation of microcontroller, realized serial communication interface operation simple and convenient, and the communication interface of the low-power consumption of design and realization serial communication port.
The utility model content
The technical problems to be solved in the utility model provides a kind of serial communication interface communication interface based on microcontroller, by the communication interface of microcontroller is set, the communication interface of the most serial communication interface that can realize, and possess good extensibility and transplantability.
The utility model is achieved through the following technical solutions: a kind of serial communication port based on the RISC microcontroller comprises: the high-speed synchronous serial communication interface that is used for synchronous serial communication; Be used for synchronous asynchronous and send the asynchronous reception transmission of the high-speed synchronous that receives communication interface; By bus and the CPU that described communication interface links to each other, control the communication pattern and the communications status of described communication interface; By the input/output port that bus links to each other with described communication interface, multiplexing described input/output port of described communication interface and peripheral circuit communicate.
Described high-speed synchronous serial communication interface comprises: high speed serialization peripheral communications interface control circuit, communication interface control circuit between high-speed chip, control register, state machine, shift register, buffer register and status register, described control register is selected a ground and is selected communication interface control circuit between described high speed serialization peripheral communications interface control circuit or described high-speed chip, described state machine is according to the control signal of communication interface control circuit between the control signal of described high speed serialization peripheral communications interface control circuit or described high-speed chip, described status register of control bus signal controlling and the described shift register of the output signal of described control register and described CPU, described status register is deposited the state of transmission data according to the control signal of described state machine, CPU writes or reading of data to described buffer register by data bus, described buffer register moves into or shifts out shift register with data, described shift register and described input/output port swap data send interrupt request singal and activation marker signal when displacement finishes or detects start bit stop bit serial communication module to CPU.
In high speed serialization peripheral communications interface control circuit, clock selecting, principal and subordinate select to select to link to each other with described shift register successively with the edge, described clock selecting is selected a kind of principal and subordinate's selection of sending into from multiple internal clocking, external clock is selected to link to each other with the principal and subordinate, the principal and subordinate selects to select a kind of edge of sending in clock and the external clock internally according to mode of operation and selects the clock edge that the edge selects decision to send or receive.
Between high-speed chip in the communication interface control circuit, described shift register links to each other with matching detection with clock selecting respectively, the position is detected and is judged start bit and the stop bit that receives data from input/output port, described clock selecting receives external timing signal from described input/output port, described shift register will be sent into matching detection from the address that described input/output port receives, and the address register value enters matching detection.
The asynchronous reception of described high-speed synchronous sends communication interface and comprises: control register, send control module, receive control module, the transmit status machine, the accepting state machine, transmitter register, receiving register, send shift register and receive shift register, CPU determines that by described control register the asynchronous reception of described high-speed synchronous sends the communication interface mode of operation, described transmit status machine is according to the control signal of control register, send the control signal of control module and the control signal decision duty of CPU, and the content of transmitter register write the transmission shift register, sending module sends interrupt request singal and activation marker signal to CPU, described accepting state machine is according to the control signal of control register, receive the control signal of control module and the control signal decision duty of CPU, and the content of importing described reception shift register arrives the reception buffer register, receiver module is to sending CPU interrupt request singal and activation marker signal, described transmission shift register and reception shift register and described input/output port swap data.
Described control register comprises transmit control register and receives control register that described control register links to each other with described Baud rate generator, the speed of decision transmission or reception data.
The asynchronous reception of described high-speed synchronous sends communication interface and also comprises Baud rate generator, the synchronous asynchronous selector switch, the driven selection of start bit stop bit selector switch and master control, described Baud rate generator baud rate output is exported synchronous clock for the baud rate shift clock of shift register use with through the baud rate of synchronous asynchronous selector switch, described synchronous asynchronous selector switch output synchrodata or asynchronous data, asynchronous data is through start bit stop bit selector switch and comprise start bit stop bit information, to send data and be sent to input/output port, the driven selection of described master control is according to active signal and driven signal output active clock or input slave side clock.
Perhaps, the asynchronous reception of described high-speed synchronous sends communication interface and also comprises Baud rate generator, the synchronous asynchronous selector switch, start bit stop bit selector switch, the driven selection of master control, frequency divider and Data Detection, described Data Detection is sampled to the clock signal that described Baud rate generator produces, synchronous asynchronous selector switch input synchrodata and asynchronous data, the input data select to separate synchrodata or asynchronous data through synchronous asynchronous, asynchronous data selects also to comprise start bit stop bit information through the start bit stop bit, the clock of Baud rate generator output through behind the frequency divider as the master clock of shift register and the transfer clock of communicating by letter.
Described high-speed synchronous serial communication interface comprises the IDLE control circuit, by external timing signal and inner activation signal control IDLE control circuit duty.
The asynchronous reception of described high-speed synchronous sends communication interface and comprises the IDLE control circuit, by external timing signal and inner activation signal control IDLE control circuit duty.
A kind of serial communication port of the utility model based on the RISC microcontroller, as submodular circuits, design is at chip internal, by the register of microcontroller is set with interface circuit, realize the communication module circuit working, reach the purpose of communication by universal input and output port.The work of communication module circuit is relatively independent, the mode of operation simple and convenient, after reasonably combined peripheral module resource, can be integrated in various embedded systems, the monolithic system (SOC), be widely used in consumer electronics, communication, satnav and fields such as audio frequency, video.
Description of drawings
Fig. 1 is MCU and serial communication interface circuit connection diagram.
Fig. 2 is a high-speed synchronous serial communication interface HSSP circuit diagram.
Fig. 3 is that the asynchronous reception of high-speed synchronous sends communication interface HSART circuit diagram.
Fig. 4 is a high speed serialization peripheral communications interface HSPI control circuit principle of work synoptic diagram.
Fig. 5 is a communication interface HIIC control circuit principle of work synoptic diagram between high-speed chip.
Fig. 6 is the synoptic diagram that the asynchronous reception of high-speed synchronous sends communication interface HSART transmitter.
Fig. 7 is the synoptic diagram that the asynchronous reception of high-speed synchronous sends communication interface HSART transmitter.
Fig. 8 is that communication module activates the microcontroller principle schematic.
Embodiment
As shown in Figure 1, it is two of MCU inside independently function module circuits that the asynchronous reception of high-speed synchronous serial communication interface HSSP and high-speed synchronous sends communication interface HSART, is arranged so that high-speed synchronous serial communication interface HSSP and the asynchronous reception of high-speed synchronous sends communication interface HSART and the outside is carried out data communication simultaneously by CPU.By 8 bit data bus 1 and control bus 2, control bus 2 comprises clock signal, register read write signal etc., CPU is provided with the related register of communication interface circuit, makes the asynchronous reception of high-speed synchronous serial communication interface HSSP and high-speed synchronous send the work of communication interface HSART module.Send in the communication interface HSART course of work in the asynchronous reception of high-speed synchronous, will produce relevant marking signal 3, comprise interrupt identification signal, activation marker signal or the like, all will feed back to the correlation module of CPU; Equally, the marking signal of high-speed synchronous serial communication interface HSSP generation is 4.CPU carries out the input and output setting by 2 and 3 pairs of general input and output I/O mouths, simultaneously according to the control register setting of asynchronous reception transmission communication interface HSART of high-speed synchronous and high-speed synchronous serial communication interface HSSP, determines the communication port type of I/O mouth.The communication port that setting completed, transfer bus by the asynchronous reception transmission of high-speed synchronous communication interface HSART between asynchronous reception transmission communication interface HSART of high-speed synchronous and IO is 5, carry out data and clock transfer, the transfer bus of same high-speed synchronous serial communication interface HSSP is 6.Described high-speed synchronous serial communication interface HSSP comprises communication interface HIIC control circuit between high speed serialization peripheral communications interface HSPI control circuit and high-speed chip.Because high speed serialization peripheral communications interface HSPI control circuit is under master mode, can adopt multiple clock signal as transfer clock, the utility model high speed serialization peripheral communications interface HSPI control circuit can also pass through the timing of the timer of microcontroller and export 7 as transfer clock except the clock signal by the CPU input.
As shown in Figure 2, CPU carries out assignment by the control register of data bus 1 and 2 pairs of HSSP modules of control bus, a kind of circuit working that control register is selected in HSPI control circuit or the HIIC control circuit by control bus 10,11, HSPI and HIIC can not work simultaneously, and the same time can only be selected wherein a kind of communication mode.Control register output signal 10 is selected the mode of operation of HSPI, comprises active, driven selection and the speed of transmitting data.Wherein select output 7 that speed comprised timer as transfer clock, to reach the requirement of the peripheral slow chip communication of coupling.Select the HSPI pattern, be operated in the communication mode of HSPI, in conjunction with control bus 2 and the control register output signal 15 of CPU, make state machine start working simultaneously by the control signal 12 designated state machines of HSPI.The work of state machine has determined the work of shift register by state machine output control signal 4, the serial that comprises data sends, receives and fetches data, writes data and carry out exchanges data or the like by 6 with input/output port from the buffering register read, another effect of state machine is exactly the status register by 4 control HSSP, this status register is deposited the state of transmission data, and these states all to be state by state machine provide.Equally, the principle of work of HIIC and the principle of work of HSPI are similar, and control register output control signal 11 is selected the mode of operation of HIIC, comprise active, driven and principal and subordinate's the selection and the speed of transmission data.Select the HIIC pattern, be operated in the communication mode of HIIC by the control signal 12 designated state machines of HIIC, transmission data principle is the same with HSPI.HSSP comprises that by the duty of detected state machine data shift finishes and HIIC mode detection start bit stop bit, and HSP sends interrupt request singal and activation marker signal to CPU.
As shown in Figure 3, CPU carries out assignment by the control register of data bus 1 and 2 pairs of HSART modules of control bus, and this control register comprises transmit control register and receive control register that both must work together, synthesize the HSART control register.The HSART control register is selected HSART control to enable the transmission of HSART by HSART control bus 18 or is received mode of operation, under asynchronous pattern, send and receive and to work simultaneously, also can choose and send or receive a kind of pattern work, under synchronous mode, sending and receiving to have a kind of communication mode to work at one time.In conjunction with the control signal 19 that sends control module and the control signal 18 of CPU control signal 2 and HSART control register, determine the duty of state machine jointly.The output control signal 20 of transmit status machine, part control sends the control signal 20 of the work of shift register, and another part sends the marking signal 16 of interrupt request and activation to CPU.Equally, in conjunction with the control signal 24 that receives control module and the control signal 18 of CPU control signal 2 and HSART control register, determine the duty of state machine jointly.The output control signal 22 of status register, part control sends the control signal 23 of the work of shift register, and another part sends the marking signal 17 of interrupt request and activation to CPU.16 and 17 have formed 3 of Fig. 1.The process that sends only needs CPU to write the data of transmission by 1 and 2 to transmitter register, start sending module, data will write shift register by 25 automatically, and shift register also arrives input/output port by 27 according to 19 and 21 control signal, communicates with peripheral circuit.Equally, the process that receives only need start receiver module, the data of peripheral circuit move into input/output port, arrive the reception shift register by 28, waiting for that a byte data moves finishes, move into receiving register by 26 automatic data with shift register, CPU reads the data that write reception by 1 and 2 to receiving register.
As shown in Figure 4, adopt master mode, clock is produced by inside, and multiple internal clocking 37 is arranged, and can select a kind of clock 35 by selector switch, and multiple clock has extensibility, to satisfy different transfer rates.Adopt follower mode, clock provides 36 by the outside.Select decision clock signal 34 through the principal and subordinate.Initiatively, the clock of driven two kinds of patterns is along selecting, promptly select rising edge reception, negative edge to send, still select rising edge transmission, negative edge to receive, transmit clock signal is 33,33 also is under the aggressive mode simultaneously, the clock signal of circuit transmission to the periphery.Send and receive a shared buffer register, when sending, CPU writes data by 1 and 2 to buffer register, and the data of transmission will move into shift register automatically through data channel 14.Equally, receive a byte data and finish, data will move into buffer register from shift register automatically by 14, and CPU passes through 1 and 2 with data read.The data that send shift out from output terminal 31, and the data of reception move into from input end 30.Under follower mode, can select chip selection signal 32, support many slave modes of HSPI communication.
As shown in Figure 5, the utility model HIIC aggressive mode is realized by the port input-output characteristic is set, but is possessed very strong driven communication function.Send data and only need cooperate by 1 and 2 data are write buffer register, buffer register moves into shift register by data channel 14 with data, waits for external clock 51, sends by turn by the data of data line 50 with shift register.Carry out burr by clock selecting with 51 and filter, export comparatively stable clock 52.Receive data and comprise reception start bit, stop bit, read-write, address, data, the start bit, the stop bit that receive will detect by the position to be judged, the address that receives enters matching detection by 8 bit data passages 53, address register enters matching detection by 8 bit data passages 54, the address of the two compares in match detection circuit inside, receive data and will move into buffer register, arrive microcontroller inside by data bus.Address register also is to be affiliated on the data bus of microcontroller and the control bus, and CPU can this register of directly address.
As shown in Figure 6, there is a Baud rate generator HSART inside, and Baud rate generator provides the tranmitting data register of asynchronous transmission device and the tranmitting data register of synchronous master control transmitter.Send data and only need data be write buffer register by 1 and 2 cooperations, buffer register moves into shift register by 8 bit data passages 25 with data, if asynchronous transmission is exported asynchronous data 61 and synchrodata 63 by data channel 60 through the synchronous asynchronous selector switch.Because byte data of asynchronous transmission comprises start bit and stop bit, so through start bit stop bit selector switch, the transmission data 63 that will remain on the synchronous asynchronous selection earlier after the transmission start bit again transfer to input/output port, data send and finish, and send a stop bit from start bit stop bit selector switch.Synchronized transmission is comparatively simple comparatively speaking, by turn the data 60 that send is selected by synchronous asynchronous, and output data 63 is just finished data to port and sent.The clock of asynchronous transmission directly produces 62 by baud rate.Synchrotransmitter, data are by selecting synchronously data directly to be transferred to input/output port.The clock of synchronized transmission need be judged initiatively and be driven, internal clocking produces baud rate output clock 67 and baud rate shift clock 62 by baud rate, 62 provide the internal displacement register to use, 67 through the synchronous asynchronous selector switch, output synchronous clock 68 arrives port through the driven selection output of master control master control synchronous clock 69.Driven tranmitting data register provides external clock 64 by the outside, through selecting slave side clock 65 and driven synchronous clock 66 to shift register.
As shown in Figure 7, there is a Baud rate generator HSART inside, and Baud rate generator provides the receive clock of asynchronous receiver and the receive clock of synchronous master control receiver.Reception needs baud rate to produce 70 pairs of port datas 71 of high frequency clock to sample, the input data 72 that obtain receiving by Data Detection.Synchronous asynchronous is selected 72 signals are separated, if asynchronous signal 73 also needs to select just can enter shift register through the start bit stop bit, synchronizing signal 74 directly enters shift register.Shift register moves into receiving register by data channel 26 with data, and receiving register has also comprised 2 grades of FIFO, can receive a plurality of data simultaneously.Microcontroller can be by 1 and 2 with the data read that receives.70 through frequency divider clocking low-frequency clock 80,80 clocks as the shift register master control, select by synchronous asynchronous simultaneously, produce synchronizing clock signals 79, if, will send master control synchronous clock 78, as the transfer clock of whole communication for master control receives.Driven reception produces slave side clock 76 from port input clock 75 through the driven selection of master control, selects to produce the shift clock of driven synchronous clock 77 as shift register through synchronous asynchronous simultaneously.
As shown in Figure 8, the serial communication of follower mode can be worked under the IDLE pattern.Adopt external clock, realize the state transitions of data shift and state machine, thereby realize that data send or receive.By the interrupt response that produces in Data Receiving, the process of transmitting, can change the control signal of chip id LE pattern, realize activating the IDLE pattern, MCU enters normal mode of operation.Crystal oscillator input clock 90 is shielded by signal 92 under sleep pattern, so that can't obtain being input to MCU clock internal signal 91, has realized stopping the inner most of modular circuit work of MCU, reaches the purpose of low-power consumption.The serial communication of follower mode is worked under the IDLE pattern, has only very little a part of circuit participation work of the use external clock of communication module circuit in the microcontroller, finishes the communication of data under the very low situation of power consumption.In the process of communication, produce look-at-me 93,, the microcontroller that is operated in the IDLE pattern is activated through the IDLE control circuit.
A kind of serial communication port of the utility model based on the RISC microcontroller, as submodular circuits, design is at chip internal, by the register of microcontroller is set with interface circuit, realize the communication module circuit working, reach the purpose of communication by universal input and output port.The work of communication module circuit is relatively independent, the mode of operation simple and convenient.Serial communication interface comprises that mainly high-speed synchronous serial communication interface and the asynchronous reception of high-speed synchronous send communication interface.The high-speed synchronous serial communication interface comprises communication interface between high speed serialization peripheral communications interface and high-speed chip, and the asynchronous reception of high-speed synchronous sends communication interface and comprises that high-speed synchronous receives the transmission communication interface and high-speed asynchronous reception sends communication interface.Each communication interface all has several communication patterns, has comprised the fundamental type of all serial communication interfaces of present microcontroller basically.
In addition, another feature of the present utility model is exactly the function that all serial communication interfaces all possess interrupt request, and according to low power consumption design method, driven communication pattern can be under the IDLE pattern at microcontroller and transmit data, interruption in the communication process effectively can activate the microcontroller that is in the IDLE pattern, makes it enter normal mode of operation.Serial communication interface based on microcontroller of the present utility model after the reasonably combined peripheral module resource, can be integrated in various embedded systems, the monolithic system (SOC), is widely used in consumer electronics, communication, satnav and fields such as audio frequency, video.
Claims (10)
1, a kind of serial communication port based on the RISC microcontroller is characterized in that, comprising:
The high-speed synchronous serial communication interface that is used for synchronous serial communication;
Be used for synchronous asynchronous and send the asynchronous reception transmission of the high-speed synchronous that receives communication interface;
By bus and the CPU that described communication interface links to each other, control the communication pattern and the communications status of described communication interface;
By the input/output port that bus links to each other with described communication interface, multiplexing described input/output port of described communication interface and peripheral circuit communicate.
2, serial communication port as claimed in claim 1, it is characterized in that, described high-speed synchronous serial communication interface comprises: high speed serialization peripheral communications interface control circuit, communication interface control circuit between high-speed chip, control register, state machine, shift register, buffer register and status register, described control register is selected a ground and is selected communication interface control circuit between described high speed serialization peripheral communications interface control circuit or described high-speed chip, described state machine is according to the control signal of communication interface control circuit between the control signal of described high speed serialization peripheral communications interface control circuit or described high-speed chip, described status register of control bus signal controlling and the described shift register of the output signal of described control register and described CPU, described status register is deposited the state of transmission data according to the control signal of described state machine, CPU writes or reading of data to described buffer register by data bus, described buffer register moves into or shifts out shift register with data, described shift register and described input/output port swap data send interrupt request singal and activation marker signal when displacement finishes or detects start bit stop bit serial communication module to CPU.
3, serial communication port as claimed in claim 2, it is characterized in that, clock selecting, principal and subordinate select to select to link to each other with described shift register successively with the edge, described clock selecting is selected a kind of principal and subordinate's selection of sending into from multiple internal clocking, external clock is selected to link to each other with the principal and subordinate, the principal and subordinate selects to select a kind of edge of sending in clock and the external clock internally according to mode of operation and selects the clock edge that the edge selects decision to send or receive.
4, serial communication port as claimed in claim 2, it is characterized in that, described shift register links to each other with matching detection with clock selecting respectively, the position is detected and is judged start bit and the stop bit that receives data from input/output port, described clock selecting receives external timing signal from described input/output port, described shift register will be sent into matching detection from the address that described input/output port receives, and the address register value enters matching detection.
5, serial communication port as claimed in claim 1, it is characterized in that, the asynchronous reception of described high-speed synchronous sends communication interface and comprises: control register, send control module, receive control module, the transmit status machine, the accepting state machine, transmitter register, receiving register, send shift register and receive shift register, CPU determines that by described control register the asynchronous reception of described high-speed synchronous sends the communication interface mode of operation, described transmit status machine is according to the control signal of control register, send the control signal of control module and the control signal decision duty of CPU, and the content of transmitter register write the transmission shift register, sending module sends interrupt request singal and activation marker signal to CPU, described accepting state machine is according to the control signal of control register, receive the control signal of control module and the control signal decision duty of CPU, and the content of importing described reception shift register arrives the reception buffer register, receiver module is to sending CPU interrupt request singal and activation marker signal, described transmission shift register and reception shift register and described input/output port swap data.
6, serial communication port as claimed in claim 5 is characterized in that, described control register comprises transmit control register and receive control register that described control register links to each other with described Baud rate generator, the speed of decision transmission or reception data.
7, serial communication port as claimed in claim 5, it is characterized in that, the asynchronous reception of described high-speed synchronous sends communication interface and also comprises Baud rate generator, the synchronous asynchronous selector switch, the driven selection of start bit stop bit selector switch and master control, described Baud rate generator baud rate output is exported synchronous clock for the baud rate shift clock of shift register use with through the baud rate of synchronous asynchronous selector switch, described synchronous asynchronous selector switch output synchrodata or asynchronous data, asynchronous data is through start bit stop bit selector switch and comprise start bit stop bit information, to send data and be sent to input/output port, the driven selection of described master control is according to active signal and driven signal output active clock or input slave side clock.
8, serial communication port as claimed in claim 5, it is characterized in that, the asynchronous reception of described high-speed synchronous sends communication interface and also comprises Baud rate generator, the synchronous asynchronous selector switch, start bit stop bit selector switch, the driven selection of master control, frequency divider and Data Detection, described Data Detection is sampled to the clock signal that described Baud rate generator produces, synchronous asynchronous selector switch input synchrodata and asynchronous data, the input data select to separate synchrodata or asynchronous data through synchronous asynchronous, asynchronous data selects also to comprise start bit stop bit information through the start bit stop bit, the clock of Baud rate generator output through behind the frequency divider as the master clock of shift register and the transfer clock of communicating by letter.
As arbitrary described serial communication port among the claim 1-8, it is characterized in that 9, described high-speed synchronous serial communication interface comprises the IDLE control circuit, by external timing signal and inner activation signal control IDLE control circuit duty.
As arbitrary described serial communication port among the claim 1-8, it is characterized in that 10, the asynchronous reception of described high-speed synchronous sends communication interface and comprises the IDLE control circuit, by external timing signal and inner activation signal control IDLE control circuit duty.
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| Application Number | Priority Date | Filing Date | Title |
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| CNU2005200446926U CN2833703Y (en) | 2005-08-31 | 2005-08-31 | RISC microprocessor-based serial communication port |
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| CNU2005200446926U CN2833703Y (en) | 2005-08-31 | 2005-08-31 | RISC microprocessor-based serial communication port |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104503934A (en) * | 2014-12-02 | 2015-04-08 | 天津国芯科技有限公司 | Extendable serial transmission device |
| CN106773954A (en) * | 2016-12-15 | 2017-05-31 | 深圳市博巨兴实业发展有限公司 | A kind of operating mode control method in microcontroller chip |
| CN112685355A (en) * | 2021-01-11 | 2021-04-20 | 龙迅半导体（合肥）股份有限公司 | String adding device |
-
2005
- 2005-08-31 CN CNU2005200446926U patent/CN2833703Y/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104503934A (en) * | 2014-12-02 | 2015-04-08 | 天津国芯科技有限公司 | Extendable serial transmission device |
| CN106773954A (en) * | 2016-12-15 | 2017-05-31 | 深圳市博巨兴实业发展有限公司 | A kind of operating mode control method in microcontroller chip |
| CN106773954B (en) * | 2016-12-15 | 2019-05-28 | 深圳市博巨兴实业发展有限公司 | A kind of operating mode control system in microcontroller chip |
| CN112685355A (en) * | 2021-01-11 | 2021-04-20 | 龙迅半导体（合肥）股份有限公司 | String adding device |
| CN112685355B (en) * | 2021-01-11 | 2022-03-18 | 龙迅半导体（合肥）股份有限公司 | String adding device |
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