CN2765320Y - 制造介电层的系统 - Google Patents
制造介电层的系统 Download PDFInfo
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- CN2765320Y CN2765320Y CNU2004200843502U CN200420084350U CN2765320Y CN 2765320 Y CN2765320 Y CN 2765320Y CN U2004200843502 U CNU2004200843502 U CN U2004200843502U CN 200420084350 U CN200420084350 U CN 200420084350U CN 2765320 Y CN2765320 Y CN 2765320Y
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Abstract
本实用新型提供一种制造介电层的系统。包括:一超临界制程环境,是包含一于一制程腔室中的基底,该制程腔室内具有一制程温度与一制程压力;一控制装置,是控制该制程腔室于一超临界状态;一流体扰乱装置,是提供一气胶态的非超临界流体至该制程腔室中;以及一加热装置,是加热该基底至一超临界温度,其中该流体是因该制程腔室中的该制程压力与该制程温度而转变为一超临界流体,且藉由该基底与该超临界流体的接触形成一介电层。
Description
技术领域
本实用新型是有关于一种制造集成电路的系统,特别是有关于一种于半导体基底上制造介电层的系统。
背景技术
集成电路是由设置于基底上的一或多个装置(电路组件)所构成。集成电路的主动组件密度(例如每一集成电路面积上所含装置的数目)与功能性密度(例如每一集成电路面积上所含内联机装置的数目)均受限于半导体的制程步骤,在制程上影响装置形成的限制包括有最微尺寸的制作,即制作具有最小尺寸的组件或导线,以及有关于介电层的形成,该介电层是用来隔离集成电路中不同的导电层与装置。
介电层是集成电路中用来隔离不同导体或半导体区域的物质,但随着组件尺寸不断缩小,深宽比不断增加,介电层的制作已愈显困难,困难其一即是须在不超过半导体基底热预算(制程中于降解发生前所接收的最大热能量)的情况下,提供一均匀形成的介电层,因微小组件的制作,须相对低的热预算以避免掺质自掺杂区域扩散出来,然而,传统制造介电层的方法,其所需的制程温度与持续时间均超过目前微小装置的热预算。
另一困难则是须使介电层于一窄且深的沟槽中形成均一的步阶效果,例如利用传统方法于一深沟槽中形成一介电层,即会导致填入深度不均或分布不完全,造成集成电路的表现与稳定性不佳。
因此,发展出一套可于相对低温改善介电层形成的系统是必须的。
发明内容
有鉴于此,本实用新型的目的是提供一种制造介电层的系统,以克服传统制造介电层控制工艺温度热预算不佳以及介电层填入深度不均匀的缺陷,该制造介电层的系统包括:一超临界制程环境,是包含一于一制程腔室中的基底,该制程腔室内具有一制程温度与一制程压力;一控制装置,是控制该制程腔室于一超临界状态;一流体扰乱装置,是提供一气胶态的非超临界流体至该制程腔室中;以及一加热装置,是加热该基底至一超临界温度,其中该流体是因该制程腔室中的该制程压力与该制程温度而转变为一超临界流体,且藉由该基底与该超临界流体的接触形成一介电层。
由此,本实用新型的制造介电层的系统,有效的克服了传统制造介电层工艺中所需的制程温度与持续时间均超过目前微小装置的热预算的缺陷,采用本实用新型的制造介电层的系统于一深沟槽中形成一介电层时,可以形成深度均匀并且分布完整的介电层,由此制造的集成电路可以有非常好的表现与稳定性。
附图说明
图1是根据本实用新型的一实施例,介电层制程的流程图。
图2是根据本实用新型的一实施例的相图。
图3至图7b是根据本实用新型的一实施例,不同装置的剖面示意图。
图8是根据本实用新型的一实施例,高压反应系统的示意图。
符号说明:
100~形成介电层的方法;
102~产生超临界制程条件;
104~导入流体至制程腔室;
106~维持超临界状态;
108~停止供应流体至制程腔室;
110~检视介电层是否合乎制程要求;
200~温度与压力关系图;
202~X轴;
204~Y轴;
206~超临界状态;
208、210~次临界状态;
300、504~场效晶体管;
302、404、506、602、702~基底;
304~掺杂井;
306、508、606~介电层;
308~导电层;
310~间隙壁;
400~LOCOS结构;
402~介电隔离区;
500~镶嵌式结构;
502~内联机;
600~半导体结构;
604~沟槽;
700~电机微机械装置;
704~第一牺牲层;
706~结构层;
708~第二牺牲层;
800~高压反应系统;
802、810、812、816、818~阀;
804~制造塔;
806~工作塔;
808~流体帮浦;
814~预热装置;
820~制程腔室;
822~压力计;
824~腔室压力调节装置;
826~低压膨胀装置;
828~排放系统。
具体实施方式
为让本实用新型的上述目的、特征及优点能更明显易懂,下文特举一较佳实施例,并配合所附图式,作详细说明如下:
本实用新型是有关于一种制造集成电路的系统,特别是有关于一种于半导体基底上制造集成电路的系统。以下是透过各实施方式或实施例揭露本实用新型的不同特征,其中关于组成与排列的特殊实施例是用以简化说明而非限定本实用新型,此外,本实用新型在不同实施例中,重复使用相同的标号或字母,使说明达简化、清晰的目的,而非指陈不同实施例或图示间的关系。
请参阅图1的制程流程。根据本实用新型的一实施例,于一半导体基底上形成一介电层的方法100,在本实施例中,该半导体基底是置于一制程腔室内的一底座上,于后会有详细的描述,方法100是利用一超临界流体(如图2所示)来形成该介电层。
仍请参阅图2,图2是一温度(代表X轴202)与压力(代表Y轴204)的关系图200,若以一流体例如为水作说明,当温度达Ts,压力达Ps时,该流体会进入一超临界状态206,在该超临界状态206中,液态流体的密度会与气态相同,且该流体同时拥有液体与气体的性质。例如,水的超临界状态,其温度大体为摄氏374度,压力大体为221大气压。次临界状态208与210表示仅压力达Ps,而温度未达Ts(208),或是仅温度达Ts,而压力未达Ps(210)。
续请参阅图1,方法100是以产生超临界制程条件(例如温度或压力)的步骤102为起始步骤,若本实施例以水作为试验流体,则在该制程腔室中会产生温度大体为摄氏374度,压力大体为221大气压的一水的超临界状态。
超临界条件可由数种方式产生,例如,仅须维持该制程腔室内的压力与邻近该基底的温度于该超临界范围,而腔室内其它部分的温度可停留在一次临界范围,此种不须维持腔室温度一致性的方式,保留了更多制程上的弹性空间。又例如该基底可藉由一置于该制程腔室内的热底座加热至该超临界温度,其中该底座可利用包埋于该底座内或置于该底座附近的铁线圈加热。在一实施例中,该基底透过一照射一红外线于该半导体基底上的快速热制程加热至该超临界温度,其中该红外线的波长是与硅或其它物质的吸收波长相同。
步骤104是导入该流体于该制程腔室中,例如可藉由一耦接一气化模块(如图8所示)的液体质流控制器计量供给水并气化之,其中该气化模块是利用包含一惰性气体或氧气的气体产生一流体蒸气。另一导入该流体于该制程腔室中的方法是导入一气胶态流体,该气胶态流体可藉由一喷雾装置或一超声波分散装置于该超临界状态下形成,当该气胶态流体导入该制程腔室时,该流体会因该腔室内或该基底表面压力与温度的缘故,进入邻近于该基底的超临界状态区域。
步骤106是该半导体基底暴露于该流体时,维持该超临界状态以利该介电层形成于该基底上,该流体持续供应至该基底,待该介电层达到一理想厚度为止。
步骤108是停止供应该流体至该制程腔室,步骤110是决定该介电层是否满足制程要求(例如理想厚度或均匀分布等),依步骤110的检视结果,若该介电层满足要求,则方法100可终止,然若不满足,方法100须重复步骤104再次导入水于该制程腔室中。
可利用步骤104循环供应该流体至该基底,例如经历供应水至该基底的一t1期间以及停止供应水的另一t2期间。步骤104至110可重复执行,待该介电层到达一理想厚度为止。由于透过上述重复执行的步骤会使该介电层厚度超过理想值的可能性变得很小,遂该提供流体的循环步骤可有效控制该介电层的厚度,且该方法亦可提供一致密的介电层。
藉由一包含超临界流体、一硅基底与一湿氧化制程的方法100所形成的一介电层例如为二氧化硅,二氧化硅可利用一湿氧化步骤如: 热成长获得,然而,传统的湿氧化方法须使用一相对高的制程温度(例如摄氏1150度)及一相对低的制程压力(例如1大气压),且其成长速率相对缓慢,例如每分钟成长1~2埃。具高温与低成长速率的传统湿氧化制程对低热预算的装置会有不良影响,传统湿氧化制程的缺点尚包括高能量消耗及于该制程腔室中无法获得均一温度。
如方法100所示,改善传统湿氧化制程的方式是于该湿氧化反应中使用超临界流体,通入的超临界流体是有助于介电层的形成。与传统湿氧化制程相比,超临界流体氧化可在一相对低的温度下实施,例如适合氧化的超临界流体其压力大体为22.1百万帕,温度大体摄氏374度,遂可看出本实用新型的制程温度与传统湿氧化须摄氏1150度有明显差降。
使用超临界流体亦可增加氧化速率,例如即使是结合较低制程温度的超临界制程,其氧化速率仍高于传统的湿氧化方法,而此氧化速率的增加是由于水的密度降低,使得扩散与离子迁移速率增加。例如制程条件在温度大体摄氏374度,压力大体221大气压的情况下,会使暴露于超临界水的硅其氧化速率达每分钟5埃以上。
利用超临界水亦可形成一步阶较佳的介电层,特别对高深宽比的组件具有其效果,超临界水低黏度与低表面张力的特性,使其可穿透窄沟槽并使步阶均一,遂即使极窄、深的组件,仍可获得一步阶均匀的氧化层。
由于超临界流体低极性与低表面张力的特性,使其有能力移除各种有机物质,达到清洁半导体基底表面的效果,该低极性特性是因水在超临界制程条件下,失去大量氢键所致,而使制程腔室中非极性的有机物溶于超临界水或与氧气结合,之后再藉由水、二氧化碳或其它流体将非极性有机物带离该基底。
请参阅图3,说明一具有利用图1方法100制造的介电层的集成电路装置,例如一场效晶体管(FET)300,该FET是包括一基底302,例如为一硅、类钻碳、绝缘层上覆硅(SOI)或锗化硅基底,基底302可掺杂P型如磷或N型如硼的掺质,而形成基底302中P型或N型的掺杂井304,所述多个掺质可藉如离子布植、气体扩散、CVD、PECVD、ALD或其它适合的制程方法嵌入该基底中。
该FET是包括一包含多个硼掺杂区与重氢-硼复合区的类钻碳基底302,其中所述多个硼掺杂区包含多个P型区,而所述多个重氢-硼复合区则包含多个N型区。所述多个硼掺杂区与重氢-硼复合区可形成基底302上多个微电子装置的多个源/汲极区。
所述多个硼掺杂区(硼掺杂类钻碳)可于一真空制程环境中藉由实施一碳/重氢比大体介于0.1%~5.0%的高密度电浆而形成,硼布植制程是由含硼气体与含碳/氢气体的混合气体提供掺质,其中含硼气体是包含B2H6、B2D6或其它含硼的气体,硼布植的浓度是依据含硼气体的量而定。该制程环境的压力范围大体介于0.1毫托~500托,基底302是置于温度大体介于摄氏150度~1100度的环境中,该高密度电浆是由一微波电子回旋共振(ECR)电浆源、一螺旋波电浆源、一感应耦合电浆(ICP)源或其它高密度电浆源所产生,例如ECR电浆源可利用大体介于800瓦~2500瓦的微波范围。
基底302的所述多个N型重氢-硼复合区是对硼掺杂区实施一氘电浆而形成。场效晶体管300的位置是被一光罩(未显示)所覆盖,而未被覆盖的所述多个硼掺杂区则以一氘电浆处理之。氘离子是提供一悬键(dangling bond)末端,使P型区转变为N型区。氘可由氚、氢或其它含氢气体所取代。N型区(重氢-硼复合区)的浓度可藉由通过基底302的直流电流或射频偏压所控制。
之后,利用如图1的方法100于掺杂井304之间形成一介电层306,介电层306的厚度大体介于1~100埃,接着,对介电层306进行图案化及蚀刻,以形成一形状、厚度均符合要求的FET栅介电层,续于介电层306上沉积一导电层308,以形成一栅极,导电层308是由掺杂的复晶硅或是一利用温度介于摄氏700~900度的热氧化炉管形成的金属硅化物所构成,一热退火制程是将该基底置于温度大体介于摄氏450~1000度的环境中,持续大体3~60秒。
接着,利用如图1的方法100形成一围绕介电层306与导电层308的间隙壁310,以方法100制作间隙壁310的优点包括超临界水的氧化不须如传统氧化沉积制程例如TEOS的CVD、ALD或PECVD将FET300置于较高温的环境中,另利用超临界水氧化形成间隙壁的过程,亦可同时清洁导电层308、介电层306、掺杂井304与基底302表面上的残留有机物质。
请参阅图4,说明利用如图1方法100形成的另一半导体结构,图4是一硅的局部氧化(LOCOS)结构400,例如用来隔离集成电路中的主动装置,该LOCOS结构400是包括多个形成于一半导体基底404上的介电隔离区402,介电隔离区402形成的方法可见于图1的制程100中。
请参阅图5,说明利用如图1方法100形成的另一半导体结构,图5是一镶嵌式结构500,镶嵌式结构500是包含多个内联机502,例如导线、接触窗或介层窗,内联机502是连接一半导体基底506上的多个集成电路装置504,例如为FETs,内联机502是形成于介电层508中,介电层508是用于绝缘该内联机508金属与隔离所述多个内联机,而介电层508可藉由图1的方法100形成。内联机502可填入例如铜或一阻障层(未显示)如钽、氮化钽、钛、氮化钛、钛化钨或氮化钨的导电物质,另当超临界流体产生时,该阻障层可减少或防止加热内联机所造成的铜扩散。
请参阅图6,说明利用如图1方法100形成的另一半导体结构,图6是一半导体结构600,结构600是包含一具有多个高深宽比沟槽604的基底602,所述多个沟槽604是被一介电层606所覆盖,其中介电层606可利用图1方法100制得,而沟槽604可用于例如一浮置栅极或可抹除程序只读存储器(EPROM)电极的制作,另沟槽604亦可用来隔离半导体装置的电性。方法100所使用的超临界流体,由于其低黏度与低表面张力的特性,遂可用来填入沟槽604,而助于均一步阶的形成。即使极窄、深的组件如沟槽604,亦可籍此方法制作均匀的氧化层。
请参阅图7a,说明利用图1方法100于电机微机械装置700中形成的一介电层,装置700可为一数字微镜装置、一机械齿轮、一摇杆、一加速装置的核心材料、一测斜装置或一回转装置。微机械装置700是透过如下所述的牺牲层与结构层设置于半导体基底702上。
第一牺牲层704是藉图1的方法100形成,第一牺牲层704是沉积作为结构层706的支持,而待结构层706沉积完成后,即可蚀刻移除该第一牺牲层704。制程100所使用的超临界流体,由于可穿透复杂的裂隙,遂对制作第一牺牲层704相当有帮助。
续请参阅图7b,方法100亦用于第二牺牲层708的制作,于第一牺牲层704移除后,第二牺牲层708是作为保护与悬吊结构层706之用。
请参阅图8,说明一制造并传输超临界流体的高压反应系统800,该制程循环可配合如图1的方法100作说明,首先,开启阀802,以调节由制造塔804进入工作塔806的流体流量,之后,启动流体帮浦808将工作塔806的流体经由一阀810导入一预热装置814,流体可经由阀812进入预热装置814而达到一超临界温度,或是经由邻近阀812的阀816流至预热装置814周围。
接着,开启阀818,使流体进入一载有一基底(未显示)的制程腔室820,制程腔室820内更包含有数个控制超临界流体进入腔室的阀(未显示)。在此期间,可藉由制程腔室820的泄压,更换欲作处理的基底。制程进行中,腔室820内的压力范围大体介于50~800大气压,另一腔室压力调节装置可藉由一压力计与制程腔室820连接,以共同控制腔室压力。
此外,可提供惰性气体如氩气、氮气、氢气或氧气至制程腔室820内与超临界水混合。压力计822与压力调节装置824可控制进入一低压膨胀装置826的水量,其中低压膨胀装置826是保持一低于制程腔室820的温度与压力。一般来说,低压膨胀装置826的温度大体介于摄氏0~32度,压力大体介于15~2000psi。水离开膨胀装置826后,即进入一排放系统828,在排放系统中,压力大体低于1大气压,温度低于膨胀装置826。排放系统828可作为一水的再生系统,水可藉由再生系统828再循环、纯化及再返回工作塔处理。
虽然本实用新型已以较佳实施例揭露如上,然其并非用以限定本实用新型,任何熟习此技艺者,在不脱离本实用新型的精神和范围内,当可作更动与润饰,因此本实用新型的保护范围当视权利要求书所界定者为准。
Claims (3)
1.一种制造介电层的系统,其特征在于,包括:
一超临界制程环境,是包含一于一制程腔室中的基底,该制程腔室内具有一制程温度与一制程压力;
一控制该制程腔室于一超临界状态的控制装置;
一提供一气胶态的非超临界流体至该制程腔室中的流体扰乱装置;以及
一加热该基底至一超临界温度的加热装置,其中该基底与该超临界流体接触形成一介电层。
2.根据权利要求1所述的制造介电层的系统,其特征在于,该流体扰乱装置是一超声波分散装置或一喷雾装置。
3.根据权利要求1所述的制造介电层的系统,其特征在于,加热该基底至一超临界温度的该加热装置是设置邻近于该基底。
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EP2143133A2 (en) * | 2007-04-30 | 2010-01-13 | Nanoscale Components, Inc. | Batch process for coating nanoscale features and devices manufactured from same |
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US20050106895A1 (en) * | 2003-11-17 | 2005-05-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Supercritical water application for oxide formation |
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