CN2746677Y - Telephone conference board - Google Patents
Telephone conference board Download PDFInfo
- Publication number
- CN2746677Y CN2746677Y CN 200420115876 CN200420115876U CN2746677Y CN 2746677 Y CN2746677 Y CN 2746677Y CN 200420115876 CN200420115876 CN 200420115876 CN 200420115876 U CN200420115876 U CN 200420115876U CN 2746677 Y CN2746677 Y CN 2746677Y
- Authority
- CN
- China
- Prior art keywords
- chip
- bus interface
- meeting bridge
- connects
- bridge chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Small-Scale Networks (AREA)
Abstract
The utility model relates to a telephone conference board which comprises a PCI bus interface chip 7, a programmable logic device 6 and an H. 110 bus interface chip 1. The telephone conference board is mainly characterized in that the telephone conference board is provided with conference bridge chips, and the number of the conference bridge chips is equal to or more than two. The optimum number of the conference bridge chips for implementation is four. The four conference bridge chips are a conference bridge chip (2), a conference bridge chip (3), a conference bridge chip (4) and a conference bridge chip (5). The exchange function is realized through an H. 110 bus interface control module and a PCM code stream interconnecting module, thus the 256*256 time slot exchange functions in the telephone conference board can be supported, and meanwhile the 4096 time slot exchange functions of the 512 time slots and a back board in the telephone conference board can be supported. The biggest square number of the single conference of the single telephone conference board is 250. The biggest square number of the single conference in the system is in conformity with the formula of N*250-2*(N-1), N is the number of the telephone conference board inserted in the system, and the full reciprocation can be realized.
Description
Technical field
The utility model relates to the electronic unit of a kind of communication technology aspect, refers in particular to a kind of telephone conference boards based on the meeting bridge chip.In International Patent Classification (IPC), the utility model should be divided into the big class of H04.
Background technology
At present, conference board adopts DSP (digital signal processing Digital Signal Processing) chip+conference software algorithm to realize usually, some also adopts PC software to realize, its shortcoming is: all be subjected to the restriction of running software performance, increase effect of meeting variation along with single game meeting number formulary, therefore the maximum number formulary of single game meeting is restricted, and can not realize complete mutual.
Summary of the invention
The purpose of this utility model is: at the deficiency of prior art, provide the maximum number formulary of a kind of single game meeting not to be subjected to the restriction of performance in principle and can to realize complete mutual telephone conference boards.
The purpose of this utility model is achieved through the following technical solutions:
Described telephone conference boards comprises pci bus interface chip 7, programmable logic device 6, H.110 bus interface chip 1, and main feature is: described telephone conference boards is provided with the meeting bridge chip.
Described pci bus interface chip 7 connects to described programmable logic device 6 by chip selection signal line 1-1, waiting signal line 1-2, reading writing signal line 1-3, reseting signal line 1-4 and 11 bit address holding wire 1-5,3 bit address holding wire 1-6.
Described pci bus interface chip 7 connects to described H.110 bus interface chip 1 by 11 bit address holding wire 1-5 and 10 bit address holding wire 1-9.
Described pci bus interface chip 7 passes through 11 bit address holding wire 1-5, data and control and selects holding wire 1-8 to connect to described meeting bridge chip.
Described pci bus interface chip 7 connects to described H.110 bus interface chip 1 by 8 bit data holding wire 1-7.
Described pci bus interface chip 7 passes through 8 bit data holding wire 1-7, chip selection signal line 1-15 and connects to described meeting bridge chip.
Described programmable logic device 6 connects to described H.110 bus interface chip 1 by reseting signal line 1-10.
Described programmable logic device 6 connects to described H.110 bus interface chip 1 by reading signal lines 1-11.
Described programmable logic device 6 passes through reading signal lines 1-11 and connects to described meeting bridge chip.
Described programmable logic device 6 connects to described H.110 bus interface chip 1 by write signal line 1-12.
Described programmable logic device 6 passes through write signal line 1-12 and connects to described meeting bridge chip.
Described programmable logic device 6 connects to described H.110 bus interface chip 1 by 5 road chip selection signal line 1-13.
Described programmable logic device 6 passes through 5 road chip selection signal line 1-13 and connects to described meeting bridge chip.
Described programmable logic device 6 connects to described H.110 bus interface chip 1 by 3 bit address holding wire 1-6 and 10 bit address holding wire 1-9.
Described meeting bridge chip passes through 8K frame synchronizing signal line 1-16 and connects described H.110 bus interface chip 1.
Described meeting bridge chip passes through 8M clock cable 1-17 and connects described H.110 bus interface chip 1.
Described meeting bridge chip passes through pcm stream output signal line 1-18 and connects described H.110 bus interface chip 1.
Described meeting bridge chip passes through pcm stream input signal cable 1-19 and connects described H.110 bus interface chip 1.
In specific embodiment:
Described meeting bridge chip number 〉=2.
Described meeting bridge chip number can be 4, and it comprises: meeting bridge chip 2, meeting bridge chip 3, meeting bridge chip 4 and meeting bridge chip 5.
Described pcm stream output signal line 1-18 is four meeting bridge chip pcm stream output signal lines, and described pcm stream input signal cable 1-19 is four meeting bridge chip pcm stream input signal cables.
The model L53812-2 of described H.110 bus interface chip 1, the model of described meeting bridge chip 2 is M34116, the model of described meeting bridge chip 3 is M34116, the model of described meeting bridge chip 4 is M34116, the model of described meeting bridge chip 5 is M34116, the model of described programmable logic device 6 is GAL16V8D, and the model of described pci bus interface chip 7 is PCI9030.
Because the utility model has adopted above-mentioned technical scheme, because can adopt the meeting bridge chip of polylith specialty to interconnect, the maximum number formulary of single game meeting is not subjected to the restriction of performance in principle, and can realize complete mutual.The maximum number formulary of the single game meeting of veneer only is subject to the chip-count of meeting bridge on the integrated circuit board, and the single game meeting number formulary that the many more veneers of the meeting bridge chip number that veneer is installed are supported is just many more.And support H.110 bus (a kind of backboard switching bus) on the conference board, can realize interconnection by H.110 bus between the conference board, the maximum number formulary of the single game meeting of whole system only is subject to meeting bridge chip number on the integrated circuit board number installed in the system and the integrated circuit board.
Description of drawings
Accompanying drawing 1 is the circuit connection diagram of a most preferred embodiment of the present utility model.
Accompanying drawing 2 is the fundamental diagrams under the user mode of the present utility model.
Can be clear that from accompanying drawing 1 the utility model comprises: 1 H.110 bus interface chip, 2 meeting bridge chips, 3 meeting bridge chips, 4 meeting bridge chips, 5 meeting bridge chips, 6 programmable logic devices, 7 pci bus interface chips.
Accompanying drawing 2 is the fundamental diagrams under the utility model user mode, will narrate in the back.
Embodiment
Below in conjunction with drawings and Examples the utility model is further specified: accompanying drawing 1 is a most preferred embodiment of the present utility model.As previously mentioned, the utility model comprises 1 H.110 bus interface chip, 2 meeting bridge chips, 3 meeting bridge chips, 4 meeting bridge chips, 5 meeting bridge chips, 6 programmable logic devices and 7 pci bus interface chips altogether.
In this embodiment, the concrete annexation of its each parts is as follows:
Described pci bus interface chip 7 connects to described programmable logic device 6 by chip selection signal line 1-1, waiting signal line 1-2, reading writing signal line 1-3, reseting signal line 1-4 and 11 bit address holding wire 1-5,3 bit address holding wire 1-6.
Described pci bus interface chip 7 connects to described H.110 bus interface chip 1 by 11 bit address holding wire 1-5 and 10 bit address holding wire 1-9.
Described pci bus interface chip 7 passes through 11 bit address holding wire 1-5, data and control and selects holding wire 1-8 to connect to described meeting bridge chip.
Described pci bus interface chip 7 connects to described H.110 bus interface chip 1 by 8 bit data holding wire 1-7.
Described pci bus interface chip 7 passes through 8 bit data holding wire 1-7, chip selection signal line 1-15 and connects to described meeting bridge chip.
Described programmable logic device 6 connects to described H.110 bus interface chip 1 by reseting signal line 1-10.
Described programmable logic device 6 connects to described H.110 bus interface chip 1 by reading signal lines 1-11.
Described programmable logic device 6 passes through reading signal lines 1-11 and connects to described meeting bridge chip.
Described programmable logic device 6 connects to described H.110 bus interface chip 1 by write signal line 1-12.
Described programmable logic device 6 passes through write signal line 1-12 and connects to described meeting bridge chip.
Described programmable logic device 6 connects to described H.110 bus interface chip 1 by 5 road chip selection signal line 1-13.
Described programmable logic device 6 passes through 5 road chip selection signal line 1-13 and connects to described meeting bridge chip.
Described programmable logic device 6 connects to described H.110 bus interface chip 1 by 3 bit address holding wire 1-6 and 10 bit address holding wire 1-9.
Described meeting bridge chip passes through 8K frame synchronizing signal line 1-16 and connects described H.110 bus interface chip 1.
Described meeting bridge chip passes through 8M clock cable 1-17 and connects described H.110 bus interface chip 1.
Described meeting bridge chip passes through pcm stream output signal line 1-18 and connects described H.110 bus interface chip 1.
Described meeting bridge chip passes through pcm stream input signal cable 1-19 and connects described H.110 bus interface chip 1.
The model of described H.110 bus interface chip 1 is L53812-2, the model of described meeting bridge chip 2 is M34116, the model of described meeting bridge chip 3 is M34116, the model of described meeting bridge chip 4 is M34116, the model of described meeting bridge chip 5 is M34116, the model of described programmable logic device 6 is GAL16V8D, and the model of described pci bus interface chip 7 is PCI9030.It may be noted that at this: the model of above-mentioned relevant each device only is the typical case's representative in the middle of the utility model embodiment.Certainly, as long as in the technical solution of the utility model, the device of other model that also can select similarly, function is suitable.
The utility model can be divided into three modules generally: 1) PCM (pulse code modulation pulse code modulation) code stream interconnecting modules: this module comprises H.110 bus interface chip 1, meeting bridge chip 2, meeting bridge chip 3, meeting bridge chip 4, meeting bridge chip 5.Operation principle is: pcm stream transfers to H.110 bus interface chip 1 from the backboard H.110 bus, and H.110 bus interface chip 1 and four meeting bridge chip interconnection lines meet the ST-BUS bus specification.2) meeting bridge control module: this module comprises meeting bridge chip 2, meeting bridge chip 3, meeting bridge chip 4, meeting bridge chip 5, programmable logic device 6 and pci bus interface chip 7.Operation principle is: at first initialization is provided with pci bus interface chip 7, makes its operate as normal; Then, pci bus interface chip 7 output control signals, and process programmable logic device 6 converts part address signal and read-write to chip selection signal, the read-write of meeting bridge chip; Meeting bridge chip 2-4 realizes the conferencing function to required pcm stream signal.3) H.110 bus interface control module: this module comprises H.110 bus interface chip 1, programmable logic device 6, pci bus interface chip 7.Its operation principle is: at first initialization is provided with pci bus interface chip 7, makes its operate as normal; Then, pci bus interface chip 7 output control signals, and process programmable logic device 6 converts part address signal and read-write to chip selection signal, the read-write of H.110 bus interface chip 2; H.110 bus interface chip 1 is realized pcm stream handshaking function.H.110 bus interface chip 1 is supported the local exchange of 256 * 256 time slots and 512 * 4096 time slot backboard functions of exchange.
Accompanying drawing 2 is the fundamental diagrams under the user mode of the present utility model.Its operation principle is as follows:
Local switch digital trunk E1 line inserts the E1 interface chip of relay plate, relay plate converts the PCM signal to, send into the PCMin of the meeting bridge chip of conference board through the exchange of backboard H.110 bus, the conference board chip is formed the meeting-place to the PCMin of input, export the PCMout of meeting bridge chip behind the audio mixing of meeting-place to, exchange to the E1 interface chip of relay plate through the backboard H.110 bus, the E1 interface chip is exported to local switch through the E1 digital trunk.
The utlity model has following technical characterstic:
1. support function of exchange, this function is mutual by H.110 bus interface control module and pcm stream The gang mould piece is realized. 256 * 256 time gas exchange functions in the support plate, simultaneously 512 time slots in the support plate With 4096 time gas exchange functions of backboard.
2. the maximum number formulary of the single game meeting of veneer is 250 sides, the maximum number formulary of single game meeting in the system For: N * 250-2 * (N-1), N is the conference board number that inserts in the system, and can realize complete mutual.
Claims (5)
1. telephone conference boards, described telephone conference boards comprises pci bus interface chip (7), programmable logic device (6), H.110 bus interface chip (1), it is characterized in that: described telephone conference boards is provided with the meeting bridge chip;
Described pci bus interface chip (7) connects to described programmable logic device (6) by chip selection signal line 1-1, waiting signal line 1-2, reading writing signal line 1-3, reseting signal line 1-4 and 11 bit address holding wire 1-5,3 bit address holding wire 1-6;
Described pci bus interface chip (7) connects to described H.110 bus interface chip (1) by 11 bit address holding wire 1-5 and 10 bit address holding wire 1-9;
Described pci bus interface chip (7) passes through 11 bit address holding wire 1-5, data and control and selects holding wire 1-8 to connect to described meeting bridge chip;
Described pci bus interface chip (7) connects to described H.110 bus interface chip (1) by 8 bit data holding wire 1-7;
Described pci bus interface chip (7) passes through 8 bit data holding wire 1-7, chip selection signal line 1-15 and connects to described meeting bridge chip;
Described programmable logic device (6) connects to described H.110 bus interface chip (1) by reseting signal line 1-10;
Described programmable logic device (6) connects to described H.110 bus interface chip (1) by reading signal lines 1-11;
Described programmable logic device (6) passes through reading signal lines 1-11 and connects to described meeting bridge chip;
Described programmable logic device (6) connects to described H.110 bus interface chip (1) by write signal line 1-12;
Described programmable logic device (6) passes through write signal line 1-12 and connects to described meeting bridge chip;
Described programmable logic device (6) connects to described H.110 bus interface chip (1) by 5 road chip selection signal line 1-13;
Described programmable logic device (6) passes through 5 road chip selection signal line 1-13 and connects to described meeting bridge chip;
Described programmable logic device (6) connects to described H.110 bus interface chip (1) by 3 bit address holding wire 1-6 and 10 bit address holding wire 1-9;
Described meeting bridge chip passes through 8K frame synchronizing signal line 1-16 and connects described H.110 bus interface chip (1);
Described meeting bridge chip passes through 8M clock cable 1-17 and connects described H.110 bus interface chip (1);
Described meeting bridge chip passes through pcm stream output signal line 1-18 and connects described H.110 bus interface chip (1);
Described meeting bridge chip passes through pcm stream input signal cable 1-19 and connects described H.110 bus interface chip (1).
2. telephone conference boards according to claim 1 is characterized in that: described meeting bridge chip number 〉=2.
3. according to claim 1,2 described telephone conference boards, it is characterized in that: described meeting bridge chip number is 4, and it comprises: meeting bridge chip (2), meeting bridge chip (3), meeting bridge chip (4) and meeting bridge chip (5).
4. telephone conference boards according to claim 1, it is characterized in that: described pcm stream output signal line 1-18 is four meeting bridge chip pcm stream output signal lines, and described pcm stream input signal cable 1-19 is four meeting bridge chip pcm stream input signal cables.
5. telephone conference boards according to claim 1, it is characterized in that: the model of described H.110 bus interface chip (1) is L53812-2, the model of described meeting bridge chip (2) is M34116, the model of described meeting bridge chip (3) is M34116, the model of described meeting bridge chip (4) is M34116, the model of described meeting bridge chip (5) is M34116, the model of described programmable logic device (6) is GAL16V8D, and the model of described pci bus interface chip (7) is PCI9030.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420115876 CN2746677Y (en) | 2004-12-01 | 2004-12-01 | Telephone conference board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420115876 CN2746677Y (en) | 2004-12-01 | 2004-12-01 | Telephone conference board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2746677Y true CN2746677Y (en) | 2005-12-14 |
Family
ID=35583251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200420115876 Expired - Lifetime CN2746677Y (en) | 2004-12-01 | 2004-12-01 | Telephone conference board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2746677Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100340094C (en) * | 2004-12-01 | 2007-09-26 | 何顺兰 | Telephone conference boards |
-
2004
- 2004-12-01 CN CN 200420115876 patent/CN2746677Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100340094C (en) * | 2004-12-01 | 2007-09-26 | 何顺兰 | Telephone conference boards |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101080073A (en) | A between-module communication circuit and method of dual-mode communication terminal | |
| CN1702658A (en) | IP base LSI designing system and designing method | |
| CN100340094C (en) | Telephone conference boards | |
| CN1956054A (en) | MP3 player of implementing music shared based on blue tooth technology and its method | |
| CN1856123A (en) | System and method for exchanging modules in switch | |
| CN2816907Y (en) | Video/audio frequency input output interfacing card | |
| CN2746677Y (en) | Telephone conference board | |
| CN200947476Y (en) | Motherboard and subcard interlinking system, middle installed backboard and extended connector | |
| CN1893388A (en) | Asynchronous FIFO realizing system and realizing method | |
| CN2694373Y (en) | Double nip wireless network card | |
| CN100344074C (en) | Plate card type echo eliminator | |
| CN2726237Y (en) | Plate card type echo eliminator | |
| CN1869868A (en) | Mainframe board capable of setting different kind of central processor | |
| CN1921476A (en) | Business cascade method and system applied between narrow-band communication equipments | |
| CN2807612Y (en) | ADPCM digital code converter | |
| CN1741657A (en) | Mobile communication terminal with internal memory card earphone and application method thereof | |
| CN1619518A (en) | Half duplex series communication bus external device interface | |
| CN100346326C (en) | Plate card voice recorder | |
| CN1968426A (en) | Apparatus for controlling and managing voice codec chip on user board | |
| CN1324922C (en) | Detecting device for base band signal processing sub system in CDMA communication system | |
| CN1619987A (en) | Device and method for proceeding simulation to time delay | |
| CN2599661Y (en) | Storage card fetch device using SATA interface | |
| CN1362676A (en) | USB control circuit capable of switching path automatically | |
| CN2489384Y (en) | Computer keyboard with card reader | |
| CN1599369A (en) | Physical address conversion device and conversion method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Effective date of abandoning: 20070926 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |