CN1619518A - Half duplex series communication bus external device interface - Google Patents
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Abstract
The present invention provides a half-duplex serial communication bus peripheral equipment interface, including physical layer protocol implementation module, high layer protocol implementation module and interface module; the described interface module is connected with two data wires in SPI bus, namely main equipment input/slave equipment output data wire, and main equipment output/slave equipment input data wire, and also connected with reading data signal wire and writing data signal wire so as to form reading/writing data channel of said interface. Said invention also includes SPI data wire multiplex module.
Description
Technical field
The present invention relates to the serial communication field, (Serial Peripheral Interface, the half duplex series communication bus external device of upper-layer protocol SPI) connects based on serial synchronous peripheral interface in particularly a kind of employing
Technical background
Serial communication is a very important data communication mode between main equipment and the external unit.Compare with parallel communication bus, only need less data line.(Serial PeripheralInterface is a kind of synchronous serial bus that company of Motorola (Motorola) proposes SPI) to serial synchronous peripheral interface, is used for the exchanges data between main equipment and the peripherals.Spi bus is a master-slave communication mechanism, and main equipment is a main equipment, and peripherals is slave unit.Spi bus is made of 4 buses, is respectively serial time clock line (SCK), main equipment input/slave unit output data line (MISO), main equipment output/slave unit input data line (MOSI) and the effective selection wire of slave unit (SSN).And the SPI interface is a kind of simple 8 Bit data synchronous serial interfaces, and this interface is used for quick serial data transmission, sends data and carries out with identical clock frequency with the reception data.Compare with other bus protocol, the spi bus agreement is simple, signal wire is few, transfer rate is high and advantage such as full-duplex communication.
At present, some EEPROM factories have proposed the upper-layer protocol of part based on spi bus.The frame of this upper-layer protocol is made of order, address and data successively, and the SSN high level is the beginning of a frame during to low level.The shortcoming of this upper-layer protocol is not support full duplex transmission; Do not support SPI to interrupt transmission, require promptly that SSN must keep low level in the entire frame transmission course; And because its order and address size are fixed, therefore expense is big in the time of the transmission low volume data, and efficient is low.
Therefore, at present a kind of upper-layer protocol based on spi bus is arranged again, this upper-layer protocol is a kind of master-slave mode full duplex or half-duplex operation agreement, and all transmission are initiated by main equipment, and main equipment can transmit and receive data simultaneously.Support SPI to interrupt transmission, do not require that in the transmission course of entire frame SSN keeps low level always.The frame head variable-length adopts short frame head when the transmission low volume data, improve transfer efficiency.
And adopt the serial communiction bus external equipment interface of this upper-layer protocol, realize that by physical layer protocol module, upper-layer protocol realize that module and interface module constitute.Described physical layer protocol realizes that module is used to receive serial clock signal (SCK), and according to the SPI pattern, clocking outputs to upper-layer protocol and realizes module and interface module; Described interface module connects slave unit and effectively selects signal wire (SSN), main equipment input/slave unit output data line (MISO), main equipment output/slave unit input data line (MOSI) and reading data signal line (RDATA) and write data signal line (WDATA), thereby forms the read/write data path of described serial communiction bus external equipment interface; Described upper-layer protocol realizes that module receives the upper-layer protocol frame, to carry out master-slave mode full duplex or half-duplex data communication; That receive autonomous device simultaneously forces synchronizing signal (FEN), to realize the combined synchronization of master-slave equipment; And output read/write address signal, read/write enable signal.The structure of this serial communiction bus external equipment interface is for spi bus, and signal wire is many, and promptly to carry out mutual signalling channel many with main equipment.And know all that for those skilled in the art when integrated circuit (IC) design, signalling channel of every increase just means that its structure is complicated more, the difficulty of plate level design is higher.
Summary of the invention
The objective of the invention is:, provide a kind of simple and reasonable, half duplex series communication bus external device interface that can reduce plate level design difficulty at the deficiencies in the prior art.
In order to solve the problems of the technologies described above, the technical solution used in the present invention is: a kind of half duplex series communication bus external device interface comprises that physical layer protocol realizes module, upper-layer protocol realization module and interface module;
Described physical layer protocol realizes that module is used to receive serial clock signal, and according to the SPI pattern, clocking outputs to upper-layer protocol and realizes module and interface module;
Described upper-layer protocol realizes that module receives the upper-layer protocol frame, to carry out the half-duplex data communication; Receive the synchronizing signal of forcing of autonomous device, to realize the combined synchronization of master-slave equipment; Also produce read/write address signal, read/write enable signal simultaneously according to the upper-layer protocol frame;
Described interface module connects two data lines in the spi bus, be main equipment input/slave unit output data line and main equipment output/slave unit input data line, and connect reading data signal line and write data signal line, thereby form the read/write data path of this interface;
Also comprise SPI data line Multiplexing module, described SPI data line Multiplexing module is by two data line connection interface module in the spi bus, and be connected with main equipment by the bi-directional data signal wire, thereby finish data interaction between described interface module and the main equipment.
Described SPI data line Multiplexing module can be made of output control module and channel selecting element, described channel selecting element connected in series inserts between bi-directional data signal wire and the SPI data line, described output control module is used to produce the channel selecting control signal, and be input in the channel selecting element, thereby control the conducting state of described SPI data line and bi-directional data signal wire.
Described output control module can be according to the slave unit useful signal, force synchronizing signal, and upper-layer protocol realizes the read-write state signal that module produces, and produces the channel selecting control signal.
When the slave unit useful signal or when forcing synchronizing signal to be high level, when perhaps the read-write state signal is write operation, perhaps the read-write state signal is read operation and when being in the frame head of this read operation, described output control module produces the channel selecting control signal, selects bi-directional data signal wire and the conducting of main equipment output/slave unit input data line.
Described channel selecting element can adopt three-state buffer, and the input end of described three-state buffer connects the SPI data line, and its output terminal connects the bi-directional data signal wire, and its control end input channel is selected control signal.
Described bi-directional data signal wire can be connected with the main equipment output/slave unit input data-interface conducting of output control module.
Described upper-layer protocol realizes that module can comprise bit counter, byte counter, address latch module, write control module and read control module, described upper-layer protocol realizes that the read-write state signal of module output comprises the bit number of bit counter output, the byte number of byte counter output, write the status signal of writing of control module output, and the status signals of reading control module output.
Described interface module can comprise compose buffer and read buffer zone that wherein compose buffer connects main equipment output/slave unit input data line, the described buffer zone connection main equipment input/slave unit output data line of reading.
Owing to when implementing half duplex series communication, when two data passages of MOSI and MISO and main equipment carry out data interaction, be not to carry out synchronously.Therefore if also adopt the structure of serial communiction bus external equipment interface of the prior art, being actually has wasted a data passage, the difficulty of having given the unnecessary increase of plate level design.Therefore the present invention adopts SPI data line Multiplexing module with on this two data channel multiplexings to bi-directional data signal wire exactly, thereby reduces the signal that communicates with main equipment, reaches the purpose of the complicacy that reduces the design of plate level.In addition, SPI data line Multiplexing module of the present invention is according to the slave unit useful signal, forces synchronizing signal, and upper-layer protocol is realized the read-write state signal that module produces, produce the channel selecting control signal, its logical relation is simple, precise control can effectively realize SPI data multiplex function.Relative prior art, the present invention is guaranteeing to have characteristics such as simple and reasonable, that signal wire is few, the design of plate level is simpler under the unimpeded prerequisite of master and slave equipment half-duplex data communication precise control, data channel.
Description of drawings
Accompanying drawing 2 is the frame head structural drawing of the upper-layer protocol frame among Fig. 1;
Accompanying drawing 3 is the structural drawing of the subframe head of the upper-layer protocol frame among Fig. 1;
Accompanying drawing 4 is a kind of structural principle block scheme that adopts the serial communiction bus external equipment interface of Fig. 1,2,3 upper-layer protocol in the prior art;
Accompanying drawing 5 is the structural principle block scheme of a kind of half duplex series communication bus external device interface of the present invention;
Accompanying drawing 6 is the circuit block diagram of a kind of preferred embodiment of the present invention.
Embodiment
In order more to have known explanation technical scheme of the present invention, be necessary at first to describe in detail the structural principle of upper-layer protocol of the present invention.
Described upper-layer protocol is a kind of master-slave mode full duplex or half-duplex operation agreement, and all transmission are initiated by main frame, and main frame can transmit and receive data simultaneously.Support SPI to interrupt transmission, do not require that in the transmission course of entire frame SSN keeps low level always.The frame head variable-length adopts short frame head when the transmission low volume data, improve transfer efficiency.
The upper-layer protocol frame is made of frame head and payload two parts, as shown in Figure 1.Because the variable business of its carrying data volume in order to improve transfer efficiency, adopts adjustable length frame structure.In this upper-layer protocol, frame head and payload are variable-length, and are defined by frame header.
The frame head structure is made of one or more subframe heads as shown in Figure 2.Frame head always sends to slave unit from main equipment.
The subframe header structure as shown in Figure 3.Wherein:
AD is the slave unit port address.
PHF is that the payload length most-significant byte is an effective marker.When this position was 1, expression payload length most-significant byte was effective, equals PH, and subframe head length degree is 3 bytes; When this position was 0, expression payload length most-significant byte was 0, and subframe head length degree is 2 bytes.
RW is used to define the attribute of book frame head.In this upper-layer protocol, two seed frame heads are arranged, write the subframe head and read the subframe head.Write the subframe head and be used to define the transformat that sends data to slave unit from main equipment, read the subframe head and be used to define the transformat that sends data to main equipment from slave unit.When this position is 1, represent that this subframe head is for writing the subframe head; When this position was 0, this subframe head was for reading the subframe head.
PL is used to represent low 4 of payload length.
LSHF is last subframe zone bit.When this position was 1, expression book frame head was last subframe head; When this position was 0, expression book frame head was not last subframe head.
PH is used to represent the most-significant byte of payload length.These 8 is optionally, and is determined by PHF.
Res. be to keep the position.
Payload is exactly the data that are transmitted, and its length is to change.Payload length is by the subframe head definition of correspondence, and the payload length of writing the definition of subframe head is exactly the byte number that sends to the data of slave unit from main equipment, and the payload length of reading the definition of subframe head is exactly the byte number that sends to the data of main equipment from slave unit.The variation range of payload length is from 1 to 4093 byte, and when payload length is not more than 15 bytes, the PHF position of subframe head is 0, and payload length equals PL, and when payload length during greater than 15 bytes, payload length equals PH * 16+PL.
This upper-layer protocol adopts slave unit motor synchronizing and main equipment to force synchronous combined synchronization scheme.
The slave unit motor synchronizing is exactly automatically synchronous each frame of slave unit, and its method is after slave unit receives last byte of previous frame, changes the beginning of next frame automatically over to.This synchronization scenario advantage is exactly that synchronizing circuit is simple, need not main equipment and participates in; Shortcoming is a poor reliability, can not recover automatically after the step-out.
It is exactly that main equipment sends synchronizing signal synchronously that main equipment forces, and its method is that main equipment forces synchronizing signal (FEN) to the slave unit transmission.It is the reliability height that the advantage of this synchronization scenario is lost; Shortcoming is to need main equipment to participate in, and increases the main equipment burden.
In order to bring into play the advantage of these two kinds of synchronization scenarios, overcome its shortcoming, we adopt the combined synchronization scheme.The combined synchronization scheme is exactly that main frame sends one every some frames and forces synchronizing signal FEN, forces slave unit synchronous.Do not send when forcing synchronizing signal at main frame, slave unit is synchronous automatically.
Adopting the serial communiction bus external equipment interface of upper-layer protocol as shown in Figure 1, 2, 3, is exactly to adopt the SPI agreement as underlying protocol, organically combines described upper-layer protocol, thereby obtains a kind of serial communiction bus external equipment interface of optimum structure.Its structure as shown in Figure 4, it realizes that by physical layer protocol module, upper-layer protocol realize that module and interface module constitute.Wherein: described physical layer protocol realizes that module is used to receive serial clock signal (SCK), and according to the SPI pattern, clocking outputs to upper-layer protocol and realizes module and interface module; Described interface module connects slave unit and effectively selects signal wire (SSN), main equipment input/slave unit output data line (MISO), main equipment output/slave unit input data line (MOSI) and reading data signal line (RDATA) and write data signal line (WDATA), thereby forms the read/write data path of described serial communiction bus external equipment interface; Described upper-layer protocol realizes that module receives described upper-layer protocol frame, to carry out master-slave mode full duplex or half-duplex data communication; That receive autonomous device simultaneously forces synchronizing signal (FEN), to realize the combined synchronization of master-slave equipment; And output read/write address signal (RADDR/WADDR), read/write enable signal (RDN/WRN).
Below in conjunction with Fig. 5,6 and specific embodiment the present invention is described in further detail.
With reference to the accompanying drawings 5, the invention provides a kind of half duplex series communication bus external device interface, comprise that physical layer protocol realizes that module, upper-layer protocol realize module and interface module.Wherein:
Described physical layer protocol realizes that module is used to receive serial clock signal, and according to the SPI pattern, clocking outputs to upper-layer protocol and realizes module and interface module;
Described upper-layer protocol realizes that module receives the upper-layer protocol frame, to carry out the half-duplex data communication; Receive the synchronizing signal of forcing of autonomous device, to realize the combined synchronization of master-slave equipment; Also produce read/write address signal (RADDR/WADDR), read/write enable signal (RDN/WRN) simultaneously according to the upper-layer protocol frame;
Described interface module connects two data lines in the spi bus, be main equipment input/slave unit output data line (MISO) and main equipment output/slave unit input data line (MOSI), and connect reading data signal line (RDATA) and write data signal line (WDATA), thereby form the read/write data path of this interface.
Multiplexing in order to realize the SPI data line, reach and reduce plate level design complexity, make more reasonably purpose of interface circuit interface, the present invention also comprises SPI data line Multiplexing module.Described SPI data line Multiplexing module passes through two data line connection interface module in the spi bus, and is connected with main equipment by bi-directional data signal wire (SIO), thereby finishes the data interaction between described interface module and the main equipment.
Fig. 6 provides the circuit block diagram of a kind of preferred embodiment of the present invention.
Among this embodiment, described SPI data line Multiplexing module is made of output control module and channel selecting element, described channel selecting element connected in series inserts between bi-directional data signal wire and the SPI data line, described output control module is used to produce the channel selecting control signal, and be input in the channel selecting element, thereby control the conducting state of described SPI data line and bi-directional data signal wire.
Described channel selecting element can adopt three-state buffer shown in Figure 6, also can adopt that other has the components and parts of channel selecting function as channel selector switch etc.Described channel selecting element can adopt the control shown in Figure 6 MISO data line wherein and the method for SIO signal wire connected relation, also can adopt the control method that is communicated with the SIO signal wire of MISO and two data line alternatives of MOSI, also can adopt the method for control MOSI and SIO signal wire connected relation.
Among Fig. 6, the input end of described three-state buffer connects the MISO data line, and its output terminal connects the bi-directional data signal wire, and its control end input channel is selected control signal.Described bi-directional data signal wire SIO is connected with the main equipment output/slave unit input data line MOSI conducting of output control module.
Described output control module is according to the slave unit useful signal, forces synchronizing signal, and upper-layer protocol is realized the read-write state signal that module produces, generation channel selecting control signal.When the slave unit useful signal or when forcing synchronizing signal to be high level, when perhaps the read-write state signal is write operation, perhaps the read-write state signal is read operation and when being in the frame head of this read operation, described output control module produces channel selecting control signal MISO_EN, make three-state buffer output high resistant, thereby select bi-directional data signal wire SIO and main equipment output/slave unit input data line MOSI conducting.
This logic discrimination relation of described output control module can adopt some simple logical circuits to realize, as Sheffer stroke gate array, decoding scheme or the like.These logic distinguishing circuits are technology common in this area, and those skilled in the art need not can realize through performing creative labour, for simplicity's sake, no longer are described in detail in this instructions.
In this preferred embodiment, described physical layer protocol realizes that module is a clock generation module.Described clock generating module functions is according to the serial clock SCK of SPI and SPI mode select signal MSEL clocking spi_clk and inversion signal spi_clkn thereof.When the SPI pattern is 0 and 3, clock signal spi_clk and SPI serial clock SCK homophase, when the SPI pattern was 1 and 2, clock signal spi_clk and SPI serial clock SCK were anti-phase.Spi_clkn is anti-phase with clock signal spi_clk all the time.In this programme, the clock of all registers all is spi_clk or its inversion signal spi_clkn.
Described interface module is by reading buffer zone and compose buffer constitutes.Wherein, compose buffer connects main equipment output/slave unit input data line MOSI, and the described buffer zone of reading connects main equipment input/slave unit output data line MISO.The compose buffer module functions is to receive data by bit from spi bus, with 8 data lines and line output.In order to reduce delay, adopt the double buffering structure.The described major function of reading buffer zone module is to read in a byte from 8 the parallel transmission number of it is believed that RDATA, and serial outputs on the spi bus then.In order to support continuous read operation, adopt prefetching technique, promptly in advance data are read.
Described upper-layer protocol realizes that module is by bit counter, byte counter, the address latch module, write control module, reading control module constitutes, the described synchronizing signal FEN that forces is input to respectively in bit counter and the byte counter, described upper-layer protocol frame is input to the address latch module respectively by main equipment output/slave unit input data line MOSI, write control module and read control module, described address latch module output read/write address signal RADDR and WADDR, describedly write control module output and write enable signal WRN, describedly read control module output and read enable signal RDATA.
The major function of bit counter is that the data of transmitting on the current spi bus of record are which bits of a certain byte.This counter is mould 8 counters.When SSN or FEN are high level, this counter reset.
Write down current transmission data during the major function of byte counter and belong to which byte in the upper-layer protocol frame.This counter is to be the counter of mould with the frame length.When FEN is high level, this counter reset.
Address latch module major function is to latch to read address or write address in the upper-layer protocol frame.
The major function of write control signal generation module is to produce write control signal WRN and write status signal.
The major function of read control signal generation module is to produce read control signal RDN and status signals.
Described upper-layer protocol realizes that the read-write state signal of module output then comprises the bit number byte_count of bit counter output, the byte number bit_count of byte counter output, write the status signal of writing of control module output, and the status signals of reading control module output.
In the present embodiment, physical layer protocol realizes that the physical circuit of module, upper-layer protocol realization module and interface module all can adopt interlock circuit of the prior art to realize, so need not in this instructions to describe in detail again.
By as can be known aforementioned, the present invention can adopt numerous embodiments to realize, therefore the present invention includes but is not limited to present embodiment.In the specific implementation process, all changes of doing according to technical solution of the present invention when the function that is produced does not exceed the scope of technical solution of the present invention, all belong to protection scope of the present invention.
Claims (8)
1, a kind of half duplex series communication bus external device interface comprises that physical layer protocol realizes module, upper-layer protocol realization module and interface module;
Described physical layer protocol realizes that module is used to receive serial clock signal, and according to the SPI pattern, clocking outputs to upper-layer protocol and realizes module and interface module;
Described upper-layer protocol realizes that module receives the upper-layer protocol frame, to carry out the half-duplex data communication; Receive the synchronizing signal of forcing of autonomous device, to realize the combined synchronization of master-slave equipment; Also produce read/write address signal, read/write enable signal simultaneously according to the upper-layer protocol frame;
Described interface module connects two data lines in the spi bus, be main equipment input/slave unit output data line and main equipment output/slave unit input data line, and connect reading data signal line and write data signal line, thereby form the read/write data path of this interface;
It is characterized in that: also comprise SPI data line Multiplexing module, described SPI data line Multiplexing module is by two data line connection interface module in the spi bus, and be connected with main equipment by the bi-directional data signal wire, thereby finish data interaction between described interface module and the main equipment.
2, half duplex series communication bus external device interface according to claim 1, it is characterized in that: described SPI data line Multiplexing module is made of output control module and channel selecting element, described channel selecting element connected in series inserts between bi-directional data signal wire and the SPI data line, described output control module is used to produce the channel selecting control signal, and be input in the channel selecting element, thereby control the conducting state of described SPI data line and bi-directional data signal wire.
3, as half duplex series communication bus external device interface as described in the claim 2, it is characterized in that: described output control module is according to the slave unit useful signal, forces synchronizing signal, and upper-layer protocol is realized the read-write state signal that module produces, generation channel selecting control signal.
4, as half duplex series communication bus external device interface as described in the claim 3, it is characterized in that: when the slave unit useful signal or when forcing synchronizing signal to be high level, when perhaps the read-write state signal is write operation, perhaps the read-write state signal is read operation and when being in the frame head of this read operation, described output control module produces the channel selecting control signal, selects bi-directional data signal wire and the conducting of main equipment output/slave unit input data line.
5, as half duplex series communication bus external device interface as described in the claim 2,3 or 4, it is characterized in that: described channel selecting element adopts three-state buffer, the input end of described three-state buffer connects the SPI data line, its output terminal connects the bi-directional data signal wire, and its control end input channel is selected control signal.
6, as half duplex series communication bus external device interface as described in the claim 5, it is characterized in that: described bi-directional data signal wire is connected with the main equipment output/slave unit input data-interface conducting of output control module.
7, as half duplex series communication bus external device interface as described in the claim 6, it is characterized in that: described upper-layer protocol realizes that module comprises bit counter, byte counter, address latch module, writes control module and read control module, described upper-layer protocol realizes that the read-write state signal of module output comprises the bit number of bit counter output, the byte number of byte counter output, write the status signal of writing of control module output, and the status signals of reading control module output.
8, as half duplex series communication bus external device interface as described in the claim 7, it is characterized in that: described interface module comprises compose buffer and reads buffer zone, wherein compose buffer connects main equipment output/slave unit input data line, and the described buffer zone of reading connects main equipment input/slave unit output data line.
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| CN100468378C (en) * | 2005-12-17 | 2009-03-11 | 鸿富锦精密工业（深圳）有限公司 | SPI apparatus telecommunication circuit |
| CN100492334C (en) * | 2005-12-14 | 2009-05-27 | 联发科技股份有限公司 | String peripheral interface device |
| CN102033828A (en) * | 2010-11-24 | 2011-04-27 | 中兴通讯股份有限公司 | Method and system for accessing external card |
| CN101399654B (en) * | 2007-09-25 | 2011-08-03 | 华为技术有限公司 | Serial communication method and apparatus |
| CN103838701A (en) * | 2012-11-22 | 2014-06-04 | Ls产电株式会社 | Data processing apparatus and method in PLC system |
| CN113485957A (en) * | 2021-06-25 | 2021-10-08 | 厦门码灵半导体技术有限公司 | Multi-protocol system control device and multi-protocol system control method for physical layer suitable for industrial application scene |
| CN118400224A (en) * | 2024-06-28 | 2024-07-26 | 宁波永新光学股份有限公司 | Half-duplex RS485 bus communication method for electric microscope |
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| CN100492334C (en) * | 2005-12-14 | 2009-05-27 | 联发科技股份有限公司 | String peripheral interface device |
| CN100468378C (en) * | 2005-12-17 | 2009-03-11 | 鸿富锦精密工业（深圳）有限公司 | SPI apparatus telecommunication circuit |
| CN101399654B (en) * | 2007-09-25 | 2011-08-03 | 华为技术有限公司 | Serial communication method and apparatus |
| CN102033828A (en) * | 2010-11-24 | 2011-04-27 | 中兴通讯股份有限公司 | Method and system for accessing external card |
| CN102033828B (en) * | 2010-11-24 | 2015-06-03 | 中兴通讯股份有限公司 | Method and system for accessing external card |
| CN103838701A (en) * | 2012-11-22 | 2014-06-04 | Ls产电株式会社 | Data processing apparatus and method in PLC system |
| CN113485957A (en) * | 2021-06-25 | 2021-10-08 | 厦门码灵半导体技术有限公司 | Multi-protocol system control device and multi-protocol system control method for physical layer suitable for industrial application scene |
| CN113485957B (en) * | 2021-06-25 | 2023-05-30 | 厦门码灵半导体技术有限公司 | Multi-protocol system control device and multi-protocol system control method for physical layer suitable for industrial-level application scene |
| CN118400224A (en) * | 2024-06-28 | 2024-07-26 | 宁波永新光学股份有限公司 | Half-duplex RS485 bus communication method for electric microscope |
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