CN2733587Y - Modification of wafer fixed installing structure - Google Patents

Modification of wafer fixed installing structure Download PDF

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Publication number
CN2733587Y
CN2733587Y CNU2004200124006U CN200420012400U CN2733587Y CN 2733587 Y CN2733587 Y CN 2733587Y CN U2004200124006 U CNU2004200124006 U CN U2004200124006U CN 200420012400 U CN200420012400 U CN 200420012400U CN 2733587 Y CN2733587 Y CN 2733587Y
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CN
China
Prior art keywords
wafer
lead frame
material layer
resin layer
conducting wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNU2004200124006U
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Chinese (zh)
Inventor
资重兴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Liang Xiwei
Original Assignee
Individual
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Filing date
Publication date
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Priority to CNU2004200124006U priority Critical patent/CN2733587Y/en
Application granted granted Critical
Publication of CN2733587Y publication Critical patent/CN2733587Y/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model discloses a modification of a wafer fixed installing structure, comprising a wafer, a conducting wire holder, a metal thread for connecting the wafer and the conducting wire holder and an external sealing colloid. The utility model is characterized in that the bottom of the wafer corresponding to each whole row of the leading legs of the conducting wire holder is provided with a sealing resin layer. The bottom surface of the sealing resin layer is coated with a sticky material layer. The sticky material layer and each whole row of the leading legs of the conducting wire holder stick together. By use of the sealing resin layer and the sticky material layer the wafer is fixed on each leading led of the conducting wire holder. The utility model adopts the sealing resin layer and the sticky material layer to make the wafer fixed on the conducting wire holder. Compared with the existing wafer fixed structure which adopts adhesive tapes used for sticking wafers to fix the wafer, the sealing cost is reduced and the wafer can be protected stably. The wafer can be prevented from flawing caused by fracturing.

Description

The improvement of wafer securing structure
Technical field
The utility model relates to a kind of wafer securing structure improvement, and particularly a kind of wafer and lead frame be cemented structural improvement mutually.
Background technology
Tend under the smart littleization research and development purpose at electric crystal now, cause recent electric crystal encapsulating structure and early stage electric crystal encapsulating structure that evident difference is arranged, as shown in Figure 6, be the composition structure of seminiferous electric crystal, it mainly is pin 201 positions at a wafer 10 bottom surface corresponding lead framves 20, the wafer that has been sticked is cemented with adhesive tape 30, make this wafer 10 directly be packed on the lead frame 20 by this, and after 201 of this wafer 10 and pins are connected metal wire 40, selected metal wire 40 positions implement a local adhesive body 50, form the electric crystal that the subset of can powering etc. uses by this.
But; above-mentioned seminiferous electric crystal is formed structure; because wafer is cemented to be high products with adhesive tape 30; it is applied on the cemented structure of wafer 10 and lead frame 20; not only can't reduce the electric crystal packaging cost; and, make wafer 10 no suitable protection structural measures own because of this wafer 10 is directly cemented with each pin 201 that is not connected, the wafer 10 cracked flaws that wait will easily take place.
The utility model content
The purpose of this utility model is to solve packaging cost height and the easily cracked problem of wafer that above-mentioned electric crystal encapsulating structure exists, and a kind of wafer securing structure improvement that overcomes above-mentioned shortcoming is provided.
The utility model includes metal wire and the outside adhesive body that wafer, lead frame, wafer are connected with lead frame, it is characterized in that, the position of each whole row's pin of wafer bottom surface corresponding lead frame is coated with a potting resin layer, be furnished with an adhesion material layer in potting resin layer coated on bottom side, make each whole row's pin formation of this adhesion material layer and lead frame cemented, mat potting resin layer and adhesion material layer are packed on each pin of lead frame wafer.
Two sides or four side places are provided with potting resin layer, adhesion material layer and lead frame respectively to described wafer in the bottom surface respectively arranges pin.
The pin of described lead frame is equipped with a projection in the bottom surface, or is provided with the junction that downward bending is extended at outboard end.
The utility model uses potting resin layer, adhesion material layer that wafer is installed in lead frame; use cemented the installing of wafer to compare with known wafer securing structure with adhesive tape; packaging cost reduces, and wafer is had stable protection, makes wafer be difficult for the chipping flaw of Denging.
Description of drawings
Fig. 1 is the perspective exploded view of the utility model first embodiment.
Fig. 2 is the cross-sectional schematic of the utility model first embodiment.
Fig. 3 is the cross-sectional schematic of the utility model second embodiment.
Fig. 4 has the cross-sectional schematic of projection for lead frame pin of the present utility model.
Fig. 5 has the cross-sectional schematic of junction for lead frame pin of the present utility model.
Fig. 6 is the cross-sectional schematic of known chip package structure.
Embodiment
See also Fig. 1, Fig. 2, Fig. 3, Fig. 4, shown in Figure 5, the utility model includes the metal wire 5 that a wafer 1, potting resin layer 2, adhesion material layer 3, lead frame 4, wafer 1 be connected with lead frame 4 and the adhesive body 6 of protection metal wire 5 connecting portions, wherein, this wafer 1 and potting resin layer 2 applied material are conventional materials, do not repeat them here; This adhesion material layer 3 can be a kind of wet type coating and constitutes the sticky stuff that sticks together; This lead frame 4 is for a plurality of block pins 41 are the parallel or four row's rectangular shapes arrangement formations of two rows, with the external electric connection element as wafer 1.
The utility model mainly is to be coated with a potting resin layer 2 at the position of wafer 1 bottom surface corresponding lead frame 4 each whole row's pin 41, as shown in Figure 1, be furnished with an adhesion material layer 3 in potting resin layer 2 coated on bottom side, make this adhesion material layer 3 and each whole row's pin 41 of lead frame 4 constitute cemented, mat potting resin layer 2 and adhesion material layer 3 are cemented on each pin 41 of lead frame 4 wafer 1, promptly form wafer 1 and be installed in lead frame 4 structures, further implement metal wire 5 routings and adhesive body 6 encapsulation, and form the electric crystal that the subset of can powering is used.
Because wafer 1 of the present utility model is to adopt adhesion material layer with low cost 3 and lead frame 4 to form fixing assembling, can avoid adopting the high fixing chip tape of using, and therefore can reduce the manufacturing cost that it is packaged into electric crystal significantly; Secondly; because wafer 1 is to have potting resin layer 2 to provide with lead frame 4 and stick together in the bottom surface; therefore in reaching smart littleization structure purpose; can be with the pressure of the outer bound pair wafer 1 of potting resin layer 2 opposing; the pressure that is produced when for example lead frame 4 postorders cut, and have effect stable and protection wafer 1.
As mentioned above, the utility model is to be provided with potting resin layer 2, adhesion material layer 3 and lead frame 4 in regular turn in wafer 1 bottom surface, its preferred embodiment be included in two side places, wafer 1 bottom surface as shown in Figure 1 and Figure 2 or four side places be coated with potting resin layer 2 and adhesion material layer 3 respectively, and it is cemented on the pin 41 of lead frame 4 with adhesion material layer 3, by this, each arranges the metal wire 5 that pin 41 middle hollow-out parts implement connecting wafer 1 and each pin 41, and the adhesive body 6 of this metal wire 5 of sealing, can form the electric crystal that an encapsulation is finished; Again as shown in Figure 3, also can on reach around the wafer 1, implement an adhesive body 6 ' in addition to reach better seal protection effect.
Feature of the present utility model is the structure that wafer 1 is installed in lead frame 4, and the configuration of the pin 41 of lead frame 4 is not limited to specific configuration, can be rectangular block shape shown in Figure 1; Or as shown in Figure 4, rectangular block shape pin 41a is equipped with a projection 411a in the bottom surface, with this projection 411a as with the position that is electrically conducted of other electronic equipment; Or as shown in Figure 5, this rectangular block shape pin 41b is provided with the junction 412b that a bending is downwards extended in outboard end, with this junction 412b as with the position that is electrically conducted of other electronic equipment.

Claims (3)

1, a kind of wafer securing structure improvement, it includes metal wire and outside adhesive body that wafer, lead frame, wafer are connected with lead frame, it is characterized in that: the position of each whole row's pin of wafer bottom surface corresponding lead frame is coated with a potting resin layer, be furnished with an adhesion material layer in potting resin layer coated on bottom side, the whole row of each of this adhesion material layer and lead frame pin constitutes cemented.
2, a kind of wafer securing structure improvement according to claim 1 is characterized in that: two sides or four side places are provided with potting resin layer, adhesion material layer and lead frame respectively to described wafer in the bottom surface respectively arranges pin.
3, a kind of wafer securing structure improvement according to claim 1, it is characterized in that: the pin of described lead frame is equipped with a projection in the bottom surface, or is provided with the junction that downward bending is extended at outboard end.
CNU2004200124006U 2004-08-30 2004-08-30 Modification of wafer fixed installing structure Expired - Fee Related CN2733587Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNU2004200124006U CN2733587Y (en) 2004-08-30 2004-08-30 Modification of wafer fixed installing structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNU2004200124006U CN2733587Y (en) 2004-08-30 2004-08-30 Modification of wafer fixed installing structure

Publications (1)

Publication Number Publication Date
CN2733587Y true CN2733587Y (en) 2005-10-12

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Application Number Title Priority Date Filing Date
CNU2004200124006U Expired - Fee Related CN2733587Y (en) 2004-08-30 2004-08-30 Modification of wafer fixed installing structure

Country Status (1)

Country Link
CN (1) CN2733587Y (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112046824A (en) * 2018-12-29 2020-12-08 董建 Packaging jig of capacitor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112046824A (en) * 2018-12-29 2020-12-08 董建 Packaging jig of capacitor
CN112046824B (en) * 2018-12-29 2021-09-28 翟如相 Packaging jig of capacitor

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: LIANG XIWEI

Free format text: FORMER OWNER: ZI ZHONGXING

Effective date: 20071012

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20071012

Address after: 100044, room 3, building 6, car 311, main street, Xicheng District, Beijing

Patentee after: Liang Xiwei

Address before: 226500 Rugao city of Jiangsu province Hangyuan Pu 207 building 303 room

Patentee before: Zi Zhongxing

C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee