CN2622932Y - Integrated clipping amplifier - Google Patents
Integrated clipping amplifier Download PDFInfo
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- CN2622932Y CN2622932Y CN 03234919 CN03234919U CN2622932Y CN 2622932 Y CN2622932 Y CN 2622932Y CN 03234919 CN03234919 CN 03234919 CN 03234919 U CN03234919 U CN 03234919U CN 2622932 Y CN2622932 Y CN 2622932Y
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Abstract
The utility model discloses an integrated clipping amplifier, comprising more than one difference amplifiers, a feedback amplifier and a resistance capacitance feedback network which are orderly connected in series, wherein the difference amplifier comprises a complementary field effect transistor differential pair and a first pull-up field effect transistor and a second pull-up field effect transistor which are connected with the two output ends of the complementary field effect transistor differential pair, the two input ends of the feedback amplifier is connected to the last stage of the difference amplifier in multi-stage, the two output ends of the feedback amplifier are respectively connected to the input ends of common-mode voltages of the first pull-up field effect transistor and the second pull-up field effect transistor in each stage of the difference amplifier through the resistance capacitance feedback network. The common-mode voltage generated by a resistance capacitance filter forms a negative feedback, and the field effect transistor can be effectively prevented from entering into the non-saturation area because of temperature variation or process deviation, thereby guaranteeing that the circuit can always normally work. That is to say, the sensitivity of the circuit to the temperature and process deviation is reduced, and the yield is improved.
Description
Technical field:
The utility model relates to a kind of integrated limiting amplifier, the common-mode feedback of integrated limiting amplifier and imbalance technology for eliminating.
Background technology:
At present, Cheng Shu commercial integrated limiting amplifier constitutes by ambipolar (Bipolar) device.Be the advantage of performance CMOS technology, existing in recent years people [1,2,3] adopts the mode of continuous detecting (Successive Detection) successfully to design well behaved CMOS limiting amplifier.But, also have certain weak point.The design of Matt Peterson is integrated more resistance, simple in structure, but the resistance chip area is big, temperature characterisitic difference and fabrication error height, and the circuit overall performance is had bigger negative effect.People's such as K.Shorram design is the typical case comparatively, disclose name among they the 95th page (the 1995 Symposlum on VLSI Circuits Digest of Technical Papers.p.95) in " the very large scale integration technology paper digest " of nineteen ninety-five and be called " complementary field effect pipe limiting amplifier and signal strength signal intensity indication " (" A CMOS Limiting Amplifier and Signal-Strength Indicator ") middle pull-up resistor that adopts diode connecting-type N channel field-effect pipe (Diode-connected N field effect transistor) as N channel field-effect pipe differential pair, because the inclined to one side effect of lining, this will seriously reduce the dynamic range of limiting amplifier, limit its application in low-voltage circuit.People such as Po-ChuinHuang are for overcoming above-mentioned shortcoming, at IEEE solid state circuit magazine the 10th phase of October in 2000 volume 35 (IEEE Journal of Solid-State Circuits, Vol.35, No, 10, Oct.2000, " 10.7MHZ complementary field effect pipe limiting amplifier/indication input signal amplitude " (" A2-V10.7MHz CMOS LimitingAmplifier/RSSI ") disclosed p1474), it adopts the pull down resistor of diode connecting-type N channel field-effect pipe (Diode-connected N field effect transistor) as complementary field effect pipe differential pair, this has no doubt increased dynamic range, but change with operating state owing to the output common-mode point, be difficult to realize common-mode feedback, cause circuit to variations in temperature and fabrication error sensitivity, reduced circuit performance.
As shown in Figure 1, (for example: G=12dB) the differential amplifier cascade constitutes typical C MOS limiting amplifier by 7 low gains.8 full-wave rectifiers and RC network with the output of 7 differential amplifiers or input adds and, be rectified into direct voltage, be used to indicate input signal amplitude (RSSI).The course of work of circuit is: the every increase of input signal G is (for example 12dB) doubly, and with saturated one-level amplifier, therefore the voltage of input signal amplitude indication increase 1 times.The input signal of amplitude minimum makes the 7th grade of amplifier saturated, and maximum makes 7 amplifiers all saturated.In addition, circuit also increases a RC feedback network and subtracter is used for the imbalance elimination.
The low gain differential amplifier of function admirable usually adopts structure as shown in Figure 2.Be in the linear amplification state during amplifier operate as normal, be in non-linear magnifying state when saturated.In order to increase dynamic range, the input and output common-mode point is difficult to during with non-linear amplification consistent at linear amplification, and the method for easy-to-use routine realizes common-mode feedback.The difference MOS amplifier of no common-mode feedback is very responsive to temperature and fabrication error, and its finished product is cisco unity malfunction usually.
Summary of the invention:
The purpose of this utility model is exactly in order to overcome the above problems, and proposes a kind of integrated limiting amplifier, and it can reduce the susceptibility of circuit to variations in temperature and technology.
For achieving the above object, the utility model proposes a kind of integrated limiting amplifier, comprise an above differential amplifier of series connection successively, feedback amplifier and resistance capacitance feedback network, described differential amplifier comprise complementary field effect pipe differential pair with link to each other with the dual output end of complementary field effect pipe differential pair respectively first, draw field effect transistor on second, the double input end of feedback amplifier is connected to the dual output end of the afterbody differential amplifier in multistage, and the dual output end of feedback amplifier is connected to first in every grade of difference amplifier through the resistance capacitance feedback network respectively, draw the common-mode voltage input of field effect transistor on second.
Owing to adopted above scheme, the common-mode voltage that resistor ﹠ capacitor filter produces forms negative feedback, can effectively stop field effect transistor because variations in temperature or process deviation enter non-saturated region, thereby can guarantee that circuit can operate as normal.That is to say that circuit has reduced the sensitivity of temperature and fabrication error, has improved rate of finished products.
Description of drawings:
Fig. 1 is the circuit block diagram of the integrated limiting amplifier embodiment of prior art;
Fig. 2 is the circuit diagram of low gain differential amplifier in the integrated limiting amplifier of prior art;
Fig. 3 is the circuit block diagram of the integrated limiting amplifier embodiment of the utility model;
The circuit diagram of low gain differential amplifier in the integrated limiting amplifier of Fig. 4 the utility model.
Embodiment:
Also in conjunction with the accompanying drawings the utility model is described in further detail below by specific embodiment.
Embodiment one: as shown in Figure 3, a kind of integrated limiting amplifier, comprise an above differential amplifier f1 of series connection successively, f2, f3, f4, f5, f6, f7, feedback amplifier f8, resistance capacitance feedback network 2 and more than one full-wave rectifying circuit, described differential amplifier f1, f2, f3, f4, f5, f6, f7 comprise complementary field effect pipe differential pair and respectively with complementary field effect pipe differential pair T3, the output of T4 link to each other first, draw field effect transistor T1 on second, T2, the double input end of feedback amplifier f8 is connected to the dual output end of the afterbody differential amplifier f7 in multistage, and the dual output end of feedback amplifier f8 is connected to first in every grade of difference amplifier through resistance capacitance feedback network 2 respectively, draw field effect transistor T1 on second, the common-mode voltage input a of T2, b.The input of each full-wave rectifying circuit is connected to the input of each corresponding differential amplifier respectively, and the output of all full-wave rectifying circuits links together.Resistance capacitance feedback network 2, first resistance R 1, first capacitor C 1 and second resistance R 2 that comprise series connection successively, the other end of first resistance R 1 and second resistance R 2 is as the double input end of resistance capacitance feedback network 2, and the two ends of first capacitor C 1 are as first, second output of resistance capacitance feedback network 2.Wherein differential amplifier comprises first, second N channel field-effect pipe T1, T2, the first, second, third, fourth and the 5th P-channel field-effect transistor (PEFT) pipe T3, T4, T5, T6, T7, the first and second N channel field-effect pipe T1, T2 common drain, their source electrode is respectively as first, second output and be connected to the drain electrode of first, second P-channel field-effect transistor (PEFT) pipe T3, T4, and the grid level of first, second P-channel field-effect transistor (PEFT) pipe T3, T4 is as the common-mode voltage input; The grid of first, second P-channel field-effect transistor (PEFT) pipe T3, T4 is first, second power input, their common sources, and through the 5th P-channel field-effect transistor (PEFT) pipe T7 ground connection.Be connected to the 4th and the 5th channel field-effect pipe T5, T6 between first, second output and the ground, their grid and drain electrode are connected together, as voltage-stabiliser tube.As shown in Figure 3.Wherein preceding 7 differential amplifiers are identical, are low gain amplifier.Signal carries out other processing from the circuit that the 7th grade of amplifier outputs to the back.And, generally requiring the gain of feedback amplifier higher in order to guarantee good feedback effects, its structure can be different or not similar with preceding 7 grades of amplifiers.The scheme that I provide has adopted similar structure, that is to say, the dimension scale of feedback amplifier and preceding 7 grades are different, and it is different promptly to gain.Feedback amplifier produces common-mode voltage in conjunction with RC network and feeds back to the 7 grades of difference amplifiers in front.
The primary circuit structure is fabrication error and temperature sensitive reason, when variations in temperature or process deviation, the characteristic of field effect transistor or bias voltage will change at random, field effect transistor is easy to break away from saturation region (saturate region) and enters non-saturated region (triode region), thereby make differential amplifier can't amplify circuit malfunction! The key of embodiment one described scheme is, feedback amplifier can form negative feedback in conjunction with the common-mode voltage that the resistance capacitance feedback network produces, can prevent effectively that field effect transistor from entering non-saturated region owing to variations in temperature or process deviation, thereby can guarantee circuit total energy operate as normal.That is to say that circuit has reduced the sensitivity of temperature and fabrication error.Simultaneously, though this scheme does not have special offset cancellation circuit, has the function that imbalance is eliminated.The resistance capacitance feedback network has produced two common-mode feedback voltages at the electric capacity two ends, correctly these two voltages are connected on every grade of corresponding field effect transistor of amplifier, can suppress the offset voltage of circuit effectively.
The effect of present design below the situation that does not increase circuit complexity has reached:
When 1〉having kept circuit, reduced the sensitivity of circuit significantly, improved rate of finished products temperature and technology than great dynamic range.Temperature is from 0 ℃ to 85 ℃, and in whole working range, the RSSI output error less than 0.5dB, exceeds 1 times than the 1dB as a result of the bibliographical information of K.Shorram during with respect to room temperature.
2〉linearity of circuit improves a lot under the specified temp.In whole service area, the linearity of circuit fluctuates less than 0.1dB.The bibliographical information of K.Shorram is 0.3dB.
3〉circuit does not have special offset cancellation circuit, but has imbalance and eliminates function.
Claims (5)
1, a kind of integrated limiting amplifier, comprise an above differential amplifier (f1 of series connection successively, f2, f3, f4, f5, f6, f7) and resistance capacitance feedback network (2), described differential amplifier (f1, f2, f3, f4, f5, f6, f7) comprise complementary field effect pipe differential pair and respectively with complementary field effect pipe differential pair (T3, T4) dual output end link to each other first, draw field effect transistor (T1 on second, T2), it is characterized in that: also comprise feedback amplifier (f8), the double input end of feedback amplifier (f8) is connected to the dual output end of the afterbody differential amplifier (f7) in multistage, and the dual output end of feedback amplifier (f8) is connected to first in every grade of difference amplifier through resistance capacitance feedback network (2) respectively, draw field effect transistor (T1 on second, T2) common-mode voltage input (a, b).
2, integrated limiting amplifier as claimed in claim 1, it is characterized in that: described resistance capacitance feedback network (2), first resistance (R1), first electric capacity (C1) and second resistance (R2) that comprise series connection successively, the other end of first resistance (R1) and second resistance (R2) is as the double input end of resistance capacitance feedback network (2), and the two ends of first electric capacity (C1) are as first, second output of resistance capacitance feedback network (2).
3, integrated limiting amplifier as claimed in claim 1 or 2, it is characterized in that: also comprise more than one full-wave rectifying circuit, the input of each full-wave rectifying circuit is connected to the input of corresponding differential amplifier respectively, and the output of all full-wave rectifying circuits links together.
4, integrated limiting amplifier as claimed in claim 3, it is characterized in that: described differential amplifier comprises first, second N channel field-effect pipe (T1, T2), first, second and the 3rd P-channel field-effect transistor (PEFT) pipe (T3, T4, T7), first and second N channel field-effect pipe (T1, the T2) common drains, their source electrode is respectively as first, second output and be connected to the drain electrode of first, second P-channel field-effect transistor (PEFT) pipe (T3, T4), and the grid level of first, second P-channel field-effect transistor (PEFT) pipe (T3, T4) is as the common-mode voltage input; The grid of first, second P-channel field-effect transistor (PEFT) pipe (T3, T4) is first, second power input, their common sources, and through the 5th P-channel field-effect transistor (PEFT) pipe (T7) ground connection.
5, integrated limiting amplifier as claimed in claim 4, it is characterized in that: also comprise the 4th and the 5th P-channel field-effect transistor (PEFT) pipe (T5, T6), be connected to the 4th and the 5th channel field-effect pipe (T5, T6) between first, second output and the ground, their grid and drain electrode are connected together, as voltage-stabiliser tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03234919 CN2622932Y (en) | 2003-06-11 | 2003-06-11 | Integrated clipping amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03234919 CN2622932Y (en) | 2003-06-11 | 2003-06-11 | Integrated clipping amplifier |
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| CN2622932Y true CN2622932Y (en) | 2004-06-30 |
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| CN 03234919 Expired - Fee Related CN2622932Y (en) | 2003-06-11 | 2003-06-11 | Integrated clipping amplifier |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101729032A (en) * | 2008-10-22 | 2010-06-09 | 杭州士兰微电子股份有限公司 | Gain limiter circuit |
| CN102571227A (en) * | 2011-11-10 | 2012-07-11 | 嘉兴联星微电子有限公司 | Amplitude detection circuit with direct current offset elimination function |
| CN103812579A (en) * | 2012-11-08 | 2014-05-21 | 旭扬半导体股份有限公司 | Receiving signal strength indicator circuit having low voltage and wide detection energy range |
| CN104242843A (en) * | 2014-09-09 | 2014-12-24 | 长沙景嘉微电子股份有限公司 | Amplifier output amplitude limiting circuit |
| CN111800152A (en) * | 2020-07-13 | 2020-10-20 | 重庆百瑞互联电子技术有限公司 | Circuit for extracting received signal strength in receiver |
-
2003
- 2003-06-11 CN CN 03234919 patent/CN2622932Y/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101729032A (en) * | 2008-10-22 | 2010-06-09 | 杭州士兰微电子股份有限公司 | Gain limiter circuit |
| CN101729032B (en) * | 2008-10-22 | 2014-06-18 | 杭州士兰微电子股份有限公司 | Gain limiter circuit |
| CN102571227A (en) * | 2011-11-10 | 2012-07-11 | 嘉兴联星微电子有限公司 | Amplitude detection circuit with direct current offset elimination function |
| CN102571227B (en) * | 2011-11-10 | 2014-04-16 | 嘉兴联星微电子有限公司 | Amplitude detection circuit with direct current offset elimination function |
| CN103812579A (en) * | 2012-11-08 | 2014-05-21 | 旭扬半导体股份有限公司 | Receiving signal strength indicator circuit having low voltage and wide detection energy range |
| CN104242843A (en) * | 2014-09-09 | 2014-12-24 | 长沙景嘉微电子股份有限公司 | Amplifier output amplitude limiting circuit |
| CN111800152A (en) * | 2020-07-13 | 2020-10-20 | 重庆百瑞互联电子技术有限公司 | Circuit for extracting received signal strength in receiver |
| CN111800152B (en) * | 2020-07-13 | 2022-01-04 | 重庆百瑞互联电子技术有限公司 | Circuit for extracting received signal strength in receiver |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: XINKE INTERNATIONAL PRIVATE CO., LTD. Free format text: FORMER OWNER: SHENZHEN YUANHE MICROELECTRONICS TECHNOLOGY CO., LTD. Effective date: 20080725 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20080725 Address after: Singapore 098632 auspicious treasure Bay edifice 16-01 harbor front street 1, zip code: Patentee after: Xinke Int Private Co., Ltd. Address before: Room 410, South District, Longgang incubator center, overseas student Pioneer Park, Guangdong, Shenzhen 518172, China Patentee before: Shenzhen Yuanhe Microelectronics Technology Co., Ltd. |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040630 Termination date: 20110611 |