CN101729032B

CN101729032B - Gain limiter circuit

Info

Publication number: CN101729032B
Application number: CN200810121912.9A
Authority: CN
Inventors: 郑泉智
Original assignee: Hangzhou Silan Microelectronics Co Ltd
Current assignee: Hangzhou Silan Microelectronics Co Ltd
Priority date: 2008-10-22
Filing date: 2008-10-22
Publication date: 2014-06-18
Anticipated expiration: 2028-10-22
Also published as: CN101729032A

Abstract

The invention provides a gain limiter circuit which is formed by sequentially connecting N gain levels with differential input and differential output in series, wherein the differential input of the first gain level is used as the signal input end of the gain limiter circuit; the differential output of the last gain level is used as the signal output end of the gain limiter circuit; the gain level for receiving feedback is also provided with the second differential input; the differential output of the Kth gain level feeds signals back to the second differential input of the Mth gain level for receiving feedback through a feedback loop, wherein K is a random integer between 1 and N, and M is less than or equal to K; and each gain level is only contained in one feedback loop. The gain limiter circuit can reduce chip pins and peripheral components of an integrated circuit and is suitable for low-voltage working.

Description

Gain limiter circuit

Technical field

The present invention relates to radio frequency receiver signal processing technology, especially relate to the gain limiter circuit that amplifies intermediate-freuqncy signal, suppresses direct current and low frequency signal.

Background technology

Tradition gain limiter circuit structure, as shown in Figure 1, the gain stage that has difference input and difference output by several is connected in series successively and forms amplification, wherein first order gain stage has two difference inputs, first difference input of first order gain stage is as the signal input part of gain limiter circuit, the differential output signal of afterbody gain stage is given second difference input of the first gain stage by resistance feedback, between the second difference input of the first gain stage, connect shunt capacitance simultaneously, form offset compensation.First order gain stage circuit figure as shown in Figure 2 and the gain stage circuit except the first order as shown in Figure 3, the circuit of each gain stage is made up of NMOS.

Adopt traditional gain limiter circuit, the signal input X (S) that supposes gain limiter circuit is that 72dB, high pass-three dB bandwidth are that 160KHz, resistance value are 1M ohm to the gain of signal output Y (S), so needed electric capacity is 4nF, required electric capacity is excessive, can not be integrated in chip, need to increase pin and the peripheral cell of integrated circuit.

In order to realize high-gain, the gate source voltage of load M3, the M4 of each gain stage is often very large, is generally 2V simultaneously _tHeven higher, wherein V _tHfor threshold voltage, the supply voltage VDD of gain stage is greater than 2V as shown in Figure 9 _tH+ 2V _dS(approximately 3 V above _tHabove) circuit could normally be worked, wherein V _dSfor drain-source voltage.

Summary of the invention

The present invention is intended to solve the deficiencies in the prior art, and chip pin and the peripheral cell that can reduce integrated circuit are provided, and is applicable to the gain limiter circuit of operating on low voltage.

A kind of gain limiter circuit is connected in series successively by N the gain stage with difference input and difference output, the difference input of the first gain stage is as the signal input part of gain limiter circuit, the difference output of afterbody gain stage is as the signal output part of gain limiter circuit, also there is the second difference input for receiving the gain stage of feedback, the difference output of K stage gain level feeds back to the second differential input signal of the M stage gain level that receives feedback by feedback control loop, K is the arbitrary integer between 1 to N, M is less than or equal to K, and each gain stage is only comprised in a feedback control loop, electric capacity in each feedback control loop is integrated in gain limiter circuit inside.

Wherein, described feedback control loop can be RC low pass filter.

Wherein, described feedback control loop can also be Gm-C low pass filter.

Wherein, described feedback control loop can also be Active RC integrator.

Wherein, described feedback control loop can also be active switch capacitance integrator.

Wherein, described gain stage comprises nmos pass transistor M1, M2, resistance R 1, R2, power vd D and the first current source, wherein nmos pass transistor M1, M2 and resistance R 1, R2 form differential input and output pair, resistance R 1 and resistance R 2 are connected to power vd D jointly, and the source electrode of M1 and M2 is connected the first current source ground connection.

Wherein, described gain stage accept feedback also comprise the grid of nmos pass transistor M3, M4, M3 and the grid of M4 right as the second difference input, it is right that the drain electrode of M3 and M4 is connected to difference output, the source electrode of M3 and M4 is connected the second current source ground connection.

Taking the gain limiter circuit of RC loop with two gain stages as example, the signal input X (S) that supposes gain limiter circuit is 72dB to the gain of signal output Y (S), high pass-three dB bandwidth is 160KHz, and resistance value is that 1M ohm and the gain of each gain stage are respectively 36dB.The needed electric capacity of so every one-level is only 32pF, and electric capacity can be integrated in gain limiter circuit inside.

Visible by above analysis, the invention has the beneficial effects as follows the inner employing of gain limiter circuit multiple gain feedback loops realization imbalance elimination and suppress low frequency signal, reduce the capacitance in feedback circuit, electric capacity can be integrated in to gain limiter circuit inside, reduce chip pin and peripheral cell number.

Simultaneously in the gain stage of gain limiter circuit of the present invention, replace NMOS pipe in traditional gain stage as load with resistance R1, R2, reduce the pressure drop of power vd D to output, make gain limiter circuit be more suitable for the occasion in operating on low voltage, as go for intermediate-frequency receiver.

Brief description of the drawings:

Fig. 1 tradition gain limiter circuit structure chart

The first order gain stage circuit figure of Fig. 2 tradition gain limiter circuit

Gain stage circuit figure beyond the first order gain stage of Fig. 3 tradition gain limiter circuit

The gain limiter circuit structure chart of Fig. 4 RC low-pass-filter feedback loop of the present invention

Fig. 5 the present invention has the gain limiter circuit structure chart of Gm-C low-pass-filter feedback loop

Fig. 6 the present invention has gain stage circuit figure in the gain limiter circuit of Active RC integrator feedback control loop

Gain stage circuit figure in Fig. 7 gain limiter circuit of the present invention

In Fig. 8 gain limiter circuit of the present invention, accept the gain stage circuit figure of feedback

The minimum vdd voltage key diagram of Fig. 9 tradition gain limiter circuit

Embodiment

Below in conjunction with accompanying drawing, content of the present invention is further illustrated.

Gain limiter circuit shown in Fig. 4 is connected in series successively by 4 gain stages with difference input and difference output, the difference input VIP1 of the first gain stage, VIM1 is as the signal input part X (S) of gain limiter circuit, afterbody gain stage, the 4th grade, difference output VOP, VOM is as the signal output part Y (S) of gain limiter circuit, for receiving the gain stage of feedback, i.e. the first gain stage, the second gain stage also has the second difference input VIP2, VIM2, the difference output VOP of the 1st stage gain level, VOM feeds back to the second differential input signal VIP2 of the 1st stage gain level that receives feedback by feedback control loop, VIM2, the difference output VOP of the 4th stage gain level, VOM feeds back to the second differential input signal VIP2 of the 2nd stage gain level that receives feedback by feedback control loop, VIM2.

Wherein, described feedback control loop can be RC low pass filter, as shown in Figure 4.

Wherein, described feedback control loop can also be Gm-C low pass filter, as shown in Figure 5.

Wherein, described feedback control loop can also be Active RC integrator, as shown in Figure 6.

Wherein, described feedback control loop can also be active switch capacitance integrator, and switched-capacitor integrator is another implementation of Active RC integrator.

Wherein, described gain stage, as shown in Figure 7, comprise nmos pass transistor M1, M2, resistance R 1, R2, power vd D and the first current source, wherein nmos pass transistor M1, M2 and resistance R 1, R2 form differential input and output pair, resistance R 1 and resistance R 2 are connected to power vd D jointly, and the source electrode of M1 and M2 is connected the first current source ground connection.

Wherein, the first gain stage of described acceptance feedback and the second gain stage also comprise the grid of nmos pass transistor M3, M4, M3 and the grid of M4 right as the second difference input, it is right that the drain electrode of M3 and M4 is connected to difference output, and the source electrode of M3 and M4 is connected the second current source ground connection.

Should be understood that: above-described embodiment is just to explanation of the present invention; instead of limitation of the present invention; any replacement or amendment that does not exceed the change of innovation and creation within the scope of connotation of the present invention amendment, local structure to circuit, other unsubstantialities such as type or the replacement of model to components and parts, within all falling into protection range of the present invention.

Claims

1. a gain limiter circuit, is characterized in that comprising and has by N the gain stage that difference input and difference export and be connected in series successively,

Wherein, the difference input of the first gain stage is as the signal input part of gain limiter circuit, and the difference of afterbody gain stage is exported the signal output part as gain limiter circuit,

Wherein, also have the second difference input for receiving the gain stage of feedback, the difference output of K stage gain level feeds back to the second differential input signal of the M stage gain level that receives feedback by feedback control loop, and K is the arbitrary integer between 1 to N, and M is less than or equal to K,

Wherein, described gain limiter circuit comprises multiple feedback control loops and each gain stage is only comprised in a feedback control loop, and the electric capacity in each feedback control loop is integrated in gain limiter circuit inside.

2. gain limiter circuit as claimed in claim 1, is characterized in that described feedback control loop is RC low pass filter.

3. gain limiter circuit as claimed in claim 1, is characterized in that described feedback control loop is Gm-C low pass filter.

4. gain limiter circuit as claimed in claim 1, is characterized in that described feedback control loop is Active RC integrator.

5. gain limiter circuit as claimed in claim 1, is characterized in that described feedback control loop is active switch capacitance integrator.

6. gain limiter circuit as claimed in claim 1, it is characterized in that described gain stage comprises nmos pass transistor M1, M2, resistance R 1, R2, power vd D and the first current source, wherein nmos pass transistor M1, M2 and resistance R 1, R2 form differential input and output pair, resistance R 1 and resistance R 2 are connected to power vd D jointly, and the source electrode of M1 and M2 is connected the first current source ground connection.

7. gain limiter circuit as claimed in claim 5, it is characterized in that the gain stage of accepting feedback also comprises that the grid of nmos pass transistor M3, M4, M3 and the grid of M4 are right as the second difference input, it is right that the drain electrode of M3 and M4 is connected to difference output, and the source electrode of M3 and M4 is connected the second current source ground connection.