CN103236864B - The accepted theory that a kind of chip area reduces - Google Patents

The accepted theory that a kind of chip area reduces Download PDF

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CN103236864B
CN103236864B CN201310123786.1A CN201310123786A CN103236864B CN 103236864 B CN103236864 B CN 103236864B CN 201310123786 A CN201310123786 A CN 201310123786A CN 103236864 B CN103236864 B CN 103236864B
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nmos pass
transistor
pass transistor
drain electrode
nmos
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CN103236864A (en
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武振宇
王云峰
樊晓华
黄水龙
张海英
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Abstract

The invention discloses the accepted theory that a kind of chip area reduces, this circuit comprises subtracter, limiting amplifier chain, full-wave rectifier group, output buffer and DC maladjustment and extracts circuit.The present invention adopts new DC maladjustment to extract circuit, the chip area of whole circuit is significantly reduced, improves integrated level, reduce cost.Circuit structure of the present invention is simple, and working stability is reliable, can be applied to the receiver of Low Medium Frequency and zero intermediate frequency simultaneously, is particularly useful for zero intermediate frequency application.

Description

The accepted theory that a kind of chip area reduces
Technical field
The present invention relates to technical field of integrated circuits, particularly relate to the accepted theory that a kind of chip area reduces.
Background technology
Along with the development of wireless telecommunications, the requirement of people to low-power consumption and low cost is more and more higher.Because the intensity of receiver Received signal strength can in very large range change, so need the intensity of control signal under the prerequisite ensureing the error rate, to save the useful life of power consumption and prolongation battery.Controlled the gain of variable gain amplifier by the intensity detecting Received signal strength, to reach the object that power level controls, obtain stable output signal strength.
Received signal strength indicator (RSSI) circuit is module conventional in optical communication system and radio-frequency (RF) communication system, and it is for the purpose of power detection, is normally used for detecting current channel status.RSSI is actually a logarithmic amplifier, and the power of its amplitude outputed signal and input signal is linear.Amplitude limiter is used for amplifying the photosignal received or radiofrequency signal, with automatic gain controller (AutomaticGainControllor, AGC) compare, it can amplify input signal fast, and the square-wave signal after amplifying can directly process as digital signal, greatly simplify the design of subsequent demodulation circuit.
When zero intermediate frequency is applied, in RSSI, the DC maladjustment of amplitude limiting amplifier circuit is the problem needing to consider emphatically.If do not taken measures, the DC maladjustment signal of prime may block the intermediate-freuqncy signal of input, makes the amplifying circuit of rear class saturated in advance.Usually in RSSI circuit, add DC maladjustment eliminate circuit, the form feedovering and feed back can be taked to realize the elimination of DC maladjustment.
The existing many sections of designs of document to RSSI are studied.The people such as Yi-ChungChen adopt feedforward form to realize the elimination of DC maladjustment to every one-level limiting amplifier, and every one-level all needs RC low-pass filter circuit, needs larger area and not easily realizes low cut-off frequency.And the lower-cut-off frequency of entirety is limited to the highest first stage amplifier of lower-cut-off frequency, not easily determine and poor-performing.The people such as Po-ChiunHuang adopt overall negative feedback to realize DC maladjustment to limiting amplifier chain to suppress, for reaching low lower-cut-off frequency, have employed n trap resistance and external bulky capacitor and forming the extraction that low pass filter realizes DC offset voltage.Because the scheme of the people such as Po-ChiunHuang adopts fully differential structure, therefore need outward element and two extra pins.The people such as Chen Dianyu all adopt local negative feedback to every first stage amplifier, reduce the capacitance of required low pass filter, thus achieve the integrated of DC maladjustment elimination circuit.But every electric capacity needed for one-level still reaches 70pF, when multi-stage cascade, still can take considerable chip area.And the poles coincide of every one-level, the bandpass flatness of whole circuit will inevitably be had influence on.In sum, there is various defect in the RSSI circuit of prior art: chip area is comparatively large, and lower-cut-off frequency is higher and not easily determine, integrated level is poor, and outer member is more, and bandpass flatness is poor.
Summary of the invention
(1) technical problem that will solve
For the above-mentioned problems in the prior art, the invention provides the accepted theory that a kind of chip area reduces.
(2) technical scheme
For achieving the above object, the invention provides the accepted theory that a kind of chip area reduces, this circuit comprises subtracter, limiting amplifier chain, full-wave rectifier group, output buffer and DC maladjustment and extracts circuit, wherein:
Subtracter, for by the intermediate-freuqncy signal inputted from outside with extract the DC offset voltage that circuit inputs from DC maladjustment and subtract each other, and export the signal obtained to limiting amplifier chain and first order full-wave rectifier respectively;
Limiting amplifier chain, comprises the limiting amplifier of multiple series connection, and the intermediate-freuqncy signal that this limiting amplifier chain exports respectively input direct-current imbalance extracts circuit, output buffer and afterbody full-wave rectifier;
Full-wave rectifier group, comprise multistage full-wave rectifier, first order full-wave rectifier is connected between subtracter and limiting amplifier chain, second level full-wave rectifier is connected between first and second limiting amplifier in limiting amplifier chain, by that analogy, afterbody full-wave rectifier be connected in limiting amplifier chain between last limiting amplifier and output buffer, the output signal of each limiting amplifier also exports the full-wave rectifier be connected with its output to, and full-wave rectifier group exports receiving signal intensity indication signal;
Output buffer, for the intermediate-freuqncy signal of Buffer output limiting amplifier chain input;
DC maladjustment extracts circuit, extracts DC offset voltage, and export subtracter to in the intermediate-freuqncy signal that exports from this limiting amplifier chain.
In such scheme, described subtracter comprise first, second, the 5th to the 8th, o mono-and o bi-NMOS transistor (M 1, M 2, M 5-M 8, M o1, M o2), and the third and fourth PMOS transistor (M 3, M 4), wherein:
Supply voltage connects the 3rd PMOS transistor M 3with the 4th PMOS transistor M 4source electrode, the 3rd PMOS transistor M 3with the 4th PMOS transistor M 4grid meet bias voltage V bp, the 3rd PMOS transistor M 3drain electrode and the first nmos pass transistor M 1drain electrode connect, the 4th PMOS transistor M 4drain electrode and the second nmos pass transistor M 2drain electrode connect, the first nmos pass transistor M 1) and the second nmos pass transistor M 2source electrode meet the 7th nmos pass transistor M 7drain electrode, the 7th nmos pass transistor M 7source ground, the 7th nmos pass transistor M 7with the 8th nmos pass transistor M 8grid meet bias voltage V bn, the 8th nmos pass transistor M 8source ground, o mono-nmos pass transistor M o1with o bi-NMOS transistor M o2source electrode meet the 8th nmos pass transistor M 8drain electrode, o mono-nmos pass transistor M o1drain electrode meet the 5th nmos pass transistor M 5drain electrode, and with the first nmos pass transistor M 1drain electrode connect, the 5th nmos pass transistor M 5drain and gate connect, o bi-NMOS transistor M o2drain electrode meet the 6th nmos pass transistor M 6drain electrode, and with the second nmos pass transistor M 2drain electrode connect, the 6th nmos pass transistor M 6drain and gate connect;
First nmos pass transistor M 1with the second nmos pass transistor M 2grid as the input of intermediate-freuqncy signal, o mono-nmos pass transistor M o1with o bi-NMOS transistor M o2grid as the input of DC offset voltage, the first nmos pass transistor M 1with the second nmos pass transistor M 2drain electrode as the output of subtracter.
In such scheme, described limiting amplifier comprises the 30, the 31, the 32, the 37 and the 38 nmos pass transistor (M 30, M 31, M 32, M 37, M 38) and the 33 to the 36 PMOS transistor (M 33, M 34, M 35, M 36);
Supply voltage connects the 33 to the 36 PMOS transistor (M 33, M 34, M 35, M 36) source electrode, the 35 PMOS transistor M 35drain electrode and the 37 nmos pass transistor M 37drain electrode connect, the 37 nmos pass transistor M 37drain electrode be connected with grid, the 37 nmos pass transistor M 37source ground; 35 PMOS transistor M 35grid and the 33 PMOS transistor M 33grid connect, the 33 PMOS transistor M 33grid with drain electrode be connected, the 33 PMOS transistor M 33drain electrode and the 31 nmos pass transistor M 31drain electrode connect, the 31 nmos pass transistor M 31source electrode and the 30 nmos pass transistor M 30drain electrode connect, the 30 nmos pass transistor M 30source ground; 34 PMOS transistor M 34grid and the 36 PMOS transistor M 36grid connect, the 34 PMOS transistor M 34grid with drain electrode be connected, the 34 PMOS transistor M 34drain electrode and the 30 bi-NMOS transistor M 32drain electrode connect, the 30 bi-NMOS transistor M 32source electrode and the 30 nmos pass transistor M 30drain electrode connect; 36 PMOS transistor M 36drain electrode and the 38 nmos pass transistor M 38drain electrode connect, the 38 nmos pass transistor M 38drain electrode be connected with grid, the 38 nmos pass transistor M 38source ground;
31 nmos pass transistor M 31with the 30 bi-NMOS transistor M 32grid as the input of limiting amplifier, the 37 nmos pass transistor M 37with the 38 nmos pass transistor M 38drain electrode as the output of limiting amplifier.
In such scheme, described full-wave rectifier comprises the 41 to the 46 nmos pass transistor (M 41, M 42, M 43, M 44, M 45, M 46), the 47 to the 50 PMOS transistor (M 47, M 48, M 49, M 50);
Supply voltage connects the 47 to the 50 PMOS transistor (M 47, M 48, M 49, M 50) source electrode;
47 PMOS transistor M 47grid with drain electrode be connected, the 47 PMOS transistor M 47drain electrode respectively with the 41 nmos pass transistor M 41drain electrode and the 43 nmos pass transistor M 43drain electrode connect, the 41 nmos pass transistor M 41source electrode respectively with the 46 nmos pass transistor M 46drain electrode and the 44 nmos pass transistor M 44source electrode connect, bias voltage V bmeet the 46 nmos pass transistor M 46with the 45 nmos pass transistor M 45grid, the 46 nmos pass transistor M 46with the 45 nmos pass transistor M 45source ground; 41 nmos pass transistor M 41grid and the 40 bi-NMOS transistor M 42grid connect;
48 PMOS transistor M 48grid and the 47 PMOS transistor M 47grid connect, the 48 PMOS transistor M 48drain electrode respectively with the 40 bi-NMOS transistor M 42drain electrode, the 44 nmos pass transistor M 44drain electrode and the 49 PMOS transistor M 49drain electrode connect; 40 bi-NMOS transistor M 42source electrode and the 45 nmos pass transistor M 45drain electrode connect, the 43 nmos pass transistor M 43source electrode and the 45 nmos pass transistor M 45drain electrode connect, the 43 nmos pass transistor M 43grid and the 44 nmos pass transistor M 44grid connect;
49 PMOS transistor M 49drain and gate connect, the 49 PMOS transistor M 49grid and the 50 PMOS transistor M 50grid connect;
41 nmos pass transistor M 41grid and the 44 nmos pass transistor M 44grid as the input of full-wave rectifier, the 50 PMOS transistor M 50drain electrode as the output of full-wave rectifier.
In such scheme, described output buffer comprises the 51, the 52, the 55 to the 57 nmos pass transistor (M 51, M 52, M 55, M 56, M 57), the 53 and the 54 PMOS transistor (M 53, M 54) and first and second resistance (R 1, R 2);
Supply voltage connects the 53 and the 54 PMOS transistor M 53, M 54source electrode;
53 PMOS transistor M 53with the 54 PMOS transistor M 54grid connect, the 53 PMOS transistor M 53drain electrode through resistance R 1with the 53 PMOS transistor M 53grid connect, the 54 PMOS transistor M 54drain electrode through resistance R 2with the 54 PMOS transistor M 54grid connect;
53 PMOS transistor M 53drain electrode and the 51 nmos pass transistor M 51with the 55 nmos pass transistor M 55drain electrode connect, the 51 nmos pass transistor M 51source electrode and the 57 nmos pass transistor M 57drain electrode connect, the 57 nmos pass transistor M 57source ground, biased electrical crimping the 57 nmos pass transistor M 57grid; 54 PMOS transistor M 54drain electrode and the 50 bi-NMOS transistor M 52with the 56 nmos pass transistor M 56drain electrode connect, the 50 bi-NMOS transistor M 52source electrode and the 57 nmos pass transistor M 57drain electrode connect;
55 nmos pass transistor M 55drain and gate connect, the 55 nmos pass transistor M 55source ground; 56 nmos pass transistor M 56drain and gate connect, the 56 nmos pass transistor M 56source ground;
51 nmos pass transistor M 51with the 50 bi-NMOS transistor M 52grid as the input of output buffer, the 51 nmos pass transistor M 51with the 50 bi-NMOS transistor M 52drain electrode as the output of output buffer.
In such scheme, described DC maladjustment is extracted circuit and is comprised:
Connect into diode structure and be operated in first and second PMOS (M of cut-off region 1, M 2), this first and second PMOS (M 1, M 2) form two large resistance of equivalence; And
Electric capacity C 0, this electric capacity C 0be connected to first and second PMOS (M 1, M 2) source between;
Wherein, this first and second PMOS (M 1, M 2) and electric capacity C 0form low-pass filter structure.
In such scheme, described DC maladjustment is extracted circuit and is comprised:
Connect into diode structure and be operated in first of cut-off region and skim and the second slash NMOS tube (M 1', M 2'), this first slash and second skims NMOS tube (M 1', M 2') form two large resistance of equivalence; And
Electric capacity C 0', this electric capacity C 0' be connected to the first slash and the second slash NMOS tube (M 1', M 2') source between;
Wherein, this first slash and second skims NMOS tube (M 1', M 2') and electric capacity C 0' form low-pass filter structure.
In such scheme, the output of described full-wave rectifier is through the resistance of parallel connection and capacity earth.
(3) beneficial effect
As can be seen from technique scheme, the present invention has following beneficial effect:
1, the accepted theory that reduces of chip area provided by the invention, takies chip area little, and working stability is reliable, can be applied to the receiver of Low Medium Frequency and zero intermediate frequency simultaneously, is particularly useful for zero intermediate frequency application; DC maladjustment eliminates metal-oxide-semiconductor and the filter capacitor that circuit comprises the diode structure being operated in cut-off region, the cut-off region metal-oxide-semiconductor of diode structure easily can realize the resistance up to 1T ohm, thus substantially reduce required filter capacitor, chip area is significantly reduced.
2, the accepted theory that reduces of chip area provided by the invention, when the forward gain of amplitude limiter is up to 91dB, only needs the filter capacitor C of 4pF 0with the metal-oxide-semiconductor of W/L=220nm/300nm, the lower-cut-off frequency of whole circuit just can be made to reach 588Hz.By filter capacitor C 0realized by NMOS tube electric capacity, then the chip area that DC maladjustment now extracts circuit only has 45 μm × 15 μm.Compared with the RSSI circuit in the document delivered, the DC maladjustment size of extracting filter capacitor in circuit has been reduced to 4pF by the magnitude of tens to hundreds of pF, and the large resistance in filter circuit is also realized by undersized metal-oxide-semiconductor, these two measures all significantly reduce the area of domain.
3, the accepted theory that reduces of chip area provided by the invention, by adjusting the size of the cut-off metal-oxide-semiconductor of diode structure, easily can adjust the resistance of the large resistance of equivalence, thus realizing the adjustment of lower-cut-off frequency.
4, the accepted theory that reduces of chip area provided by the invention, limiting amplifier adopts the gain unit of current mirror form, makes gain only relevant with transistor size, significantly reduces the impact of process deviation.
5, the accepted theory that reduces of chip area provided by the invention, output buffer adopts that simple resistor common-mode feedback is stable exports DC level, and circuit structure is simple, and reliable operation, power consumption is less.
6, the accepted theory that reduces of chip area provided by the invention, circuit is extracted owing to adopting new DC maladjustment, significantly reduce chip area, there is peripheral components few, low cost, low-power consumption, high integration, detects dynamic range large, the features such as the linearity is good, can be widely used in radio communication, the various needs such as optical fiber communication is detected in the receiver of received signal strength.
Accompanying drawing explanation
Fig. 1 is the formation block diagram of the RSSI circuit that the chip area of the embodiment of the present invention reduces;
Fig. 2 is the circuit theory diagrams of the subtracter of the embodiment of the present invention;
Fig. 3 is the circuit theory diagrams of the limiting amplifier of the embodiment of the present invention;
Fig. 4 is the circuit theory diagrams of the full-wave rectifier of the embodiment of the present invention;
Fig. 5 is the circuit theory diagrams of the output buffer of the embodiment of the present invention;
Fig. 6 a is that the one of the DC maladjustment extraction circuit of the embodiment of the present invention forms block diagram;
Fig. 6 b is that the another kind of the DC maladjustment extraction circuit of the embodiment of the present invention forms block diagram;
Fig. 7 is the bandwidth sum gain characteristic curve figure of the RSSI circuit of the embodiment of the present invention;
Fig. 8 is the linear changing relation schematic diagram of output voltage with input power of the RSSI circuit of the embodiment of the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is the formation block diagram of the RSSI circuit that the chip area of the embodiment of the present invention reduces, and this circuit comprises subtracter, limiting amplifier chain, full-wave rectifier group, output buffer and DC maladjustment and extracts circuit.Wherein: subtracter, for by the intermediate-freuqncy signal inputted from outside with extract the DC offset voltage that circuit inputs from DC maladjustment and subtract each other, and export the signal obtained to limiting amplifier chain and first order full-wave rectifier respectively; Limiting amplifier chain, comprises the limiting amplifier of multiple series connection, and the intermediate-freuqncy signal that this limiting amplifier chain exports respectively input direct-current imbalance extracts circuit, output buffer and afterbody full-wave rectifier; Full-wave rectifier group, comprise multistage full-wave rectifier, first order full-wave rectifier is connected between subtracter and limiting amplifier chain, second level full-wave rectifier is connected between first and second limiting amplifier in limiting amplifier chain, by that analogy, afterbody full-wave rectifier be connected in limiting amplifier chain between last limiting amplifier and output buffer, the output signal of each limiting amplifier also exports the full-wave rectifier be connected with its output to, and full-wave rectifier group exports receiving signal intensity indication signal; Output buffer, for the intermediate-freuqncy signal of Buffer output limiting amplifier chain input; DC maladjustment extracts circuit, extracts DC offset voltage, and export subtracter to in the intermediate-freuqncy signal that exports from this limiting amplifier chain.The output of full-wave rectifier is through the resistance of parallel connection and capacity earth.
In FIG, intermediate frequency input, by one group of input of subtracter, sends into limiting amplifier chain, and the output of limiting amplifier chain connects output buffer, connects the input that DC maladjustment extracts circuit simultaneously; The input of the input and output buffer of every one-level of limiting amplifier chain all connects the input of a full-wave rectifier, the output of full-wave rectifier is sued for peace through overcurrent, on the low pass filter that external resistance and electric capacity form, obtain the RSSI output voltage of indicative input signal amplitude; Output buffer exports the intermediate-freuqncy signal through amplifying, for late-class circuit process; DC maladjustment extracts the DC component of circuit extraction output signal, sends into another group input of subtracter, thus DC maladjustment is deducted from input signal.The DC maladjustment that DC maladjustment extraction circuit and subtracter together form RSSI circuit eliminates circuit.
As shown in Figure 2, Fig. 2 is the circuit theory diagrams of the subtracter of the embodiment of the present invention, this subtracter comprise first, second, the 5th to the 8th, o mono-and o bi-NMOS transistor (M 1, M 2, M 5-M 8, M o1, M o2), and the third and fourth PMOS transistor (M 3, M 4).Wherein, supply voltage connects the 3rd PMOS transistor M 3with the 4th PMOS transistor M 4source electrode, the 3rd PMOS transistor M 3with the 4th PMOS transistor M 4grid meet bias voltage V bp, the 3rd PMOS transistor M 3drain electrode and the first nmos pass transistor M 1drain electrode connect, the 4th PMOS transistor M 4drain electrode and the second nmos pass transistor M 2drain electrode connect, the first nmos pass transistor M 1with the second nmos pass transistor M 2source electrode meet the 7th nmos pass transistor M 7drain electrode, the 7th nmos pass transistor M 7source ground, the 7th nmos pass transistor M 7with the 8th nmos pass transistor M 8grid meet bias voltage V bn, the 8th nmos pass transistor M 8source ground, o mono-nmos pass transistor M o1with o bi-NMOS transistor M o2source electrode meet the 8th nmos pass transistor M 8drain electrode, o mono-nmos pass transistor M o1drain electrode meet the 5th nmos pass transistor M 5drain electrode, and with the first nmos pass transistor M 1drain electrode connect, the 5th nmos pass transistor M 5drain and gate connect, o bi-NMOS transistor M o2drain electrode meet the 6th nmos pass transistor M 6drain electrode, and with the second nmos pass transistor M 2drain electrode connect, the 6th nmos pass transistor M 6drain and gate connect; First nmos pass transistor M 1with the second nmos pass transistor M 2grid as the input of intermediate-freuqncy signal, o mono-nmos pass transistor M o1with o bi-NMOS transistor M o2grid as the input of DC offset voltage, the first nmos pass transistor M 1with the second nmos pass transistor M 2drain electrode as the output of subtracter.
In fig. 2, nmos pass transistor M 1, M 2for input difference pair, two ends vinp, vinn of input signal meet nmos pass transistor M 1, M 2grid, M o1, M o2for DC maladjustment input difference pair, the drain terminal of two groups of input pipes adopts cross connecting structure, realizes the function that input signal subtracts each other.PMOS transistor M 3, M 4by voltage V bpbiased, PMOS transistor M 3, M 4source electrode meet power supply V dD, for circuit provides current source, nmos pass transistor M 7, M 8it is the tail current source of two groups of differential pairs.Nmos pass transistor M 5, M 6for the load pipe that diode connects.The gain of subtracter is arranged on about 0dB.Output signal Voutn, the Voutp of subtracter access the input of limiting amplifier chain.
As shown in Figure 3, Fig. 3 is the circuit theory diagrams of the limiting amplifier of the embodiment of the present invention.Limiting amplifier comprises the 30, the 31, the 32, the 37 and the 38 nmos pass transistor (M 30, M 31, M 32, M 37, M 38) and the 33 to the 36 PMOS transistor (M 33, M 34, M 35, M 36); Supply voltage connects the 33 to the 36 PMOS transistor (M 33, M 34, M 35, M 36) source electrode, the 35 PMOS transistor M 35drain electrode and the 37 nmos pass transistor M 37drain electrode connect, the 37 nmos pass transistor M 37drain electrode be connected with grid, the 37 nmos pass transistor M 37source ground; 35 PMOS transistor M 35grid and the 33 PMOS transistor M 33grid connect, the 33 PMOS transistor M 33grid with drain electrode be connected, the 33 PMOS transistor M 33drain electrode and the 31 nmos pass transistor M 31drain electrode connect, the 31 nmos pass transistor M 31source electrode and the 30 nmos pass transistor M 30drain electrode connect, the 30 nmos pass transistor M 30source ground; 34 PMOS transistor M 34grid and the 36 PMOS transistor M 36grid connect, the 34 PMOS transistor M 34grid with drain electrode be connected, the 34 PMOS transistor M 34drain electrode and the 30 bi-NMOS transistor M 32drain electrode connect, the 30 bi-NMOS transistor M 32source electrode and the 30 nmos pass transistor M 30drain electrode connect; 36 PMOS transistor M 36drain electrode and the 38 nmos pass transistor M 38drain electrode connect, the 38 nmos pass transistor M 38drain electrode be connected with grid, the 38 nmos pass transistor M 38source ground; 31 nmos pass transistor M 31with the 30 bi-NMOS transistor M 32grid as the input of limiting amplifier, the 37 nmos pass transistor M 37with the 38 nmos pass transistor M 38drain electrode as the output of limiting amplifier.
In figure 3, nmos pass transistor M 30, M 31, M 32form input difference pair, two ends Vinp3, Vinn3 of input signal meet nmos pass transistor M 31, M 32grid, PMOS transistor M 33, M 35with PMOS transistor M 34, M 36form the current-mirror structure of 1: 1, PMOS transistor M 35, M 36drain electrode output signal Voutp3, Voutn3, nmos pass transistor M 37, M 38for the load pipe that diode connects.Such input pipe and load pipe have identical bias current, and the gain of limiting amplifier is:
A v = g m 1 g m 7 = ( W / L ) 1 ( W / L ) 7 - - - ( 1 )
Visible, gain is only relevant to the ratio of transistor size, thus significantly reduces the impact of process corner deviation on circuit performance.
As shown in Figure 4, Fig. 4 is the circuit theory diagrams of the full-wave rectifier of the embodiment of the present invention.Full-wave rectifier comprises the 41 to the 46 nmos pass transistor (M 41, M 42, M 43, M 44, M 45, M 46), the 47 to the 50 PMOS transistor (M 47, M 48, M 49, M 50); Supply voltage connects the 47 to the 50 PMOS transistor (M 47, M 48, M 49, M 50) source electrode; 47 PMOS transistor M 47grid with drain electrode be connected, the 47 PMOS transistor M 47drain electrode respectively with the 41 nmos pass transistor M 41drain electrode and the 43 nmos pass transistor M 43drain electrode connect, the 41 nmos pass transistor M 41source electrode respectively with the 46 nmos pass transistor M 46drain electrode and the 44 nmos pass transistor M 44source electrode connect, bias voltage V bmeet the 46 nmos pass transistor M 46with the 45 nmos pass transistor M 45grid, the 46 nmos pass transistor M 46with the 45 nmos pass transistor M 45source ground; 41 nmos pass transistor M 41grid and the 40 bi-NMOS transistor M 42grid connect; 48 PMOS transistor M 48grid and the 47 PMOS transistor M 47grid connect, the 48 PMOS transistor M 48drain electrode respectively with the 40 bi-NMOS transistor M 42drain electrode, the 44 nmos pass transistor M 44drain electrode and the 49 PMOS transistor M 49drain electrode connect; 40 bi-NMOS transistor M 42source electrode and the 45 nmos pass transistor M 45drain electrode connect, the 43 nmos pass transistor M 43source electrode and the 45 nmos pass transistor M 45drain electrode connect, the 43 nmos pass transistor M 43grid and the 44 nmos pass transistor M 44grid connect; 49 PMOS transistor M 49drain and gate connect, the 49 PMOS transistor M 49grid and the 50 PMOS transistor M 50grid connect; 41 nmos pass transistor M 41grid and the 44 nmos pass transistor M 44grid as the input of full-wave rectifier, the 50 PMOS transistor M 50drain electrode as the output of full-wave rectifier.
In the diagram, circuit adopts nonequilibrium source-coupled to structure, by nmos pass transistor M 42, M 43, M 45with nmos pass transistor M 41, M 44, M 46two pairs of non-equilibrium Differential Input form pipe, and input signal Vinp4, Vinn4 meet nmos pass transistor M 41, M 44grid.Nmos pass transistor M 42, M 44size elect nmos pass transistor M as 41, M 43k doubly (K is integer).PMOS transistor M 47, M 48with PMOS transistor M 49, M 50be respectively two groups of current mirrors, PMOS transistor M 50drain electrode as output output current Iout.Like this, nmos pass transistor M 42with nmos pass transistor M 44electric current sum deduct nmos pass transistor M 41with nmos pass transistor M 43electric current sum just obtain full-wave rectifier electric current export.When inputting within the specific limits, output current and input voltage just obtain the logarithmic relationship be similar to.The scope exported with being entered as logarithmic relationship can be adjusted by adjustment K value.
As shown in Figure 5, Fig. 5 is the circuit theory diagrams of the output buffer of the embodiment of the present invention.Output buffer comprises the 51, the 52, the 55 to the 57 nmos pass transistor (M 51, M 52, M 55, M 56, M 57), the 53 and the 54 PMOS transistor (M 53, M 54) and first and second resistance (R 1, R 2); Supply voltage connects the 53 and the 54 PMOS transistor (M 53, M 54) source electrode; 53 PMOS transistor M 53with the 54 PMOS transistor M 54grid connect, the 53 PMOS transistor M 53drain electrode through resistance R 1with the 53 PMOS transistor M 53grid connect, the 54 PMOS transistor M 54drain electrode through resistance R 2with the 54 PMOS transistor M 54grid connect; 53 PMOS transistor M 53drain electrode and the 51 nmos pass transistor M 51with the 55 nmos pass transistor M 55drain electrode connect, the 51 nmos pass transistor M 51source electrode and the 57 nmos pass transistor M 57drain electrode connect, the 57 nmos pass transistor M 57source ground, biased electrical crimping the 57 nmos pass transistor M 57grid; 54 PMOS transistor M 54drain electrode and the 50 bi-NMOS transistor M 52with the 56 nmos pass transistor M 56drain electrode connect, the 50 bi-NMOS transistor M 52source electrode and the 57 nmos pass transistor M 57drain electrode connect; 55 nmos pass transistor M 55drain and gate connect, the 55 nmos pass transistor M 55source ground; 56 nmos pass transistor M 56drain and gate connect, the 56 nmos pass transistor M 56source ground; 51 nmos pass transistor M 51with the 50 bi-NMOS transistor M 52grid as the input of output buffer, the 51 nmos pass transistor M 51with the 50 bi-NMOS transistor M 52drain electrode as the output of output buffer.
In Figure 5, nmos pass transistor M 51, M 52, M 57form input difference pair, PMOS transistor M 53, M 54for current source, nmos pass transistor M 55, M 56form the load pipe that diode connects.Resistance R 1with resistance R 2for common-mode feedback resistor, stablize output common mode level.Two ends Vinp_buf, Vinn_buf of input signal meet nmos pass transistor M 51, M 52grid, PMOS transistor M 53, M 54drain electrode output signal Von_buf, Vop_buf.
As shown in Figure 6 a, Fig. 6 a is the one formation block diagram of the DC maladjustment extraction circuit of the embodiment of the present invention.This DC maladjustment is extracted circuit and is comprised: connect into diode structure and be operated in first and second PMOS (M of cut-off region 1, M 2), this first and second PMOS (M 1, M 2) form two large resistance of equivalence; And electric capacity C 0, this electric capacity C 0be connected to first and second PMOS (M 1, M 2) source between; Wherein, this first and second PMOS (M 1, M 2) and electric capacity C 0form low-pass filter structure.
In Fig. 6 a, input Vinp_buf and Vinn_buf of output buffer, respectively by low pass filter, extracts the DC maladjustment component of output signal, is respectively Vosp and Vosn, send into one group of input of subtracter, DC maladjustment is deducted from the input signal of RSSI.Low pass filter is by the PMOS M of diode structure 0, M 1with the electric capacity C being connected across metal-oxide-semiconductor source 0composition.Because PMOS is operated in cut-off region, the large resistance of equivalence up to 1T ohm can be realized easily.Like this, the electric capacity of metal-oxide-semiconductor source cross-over connection can adopt less numerical value, and realizes good filter effect.In the present embodiment, C 0get 4pF, realized by nmos pipe electric capacity, the large resistance for filtering is realized by the PMOS of W/L=220n/300n, and the chip area that whole DC maladjustment extracts circuit only has 45 μm × 15 μm.Result in the comprehensive document delivered both at home and abroad, if fully integrated in sheet, DC maladjustment in RSSI circuit extracts circuit, the half that generally account for RSSI circuit layout area is even more, therefore, the RSSI circuit of the embodiment of the present invention significantly reduces chip area, achieves higher integrated level and lower cost.
As shown in Figure 6 b, Fig. 6 b is the another kind formation block diagram of the DC maladjustment extraction circuit of the embodiment of the present invention.This DC maladjustment is extracted circuit and is comprised: connect into diode structure and be operated in first of cut-off region and skim and the second slash NMOS tube (M 1', M 2'), this first slash and second skims NMOS tube (M 1', M 2') form two large resistance of equivalence; And electric capacity C 0', this electric capacity C 0' be connected to the first slash and the second slash NMOS tube (M 1', M 2') source between; Wherein, this first slash and second skims NMOS tube (M 1', M 2') and electric capacity C 0' form low-pass filter structure.
In figure 6b, input Vinp_buf and Vinn_buf of output buffer, respectively by low pass filter, extracts the DC maladjustment component of output signal, is respectively Vosp and Vosn, send into one group of input of subtracter, DC maladjustment is deducted from the input signal of RSSI.Low pass filter is by the NMOS tube M of diode structure 0', M 1' and be connected across the electric capacity C of metal-oxide-semiconductor source 0' composition.Because NMOS tube is operated in cut-off region, the large resistance of equivalence up to 1T ohm can be realized easily.Like this, the electric capacity of metal-oxide-semiconductor source cross-over connection can adopt less numerical value, and realizes good filter effect.
Fig. 7 is the bandwidth sum gain characteristic curve figure of the RSSI circuit of the embodiment of the present invention.When the gain of limiting amplifier is 91dB, the lower-cut-off frequency of the embodiment of the present invention reaches 588Hz, and upper cut-off frequency is 218MHz.
Fig. 8 is the linear changing relation schematic diagram of output voltage with input power of the RSSI circuit of the embodiment of the present invention.Can be seen by Fig. 8, when RSSI input signal changes from-90 ~-5dBm, output voltage linearly drops to 0.36V from 1.53V, achieves the linear detection range of about 85dB.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (6)

1. the accepted theory that reduces of chip area, is characterized in that, this circuit comprises subtracter, limiting amplifier chain, full-wave rectifier group, output buffer and DC maladjustment and extracts circuit, wherein:
Subtracter, for by the intermediate-freuqncy signal inputted from outside with extract the DC offset voltage that circuit inputs from DC maladjustment and subtract each other, and export the signal obtained to limiting amplifier chain and first order full-wave rectifier respectively;
Limiting amplifier chain, comprises the limiting amplifier of multiple series connection, and the intermediate-freuqncy signal that this limiting amplifier chain exports respectively input direct-current imbalance extracts circuit, output buffer and afterbody full-wave rectifier;
Full-wave rectifier group, comprise multistage full-wave rectifier, first order full-wave rectifier is connected between subtracter and limiting amplifier chain, second level full-wave rectifier is connected between first and second limiting amplifier in limiting amplifier chain, by that analogy, afterbody full-wave rectifier be connected in limiting amplifier chain between last limiting amplifier and output buffer, the output signal of each limiting amplifier also exports the full-wave rectifier be connected with its output to, and full-wave rectifier group exports receiving signal intensity indication signal;
Output buffer, for the intermediate-freuqncy signal of Buffer output limiting amplifier chain input;
DC maladjustment extracts circuit, extracts DC offset voltage, and export subtracter to in the intermediate-freuqncy signal that exports from this limiting amplifier chain;
Wherein, described DC maladjustment is extracted circuit and is comprised: connect into diode structure and be operated in first and second PMOS (M of cut-off region 1, M 2), this first and second PMOS (M 1, M 2) form two large resistance of equivalence; And electric capacity C 0, this electric capacity C 0be connected to first and second PMOS (M 1, M 2) source between; Wherein, this first and second PMOS (M 1, M 2) and electric capacity C 0form low-pass filter structure; Or
Described DC maladjustment is extracted circuit and is comprised: connect into diode structure and be operated in first of cut-off region and skim and the second slash NMOS tube (M 1', M 2'), this first slash and second skims NMOS tube (M 1', M 2') form two large resistance of equivalence; And electric capacity C 0', this electric capacity C 0' be connected to the first slash and the second slash NMOS tube (M 1', M 2') source between; Wherein, this first slash and second skims NMOS tube (M 1', M 2') and electric capacity C 0' form low-pass filter structure.
2. the accepted theory that reduces of chip area according to claim 1, is characterized in that, described subtracter comprise first, second, the 5th to the 8th, o mono-and o bi-NMOS transistor (M 1, M 2, M 5-M 8, M o1, M o2), and the third and fourth PMOS transistor (M 3, M 4), wherein:
Supply voltage connects the 3rd PMOS transistor (M 3) and the 4th PMOS transistor (M 4) source electrode, the 3rd PMOS transistor (M 3) and the 4th PMOS transistor (M 4) grid meet bias voltage (V bp), the 3rd PMOS transistor (M 3) drain electrode and the first nmos pass transistor (M 1) drain electrode connect, the 4th PMOS transistor (M 4) drain electrode and the second nmos pass transistor (M 2) drain electrode connect, the first nmos pass transistor (M 1) and the second nmos pass transistor (M 2) source electrode meet the 7th nmos pass transistor (M 7) drain electrode, the 7th nmos pass transistor (M 7) source ground, the 7th nmos pass transistor (M 7) and the 8th nmos pass transistor (M 8) grid meet bias voltage (V bn), the 8th nmos pass transistor (M 8) source ground, o mono-nmos pass transistor (M o1) and o bi-NMOS transistor (M o2) source electrode meet the 8th nmos pass transistor (M 8) drain electrode, o mono-nmos pass transistor (M o1) drain electrode meet the 5th nmos pass transistor (M 5) drain electrode, and with the first nmos pass transistor (M 1) drain electrode connect, the 5th nmos pass transistor (M 5) drain and gate connect, o bi-NMOS transistor (M o2) drain electrode meet the 6th nmos pass transistor (M 6) drain electrode, and with the second nmos pass transistor (M 2) drain electrode connect, the 6th nmos pass transistor (M 6) drain and gate connect;
First nmos pass transistor (M 1) and the second nmos pass transistor (M 2) grid as the input of intermediate-freuqncy signal, o mono-nmos pass transistor (M o1) and o bi-NMOS transistor (M o2) grid as the input of DC offset voltage, the first nmos pass transistor (M 1) and the second nmos pass transistor (M 2) drain electrode as the output of subtracter.
3. the accepted theory that reduces of chip area according to claim 1, is characterized in that, described limiting amplifier comprises the 30, the 31, the 32, the 37 and the 38 nmos pass transistor (M 30, M 31, M 32, M 37, M 38) and the 33 to the 36 PMOS transistor (M 33, M 34, M 35, M 36);
Supply voltage connects the 33 to the 36 PMOS transistor (M 33, M 34, M 35, M 36) source electrode, the 35 PMOS transistor (M 35) drain electrode and the 37 nmos pass transistor (M 37) drain electrode connect, the 37 nmos pass transistor (M 37) drain electrode be connected with grid, the 37 nmos pass transistor (M 37) source ground; 35 PMOS transistor (M 35) grid and the 33 PMOS transistor (M 33) grid connect, the 33 PMOS transistor (M 33) grid with drain electrode be connected, the 33 PMOS transistor (M 33) drain electrode and the 31 nmos pass transistor (M 31) drain electrode connect, the 31 nmos pass transistor (M 31) source electrode and the 30 nmos pass transistor (M 30) drain electrode connect, the 30 nmos pass transistor (M 30) source ground; 34 PMOS transistor (M 34) grid and the 36 PMOS transistor (M 36) grid connect, the 34 PMOS transistor (M 34) grid with drain electrode be connected, the 34 PMOS transistor (M 34) drain electrode and the 30 bi-NMOS transistor (M 32) drain electrode connect, the 30 bi-NMOS transistor (M 32) source electrode and the 30 nmos pass transistor (M 30) drain electrode connect; 36 PMOS transistor (M 36) drain electrode and the 38 nmos pass transistor (M 38) drain electrode connect, the 38 nmos pass transistor (M 38) drain electrode be connected with grid, the 38 nmos pass transistor (M 38) source ground;
31 nmos pass transistor (M 31) and the 30 bi-NMOS transistor (M 32) grid as the input of limiting amplifier, the 37 nmos pass transistor (M 37) and the 38 nmos pass transistor (M 38) drain electrode as the output of limiting amplifier.
4. the accepted theory that reduces of chip area according to claim 1, it is characterized in that, described full-wave rectifier comprises the 41 to the 46 nmos pass transistor (M 41, M 42, M 43, M 44, M 45, M 46), the 47 to the 50 PMOS transistor (M 47, M 48, M 49, M 50);
Supply voltage connects the 47 to the 50 PMOS transistor (M 47, M 48, M 49, M 50) source electrode;
47 PMOS transistor (M 47) grid with drain electrode be connected, the 47 PMOS transistor (M 47) drain electrode respectively with the 41 nmos pass transistor (M 41) drain electrode and the 43 nmos pass transistor (M 43) drain electrode connect, the 41 nmos pass transistor (M 41) source electrode respectively with the 46 nmos pass transistor (M 46) drain electrode and the 44 nmos pass transistor (M 44) source electrode connect, bias voltage (V b) meet the 46 nmos pass transistor (M 46) and the 45 nmos pass transistor (M 45) grid, the 46 nmos pass transistor (M 46) and the 45 nmos pass transistor (M 45) source ground; 41 nmos pass transistor (M 41) grid and the 40 bi-NMOS transistor (M 42) grid connect;
48 PMOS transistor (M 48) grid and the 47 PMOS transistor (M 47) grid connect, the 48 PMOS transistor (M 48) drain electrode respectively with the 40 bi-NMOS transistor (M 42) drain electrode, the 44 nmos pass transistor (M 44) drain electrode and the 49 PMOS transistor (M 49) drain electrode connect; 40 bi-NMOS transistor (M 42) source electrode and the 45 nmos pass transistor (M 45) drain electrode connect, the 43 nmos pass transistor (M 43) source electrode and the 45 nmos pass transistor (M 45) drain electrode connect, the 43 nmos pass transistor (M 43) grid and the 44 nmos pass transistor (M 44) grid connect;
49 PMOS transistor (M 49) drain and gate connect, the 49 PMOS transistor (M 49) grid and the 50 PMOS transistor (M 50) grid connect;
41 nmos pass transistor (M 41) grid and the 44 nmos pass transistor (M 44) grid as the input of full-wave rectifier, the 50 PMOS transistor (M 50) drain electrode as the output of full-wave rectifier.
5. the accepted theory that reduces of chip area according to claim 1, is characterized in that, described output buffer comprises the 51, the 52, the 55 to the 57 nmos pass transistor (M 51, M 52, M 55, M 56, M 57), the 53 and the 54 PMOS transistor (M 53, M 54) and first and second resistance (R 1, R 2);
Supply voltage connects the 53 and the 54 PMOS transistor (M 53, M 54) source electrode;
53 PMOS transistor (M 53) and the 54 PMOS transistor (M 54) grid connect, the 53 PMOS transistor (M 53) drain electrode through resistance (R 1) and the 53 PMOS transistor (M 53) grid connect, the 54 PMOS transistor (M 54) drain electrode through resistance (R 2) and the 54 PMOS transistor (M 54) grid connect;
53 PMOS transistor (M 53) drain electrode and the 51 nmos pass transistor (M 51) and the 55 nmos pass transistor (M 55) drain electrode connect, the 51 nmos pass transistor (M 51) source electrode and the 57 nmos pass transistor (M 57) drain electrode connect, the 57 nmos pass transistor (M 57) source ground, biased electrical crimping the 57 nmos pass transistor (M 57) grid; 54 PMOS transistor (M 54) drain electrode and the 50 bi-NMOS transistor (M 52) and the 56 nmos pass transistor (M 56) drain electrode connect, the 50 bi-NMOS transistor (M 52) source electrode and the 57 nmos pass transistor (M 57) drain electrode connect;
55 nmos pass transistor (M 55) drain and gate connect, the 55 nmos pass transistor (M 55) source ground; 56 nmos pass transistor (M 56) drain and gate connect, the 56 nmos pass transistor (M 56) source ground;
51 nmos pass transistor (M 51) and the 50 nmos pass transistor (M 52) grid as the input of output buffer, the 51 nmos pass transistor (M 51) and the 50 bi-NMOS transistor (M 52) drain electrode as the output of output buffer.
6. the accepted theory that reduces of chip area according to claim 4, is characterized in that, the output of described full-wave rectifier is through the resistance of parallel connection and capacity earth.
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CN103762950B (en) * 2013-12-26 2017-04-26 中生(苏州)医疗仪器有限公司 Large dynamic range amplifying circuit and establishing method thereof
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CN104601186B (en) * 2014-11-19 2017-05-17 深圳市中兴微电子技术有限公司 Direct-current offset calibration method and device
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