CN108170624B - Noise monitoring circuit applied to high-speed interface bus - Google Patents

Noise monitoring circuit applied to high-speed interface bus Download PDF

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Publication number
CN108170624B
CN108170624B CN201810127155.XA CN201810127155A CN108170624B CN 108170624 B CN108170624 B CN 108170624B CN 201810127155 A CN201810127155 A CN 201810127155A CN 108170624 B CN108170624 B CN 108170624B
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CN108170624A (en
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戴澜
陈纲
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Shanghai Xinwen Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a noise monitoring circuit applied to a high-speed interface bus, which comprises a fixed gain signal amplifying sub-circuit, an amplitude extracting sub-circuit and a comparing and judging sub-circuit; wherein: the fixed gain signal amplifying sub-circuit is used for effectively amplifying signals to be input into the interface bus; the amplitude extraction sub-circuit is used for carrying out envelope extraction on the signal amplified by the fixed gain signal amplifying sub-circuit to obtain the amplitude VOA of the signal; the comparison judging sub-circuit is used for judging the amplitude VOA of the extracted signal and judging whether the signal is a useful signal or a noise signal. The noise monitoring circuit can accurately judge whether the signal input amplitude of the bus entering the idle state is a noise signal or a useful signal, thereby effectively improving the service efficiency of the interface bus and reducing the power consumption of the high-speed bus.

Description

Noise monitoring circuit applied to high-speed interface bus
Technical Field
The present invention relates to a high-speed serial transmission system design technology, and more particularly, to a noise monitoring circuit applied to a high-speed interface bus.
Background
In recent years, with the wide application and continuous development of modern high technologies such as wireless communication, satellite positioning, remote control and telemetry technology, precision guidance and the like, the application of a high-speed serial interface bus such as a chip design technology becomes a new hot spot in the semiconductor industry.
Almost all high-performance chips adopt a differential bus interface circuit, but when the differential bus interface circuit is in an idle state, noise is usually introduced into an error code, so bus transmission errors are caused, and therefore, a noise signal in the bus idle state needs to be judged, namely whether the magnitude of the differential signal is a useful signal or a noise signal needs to be judged. Thus, the noise monitoring circuit is very significant for differential bus interface circuits.
In a high-speed interface bus circuit, the bus is often in an idle state, and when the bus is in the idle state, noise enters the bus to make the bus mistakenly think that the interface has signal access, so a special circuit form is needed to judge whether the bus is in the idle state, that is, whether an access signal is noise or a useful signal.
Disclosure of Invention
Therefore, a primary object of the present invention is to provide a noise monitoring circuit for a high-speed interface bus, so as to accurately determine whether the input amplitude of a signal entering an idle state bus is a noise signal or a useful signal, thereby effectively improving the service efficiency of the interface bus and reducing the power consumption of the high-speed bus.
In order to achieve the above purpose, the technical scheme of the invention is realized as follows:
the noise monitoring circuit comprises a fixed gain signal amplifying sub-circuit, an amplitude extracting sub-circuit and a comparison judging sub-circuit; wherein:
the fixed gain signal amplifying sub-circuit is used for effectively amplifying signals to be input into the interface bus;
the amplitude extraction sub-circuit is used for carrying out envelope extraction on the signal amplified by the fixed gain signal amplification sub-circuit to obtain the amplitude of the signal;
and the comparison and judgment sub-circuit is used for judging the amplitude of the extracted signal according to the reference voltage threshold value and judging whether the signal is a useful signal or a noise signal.
Wherein: the fixed gain signal amplifying sub-circuit comprises a two-stage differential amplifier circuit, and specifically comprises:
in the first-stage differential amplifier sub-circuit, the gates G of the transistors M1 and M2 are connected to VinA and VinB, respectively; the drain electrode D of the transistor M1 and the drain electrode D of the transistor M2 are respectively connected with one end of a resistor R5 and one end of a resistor R6 in series, the other ends of the resistor R5 and the resistor R6 are connected with a resistor R4 in parallel, and the other end of the resistor R4 is connected with the end of the working voltage VDDA; the source S of the transistor M1 and the source S of the transistor M2 are connected in parallel and then connected with the negative electrode of the current source Ki1, and the positive electrode of the current source Ki1 is connected with the working ground GND1;
in the second-stage differential amplifier sub-circuit, the gate G of the transistor M4 and the gate G of the transistor M3 are connected to the drain D of the transistor M1 and the drain D of the transistor M2, respectively; the drain electrode D of the transistor M3 and the drain electrode D of the transistor M4 are respectively connected with one ends of a resistor R7 and a resistor R8, and the other ends of the resistor R7 and the resistor R8 are connected in parallel and then are connected with the end of the working voltage VDDA; the source S of the transistor M3 and the source S of the transistor M4 are connected in parallel and then connected with the cathode of the current source Ki2, and the anode of the current source Ki2 is connected with the working ground GND1;
the drain D of the transistor M3 and the drain D of the transistor M4 of the second stage differential amplifier sub-circuit serve as signal output terminals VFA and VFB, respectively.
Wherein: the amplitude extraction sub-circuit has the following specific circuit structure:
the grid G of the transistor M12 and the grid G of the transistor M9 are respectively and electrically connected with the signal output ends VFA and VFB of the fixed gain signal amplifying sub-circuit; the drain electrode D of the transistor M9 and the drain electrode D of the transistor M12 are connected with the working voltage VDDA; the source S of the transistor M9 and the source S of the transistor M12 are connected to the drain D of the transistor M29 and the drain D of the transistor M28, respectively; the gate G of the transistor M29 and the gate G of the transistor M28 are connected in series, and the source S of the transistor M29 and the source S of the transistor M28 are connected in parallel and then connected to the working ground GND1;
a signal line connecting the source electrode S of the transistor M9 and the source electrode S of the transistor M12 is used as an output end of the signal VOA extracted by the amplitude detection; a transistor M10 and a resistor R9 are connected between the drain electrode D of the transistor M9 and the signal line VOA in a bridging manner, and a capacitor C2 is connected between the source electrode S of the transistor M29 and the signal line VOA in a parallel manner; a transistor M11 and a resistor R10 are connected between the drain D of the transistor M12 and the signal line VOA in a bridging manner, and a capacitor C3 is connected between the source S of the transistor M28 and the signal line VOA in a parallel manner; the gate G of the transistor M10 and the gate G of the transistor M11 are connected in series, and are connected with a bias current BIASP.
Wherein: the comparison judging sub-circuit has the following specific circuit structure:
the signal line VOA is connected to a gate G of the transistor M16, a drain D of the transistor M16 is connected to a drain D of the transistor M18, the gate G of the transistor M18 is connected to a gate G of the transistor M19, and a source S of the transistor M18 is connected to a drain D of the transistor M19;
the drain D of the transistor M16 is connected with the gate G of the transistor M18; the source S of the transistor M16 and the source S of the transistor M17 are connected in parallel and then connected to the drain D of the transistor M20, the gate G of the transistor M20 is connected to the voltage Vc, and the source S of the transistor M20 is connected to the working ground GND1;
the gate G of the transistor M17 is connected to the reference voltage Vref, and the source S of the transistor M19 is connected to the drain D of the transistor M17 as an output signal line Vout for comparing and judging signals.
The noise monitoring circuit applied to the high-speed interface bus has the following beneficial effects:
the noise monitoring circuit can judge according to the input amplitude of the signal, and the amplitude of the noise is usually far smaller than that of the signal, and can accurately judge whether the input signal is noise or useful signal through a series of signal processing processes, namely fixed gain signal amplification, signal amplitude extraction and comparison judging processes, so that the use efficiency of the bus is effectively improved, and the power consumption of the high-speed differential bus is reduced.
The noise monitoring circuit is a highly symmetrical circuit structure and has the characteristics of simple structure and low power consumption.
Drawings
FIG. 1 is a schematic diagram of a noise monitoring circuit applied to a high-speed interface bus according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a fixed gain signal amplifying sub-circuit according to the embodiment of FIG. 1;
FIG. 3 is a schematic diagram of an amplitude extraction sub-circuit according to the embodiment of FIG. 1;
fig. 4 is a schematic diagram of a comparison and judgment sub-circuit according to the embodiment of fig. 1.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
The signal amplitude of the high-speed buses including the high-speed differential buses is smaller and smaller, so that useful signals are closer and closer to noise amplitude, which brings a plurality of difficulties for high-accuracy transmission of the signals.
When the bus stops data transmission, the interface of the bus is usually in an idle state, but the bus needs to be kept in a monitoring state all the time, and whether a useful signal is transmitted or not needs to be monitored in real time, but a certain noise signal is usually transmitted at the same time, and sometimes, excessive noise can cause misoperation.
In order to judge whether the signal transmitted from the input end of the high-speed bus is a useful signal or a noise signal, the embodiment of the invention designs the following circuit structure.
Fig. 1 is a functional block diagram of a noise monitoring circuit applied to a high-speed interface bus according to an embodiment of the present invention.
As shown in fig. 1, the noise monitoring circuit mainly includes a fixed gain signal amplifying sub-circuit (i.e., a first module), an amplitude extracting sub-circuit (i.e., a second module) and a comparing and judging sub-circuit (i.e., a third module) which are sequentially connected. The circuit also comprises a bias voltage and bias current module sub-circuit for outputting bias voltage signals and bias current signals required by the circuit of the embodiment of the invention, which is the prior art and is not repeated in the invention. Wherein:
the fixed gain signal amplifying sub-circuit is a signal amplitude monitoring circuit; the method is mainly used for effectively amplifying the signals to be input into the interface bus. Referring to fig. 1, when the differential signals VINA and VINB are simultaneously inputted, since the fixed gain signal amplifying sub-circuit is an amplifier having a fixed gain, it can effectively amplify the signal, but the amplification factor is limited to 60db at maximum.
The amplitude extraction sub-circuit is an envelope amplitude detection circuit; the signal amplitude extraction circuit is used for extracting the signal amplitude amplified by the fixed gain signal amplifying sub-circuit, namely, signal detection is carried out, and the signal amplitude is extracted.
The comparison judging sub-circuit is a comparator circuit; and the method is used for judging whether the signal is a useful signal or a noise signal according to the amplitude of the extracted signal. The specific method comprises the following steps: a signal reference threshold is preset, when the amplitude of the signal extracted through the steps is larger than the reference threshold, the signal is judged to be a useful signal, otherwise, when the amplitude of the extracted signal is lower than the reference threshold, the signal is judged to be a noise signal.
Fig. 2 is a schematic diagram of a fixed gain signal amplifying sub-circuit according to the embodiment of fig. 1.
As shown in fig. 2, the fixed gain signal amplifying sub-circuit is mainly implemented by a two-stage differential amplifier circuit.
The specific circuit structure is as follows: in the first stage differential amplifier sub-circuit, a transistor M1 and a transistor M2 and a current source Ki1 are included. The grid electrodes G of the transistor M1 and the transistor M2 are respectively connected with VinA and VinB; the drains D of the transistors M1 and M2 are respectively connected with one ends of a resistor R5 and a resistor R6 in series, the other ends of the resistor R5 and the resistor R6 are connected with a resistor R4 in parallel, and the other ends of the resistor R4 are connected with the working voltage VDDA end. The source electrode S of the transistor M1 and the source electrode S of the transistor M2 are connected in parallel and then connected to the negative electrode of the current source Ki1, and the positive electrode of the current source Ki1 is grounded GND1.
In the second stage differential amplifier sub-circuit, a transistor M3 and a transistor M4 and a current source Ki2 are included. The gates G of the transistors M4 and M3 are respectively connected with the drain D (DAT 1N end) of the transistor M1 and the drain D (DAT 1P end) of the transistor M2; the drain electrode D of the transistor M3 and the drain electrode D of the transistor M4 are respectively connected with one ends of a resistor R7 and a resistor R8, and the other ends of the resistor R7 and the resistor R8 are connected in parallel and then connected with the end of the working voltage VDDA. The sources S of the transistor M3 and the transistor M4 are connected in parallel and then connected with the negative electrode of the current source Ki2, and the positive electrode of the current source Ki2 is grounded to GND1.
The drain D of the transistor M3 and the drain D of the transistor M4 of the second stage differential amplifier sub-circuit serve as signal output terminals VFA and VFB, respectively.
In the embodiment of the present invention, the transistors M1, M2, M3 and M4 may be P-type field effect transistors.
The fixed gain signal amplifying sub-circuit formed by the first-stage differential amplifier and the second-stage differential amplifier can realize 60db gain.
Fig. 3 is a schematic diagram of an amplitude extraction sub-circuit according to the embodiment of fig. 1.
As shown in fig. 3, the amplitude extraction sub-circuit, i.e., the signal amplitude detection sub-circuit, is an envelope signal detection sub-circuit for implementing the amplitude detection function of the differential signal.
The amplitude extraction sub-circuit consists of two stages of sub-circuits. Wherein: the first stage sub-circuit mainly comprises a transistor M9, a transistor M29, a transistor M10, a resistor R9 and a capacitor C2; the second stage sub-circuit mainly comprises a transistor M12, a transistor M28, a transistor M11, a resistor R10 and a capacitor C3.
The specific circuit structure is as follows: the signal output terminals VFA and VFB of the fixed gain signal amplifying sub-circuit are electrically connected to the gate G of the transistor M12 and the gate G of the transistor M9 in the amplitude extracting sub-circuit, respectively. The drain D of the transistor M9 and the drain D of the transistor M12 are connected to the operation voltage VDDA.
The source S of the transistor M9 and the source S of the transistor M12 are connected to the drain D of the transistor M29 and the drain D of the transistor M28, respectively.
The gate G of the transistor M29 and the gate G of the transistor M28 are connected in series with a bias voltage V BIASN The source S of the transistor M29 and the source S of the transistor M28 are connected in parallel and then connected to the working ground GND1.
A signal line connecting the source S of the transistor M9 and the source S of the transistor M12 is used as an output terminal of the signal VOA extracted by the amplitude detection. A transistor M10 and a resistor R9 are connected between the drain D of the transistor M9 and the signal line VOA in a bridging manner, and a capacitor C2 is connected between the source S of the transistor M29 and the signal line VOA in parallel. Similarly, a transistor M11 and a resistor R10 are connected across the drain D of the transistor M12 and the signal line VOA, and a capacitor C3 is connected in parallel between the source S of the transistor M28 and the signal line VOA.
The gate G of the transistor M10 and the gate G of the transistor M11 are connected in series, and are connected to a bias current BIASP.
By using the amplitude extraction sub-circuit, the intensity of the signal can be effectively extracted through the signal line VOA.
Fig. 4 is a schematic diagram of a comparison and judgment sub-circuit according to the embodiment of fig. 1.
As shown in fig. 4, the comparison judging sub-circuit mainly includes a transistor M18, a transistor M19, a transistor M16, a transistor M17, and a transistor M20.
The specific circuit structure is as follows: the signal line VOA is connected to the gate G of the transistor M16, the drain D of the transistor M16 is connected to the drain D of the transistor M18, the gate G of the transistor M18 is connected to the gate G of the transistor M19, and the source S of the transistor M18 is connected to the drain D of the transistor M19.
The drain D of the transistor M16 is connected with the gate G of the transistor M18; the source S of the transistor M16 and the source S of the transistor M17 are connected in parallel and then connected to the drain D of the transistor M20, the gate G of the transistor M20 is connected to the voltage Vc, and the source S of the transistor M20 is connected to the ground GND1.
The gate G of the transistor M17 is connected to the reference voltage Vref, and the source S of the transistor M19 is connected to the drain D of the transistor M17 as an output signal line Vout for comparing and judging signals.
In this way, by comparing the signal amplitude of the output signal VOA of the amplitude extraction sub-circuit with the reference voltage threshold Vref, it is possible to determine whether the input signal is a useful signal or a noise signal from the output result of the output signal Vout.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention.

Claims (2)

1. The noise monitoring circuit is characterized by comprising a fixed gain signal amplifying sub-circuit, an amplitude extracting sub-circuit and a comparison judging sub-circuit; the amplitude extraction sub-circuit is an envelope signal detection sub-circuit and is used for realizing the amplitude detection function of the differential signal, wherein:
the fixed gain signal amplifying sub-circuit is used for effectively amplifying signals to be input into the interface bus;
the amplitude extraction sub-circuit is used for carrying out envelope extraction on the signal amplified by the fixed gain signal amplification sub-circuit to obtain the amplitude of the signal;
the comparison judging sub-circuit is used for judging the amplitude of the extracted signal according to a reference voltage threshold value and judging whether the signal is a useful signal or a noise signal;
the fixed gain signal amplifying sub-circuit comprises a two-stage differential amplifier circuit, and specifically comprises:
in the first-stage differential amplifier sub-circuit, the first-stage differential amplifier sub-circuit comprises a transistor M1, a transistor M2 and a current source Ki1, wherein the grid electrodes G of the transistor M1 and the transistor M2 are respectively connected with VinA and VinB; the drain electrode D of the transistor M1 and the drain electrode D of the transistor M2 are respectively connected with one end of a resistor R5 and one end of a resistor R6 in series, the other ends of the resistor R5 and the resistor R6 are connected with a resistor R4 in parallel, and the other end of the resistor R4 is connected with the end of the working voltage VDDA; the source S of the transistor M1 and the source S of the transistor M2 are connected in parallel and then connected with the negative electrode of the current source Ki1, and the positive electrode of the current source Ki1 is connected with the working ground GND1;
in the second-stage differential amplifier sub-circuit, the gate G of the transistor M4 and the gate G of the transistor M3 are connected to the drain D of the transistor M1 and the drain D of the transistor M2, respectively; the drain electrode D of the transistor M3 and the drain electrode D of the transistor M4 are respectively connected with one ends of a resistor R7 and a resistor R8, and the other ends of the resistor R7 and the resistor R8 are connected in parallel and then are connected with the end of the working voltage VDDA; the source S of the transistor M3 and the source S of the transistor M4 are connected in parallel and then connected with the cathode of the current source Ki2, and the anode of the current source Ki2 is connected with the working ground GND1;
the drain electrode D of the transistor M3 and the drain electrode D of the transistor M4 of the second-stage differential amplifier sub-circuit are respectively used as signal output ends VFA and VFB;
the amplitude extraction sub-circuit has the following specific circuit structure:
the grid G of the transistor M12 and the grid G of the transistor M9 are respectively and electrically connected with the signal output ends VFA and VFB of the fixed gain signal amplifying sub-circuit; the drain electrode D of the transistor M9 and the drain electrode D of the transistor M12 are connected with the working voltage VDDA; the source S of the transistor M9 and the source S of the transistor M12 are connected to the drain D of the transistor M29 and the drain D of the transistor M28, respectively; the gate G of the transistor M29 and the gate G of the transistor M28 are connected in series, and the source S of the transistor M29 and the source S of the transistor M28 are connected in parallel and then connected to the working ground GND1;
a signal line connecting the source electrode S of the transistor M9 and the source electrode S of the transistor M12 is used as an output end of the signal VOA extracted by the amplitude detection; a transistor M10 and a resistor R9 are connected between the drain electrode D of the transistor M9 and the signal line VOA in a bridging manner, and a capacitor C2 is connected between the source electrode S of the transistor M29 and the signal line VOA in a parallel manner; a transistor M11 and a resistor R10 are connected between the drain D of the transistor M12 and the signal line VOA in a bridging manner, and a capacitor C3 is connected between the source S of the transistor M28 and the signal line VOA in a parallel manner; the gate G of the transistor M10 and the gate G of the transistor M11 are connected in series, and are connected with a bias current BIASP.
2. The noise monitoring circuit according to claim 1, wherein the comparing and judging sub-circuit comprises a transistor M18, a transistor M19, a transistor M16, a transistor M17 and a transistor M20, and the specific circuit structure is as follows:
the signal line VOA is connected to a gate G of the transistor M16, a drain D of the transistor M16 is connected to a drain D of the transistor M18, the gate G of the transistor M18 is connected to a gate G of the transistor M19, and a source S of the transistor M18 is connected to a drain D of the transistor M19;
the drain D of the transistor M16 is connected with the gate G of the transistor M18; the source S of the transistor M16 and the source S of the transistor M17 are connected in parallel and then connected to the drain D of the transistor M20, the gate G of the transistor M20 is connected to the voltage Vc, and the source S of the transistor M20 is connected to the working ground GND1;
the gate G of the transistor M17 is connected to the reference voltage Vref, and the source S of the transistor M19 is connected to the drain D of the transistor M17 as an output signal line Vout for comparing and judging signals.
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Publication number Priority date Publication date Assignee Title
CN109194667B (en) * 2018-09-18 2022-03-11 上海创远仪器技术股份有限公司 Device for realizing IQ data signal data compression and transmission function based on frequency domain detection
CN111628731B (en) * 2020-06-05 2023-10-24 上海兆芯集成电路股份有限公司 Noise detection circuit

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CN208255874U (en) * 2018-02-08 2018-12-18 高科创芯(北京)科技有限公司 A kind of noise monitoring circuit applied to high-speed interface bus

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Publication number Priority date Publication date Assignee Title
CN1921297A (en) * 2005-08-25 2007-02-28 上海大缔微电子有限公司 Integrated multipath gain comparing control amplifying circuit
JP2011239154A (en) * 2010-05-10 2011-11-24 Renesas Electronics Corp Operational amplifier circuit
CN101834567A (en) * 2010-06-03 2010-09-15 中国人民解放军国防科学技术大学 Broadband gain adjustable low-noise amplifier
CN102571227A (en) * 2011-11-10 2012-07-11 嘉兴联星微电子有限公司 Amplitude detection circuit with direct current offset elimination function
CN103578477A (en) * 2012-07-30 2014-02-12 中兴通讯股份有限公司 Denoising method and device based on noise estimation
CN103746660A (en) * 2013-12-23 2014-04-23 中国电子科技集团公司第三十八研究所 Broadband CMOS (Complementary Metal-Oxide-Semiconductor Transistor) balun low noise amplifier
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