CN2591779Y - Non-pin semiconductor assembly - Google Patents
Non-pin semiconductor assembly Download PDFInfo
- Publication number
- CN2591779Y CN2591779Y CN 02292733 CN02292733U CN2591779Y CN 2591779 Y CN2591779 Y CN 2591779Y CN 02292733 CN02292733 CN 02292733 CN 02292733 U CN02292733 U CN 02292733U CN 2591779 Y CN2591779 Y CN 2591779Y
- Authority
- CN
- China
- Prior art keywords
- pin
- lead frame
- chip
- conductor component
- colloid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to a non-pin semiconductor assembly, which comprises a metal wire guiding frame, a chip and a colloid, wherein, the metal wire guiding frame is provided with a plurality of flat pins, isolating gaps are arranged between adjacent pins and between opposite pins, and the bottom face of the inner side end of each pin forms a concave part; the chip is fixed on the inner side end of the central pin of the wire guiding frame, I/O contacts are arranged downwards, and each I/O contact of the chip is electrically connected with the corresponding pins of the wire guiding frame by a metal wire; the colloid is formed and fixed on the wire guiding frame, is covered on the outer side of the chip and is filled in the isolating gaps among the pins of the wire guiding frame and the concave parts, the metal wires connected among the chip and the pin of the wire guiding frame are sealed in the colloid, and the bottom face of the outer side end of each pin of the wire guiding frame is exposed outside the colloid. The utility model has the advantages of mould cost saving, simple production, light weight, small size, etc., and can reduce the thickness of products.
Description
[technical field]
The utility model is about a kind of pin-free semi-conductor component.
[background technology]
The pin-free semi-conductor component encapsulating structure of commonly seeing now, as shown in Figure 3, it has a conductive metal frames (40) that comprises most pins (41), each pin (41) medial extremity forms Gao Qizhuan up, again chip (50) is risen in the portion with sticking pin (41) the medial extremity height of being located at lead frame (40) central authorities of I/O contact kenel mat two-sided tape (52) down, be connected in each I/O contact of chip (50) pin (41) medial extremity bottom surface place corresponding with gold thread (51) in addition with lead frame (40), cooperate mould sealing colloid (60) postforming again in the outside, and constitute the pin-free semi-conductor component that a pin (41) outboard end exposes.
Again, before take off pin-free semi-conductor component because of its chip system fully by sealing in colloid, the high temperature that is produced during chip operation has not vaporific problem, so there is the people to make as shown in Figure 4 two-conductor line shelf structure in addition, it mainly has metal first lead frame (70) that comprises most pins (71), its pin (71) medial extremity forms Gao Qizhuan up, multiple chip (80) is glued with I/O contact kenel mat two-sided tape (82) down is located on first lead frame (70) center pin (71) medial extremity, be connected in each I/O contact of chip (80) pin (71) medial extremity bottom surface place corresponding with gold thread (81) in addition with first lead frame (70), go up with adhere second lead frame (100) of a tool chip pad (101) of elargol or two-sided tape in chip (80), cooperate mould sealing colloid (90) postforming again in the outside, and constitute the pin-free semi-conductor component that a chip pad (101) and pin (71) outboard end expose.
Though before take off two and commonly use pin-free semi-conductor component and be flat with its pin exposed junction, use the integral thickness that reduces the assembly finished product, and can direct smooth weldering be located on the circuit board, and semiconductor subassembly shown in Figure 4 more designs by exposing to the outer metal pad of colloid on the chip, and the high temperature that produces when making the chip operation in the assembly can directly dispel the heat via metal pad.
But, though precedingly take off the semiconductor subassembly that the more existing bending pins of the structure of commonly using two pin-free semi-conductor components protrudes out and have compact characteristics, yet, remain in its structure in following shortcoming:
1, the die cost height of lead frame: this is commonly used two pin-free semi-conductor components and provides the accommodation space that is connected in the metal wire between chip and pin for making, need to make lead frame pin medial extremity form a high portion of rising in the punching out mode, and need to increase the expenditure and the processing cost of die cost in conjunction with mould.
2, the assembly finished product is thick partially: same as above, this is commonly used two pin-free semi-conductor components and binds mould and make lead frame pin medial extremity form a high portion of rising in the punching out mode, provide the accommodation space that connects metal wire between chip and pin, so make the thickness of this two semiconductor subassemblies integral body higher.
[utility model content]
In view of this, for taking off the encapsulating structure shortcoming of commonly using pin-free semi-conductor component before improving, the purpose of this utility model promptly is to provide a kind of and saves die cost, make easy and can reduce product thickness, and has the pin-free semi-conductor component of advantage such as compact.
Take off purpose for before reaching, a kind of pin-free semi-conductor component that the utility model proposed is characterized in that: it comprises:
One conductive metal frames, it has the pin of most flat, has external series gap between pin between its adjacent leads and relatively, and each pin medial extremity bottom surface forms recess;
One chip is to be fixedly arranged on the pin medial extremity of lead frame central authorities and to make the I/O contact down, constitutes with metal wire between each I/O contact of this chip pin corresponding with lead frame to electrically connect; And
Colloid, be that moulding is fixedly arranged on and covers on the lead frame in the chip outside, and filling is in this lead frame in the external series gap and recess between pin, will be connected in metal wire between chip and lead frame pin is sealed in, outside each pin outboard end bottom surface of lead frame is revealed in.
Pin-free semi-conductor component of the present utility model can also have following additional technical characterictic:
The pin of this lead frame can be distributed in both sides and be corresponding shape.
The pin of this lead frame also can be distributed in four limits and be two corresponding shapes.
The height of being located at the recess of lead frame pin bottom surface is no more than 1/2nd of lead frame thickness.
In this colloid can be coated on chip fully.
This colloid also can be coated on chip periphery and bottom surface, and allows outside chip upper surface is revealed in.
This colloid outer rim is concordant with lead frame pin external end edge.
This lead frame pin external end edge convexedly stretches in the colloid outer rim.
The alloy of establishing one deck silver or nickel-palladium-Jin can plate in the recess place of this lead frame.
After above stated specification, and compare with commonly using two pin-free semi-conductor components, when learning that characteristics of the present utility model comprise at least:
1, can save the die cost of making lead frame: lead frame of the present utility model can utilize etching mode directly to make moulding, need not after etching or punching out become the embryo lead frame, the mat mould stamps out the complicated procedures of height portion in the pin medial extremity again, and can save the die cost of making lead frame.
2, can reduce product thickness, reach compact purpose: the utility model semiconductor subassembly system utilizes the straight pin medial extremity of lead frame to etch partially the recess of formation, the accommodation space that connects metal wire between chip and pin directly is provided, and need not to utilize lead frame pin medial extremity to be bent into the high accommodation space that shape provides that rises, so can reduce the thickness of assembly, and present the most compact type body.
3, tool high-cooling property: the utility model semiconductor subassembly accounts for the exposed area of assembly bottom surface major part because of its straight metallic pin, and chip directly is fixedly arranged on the pin, the chip back of assembly can be exposed kenel again, so the heat that is produced during chip operation can directly conduct to the external world via pin or chip back, thereby possesses splendid radiating effect.
4, can reduce the signal propagation delay phenomenon: the electric connection system of the utility model semiconductor subassembly is directly derived by the straight pin of lead frame, its signaling path is shorter compared to commonly using in the semiconductor subassembly meander-like pin, so can reduce the signal propagation delay phenomenon.
For further understanding architectural feature of the present utility model and other purpose, attached now with graphic detailed description as the back:
[description of drawings]
Fig. 1 is the planar structure schematic diagram of the utility model one embodiment.
Fig. 2 is the planar structure schematic diagram of another embodiment of the utility model.
Fig. 3 is a floor map of commonly using first kind of pin-free semi-conductor component.
Fig. 4 is a floor map of commonly using second kind of pin-free semi-conductor component.
[embodiment]
The specific embodiment of relevant the utility model pin-free semi-conductor component, as shown in Figure 1, 2, it comprises:
One conductive metal frames (10), it has the pin (11) of most flat, the pin (11) of this lead frame (10) can be distributed in the limit, two opposite sides and locate or be distributed in kenels such as place, surrounding, has external series gap (12) between pin (11) between its adjacent leads (11) and relatively, each pin (11) medial extremity bottom surface utilizes the mode of etching partially to form recess (13) again, and this recess (13) height is the best to be no more than one of lead frame (10) thickness two minutes;
One chip (20), system is fixedly arranged on the relative pin of lead frame (10) centre (11) medial extremity with I/O contact kenel mat two-sided tape (22) down, chip (20) I/O contact is connected in formation electric connection between each I/O contact of chip (20) pin (11) corresponding with lead frame (10) with metal wire (21) in addition over against the external series gap (12) between the relative pin (11) of lead frame (10); And
Colloid (30), system's cooperation mould molding is fixedly arranged on lead frame (10) and goes up and be coated on chip (20) outside, and filling is in lead frame (10) in the external series gap (12) and recess (13) between pin (11), so that will be connected in metal wire (21) between chip (20) and lead frame (10) pin is sealed in, and allow outside each pin of lead frame (10) (11) outboard end bottom surface is revealed in, and constitute a pin-free semi-conductor component encapsulating structure.
Aforementioned colloid (30) can allow outside chip (20) upper surface is revealed in as shown in Figure 1, is beneficial to heat radiation, or as shown in Figure 2, in chip (20) can being coated on fully; Colloid (30) outer rim can be concordant with lead frame (10) pin (11) external end edge again, or lead frame (10) pin (11) outer end slightly convexedly stretches in colloid (30) outer rim; The recess (13) of lead frame (10) locates to plate the alloy of establishing one deck silver or nickel-palladium-Jin again, is connected in the last usefulness of pin (11) for metal wire (21).
This semiconductor subassembly can be assemblied on the circuit board in conjunction with other electronic building brick, and the pin of its flat of mat can direct smooth weldering be located to constitute on the circuit on the circuit board and electrically connects, and so that its specific service behaviour to be provided, and can present its compact kenel; But expose this semiconductor subassembly mat lead frame pin end in addition, and can directly do the detection of functional or open circuit/short circuit via the pin exposed junction.
Claims (10)
1, a kind of pin-free semi-conductor component, it is characterized in that: it comprises:
One conductive metal frames, it has the pin of most flat, has external series gap between pin between its adjacent leads and relatively, and each pin medial extremity bottom surface forms recess;
One chip is to be fixedly arranged on the pin medial extremity of lead frame central authorities and to make the I/O contact down, constitutes with metal wire between each I/O contact of this chip pin corresponding with lead frame to electrically connect; And
Colloid, be that moulding is fixedly arranged on and covers on the lead frame in the chip outside, and filling is in this lead frame in the external series gap and recess between pin, will be connected in metal wire between chip and lead frame pin is sealed in, outside each pin outboard end bottom surface of lead frame is revealed in.
2, pin-free semi-conductor component as claimed in claim 1 is characterized in that: the pin of this lead frame is corresponding shape for being distributed in both sides.
3, pin-free semi-conductor component as claimed in claim 1 is characterized in that: the pin of this lead frame is two corresponding shapes for being distributed in four limits.
4, pin-free semi-conductor component as claimed in claim 1 is characterized in that: the height of being located at the recess of lead frame pin bottom surface is no more than 1/2nd of lead frame thickness.
5, pin-free semi-conductor component as claimed in claim 1 is characterized in that: in this colloid is coated on chip fully.
6, pin-free semi-conductor component as claimed in claim 1 is characterized in that: this colloid is coated on chip periphery and bottom surface, and allows outside chip upper surface is revealed in.
7, pin-free semi-conductor component as claimed in claim 1 is characterized in that: this colloid outer rim is concordant with lead frame pin external end edge.
8, pin-free semi-conductor component as claimed in claim 1 is characterized in that: this lead frame pin external end edge convexedly stretches in the colloid outer rim.
9, pin-free semi-conductor component as claimed in claim 1 is characterized in that: one deck silver is established in the recess place plating of this lead frame.
10, pin-free semi-conductor component as claimed in claim 1 is characterized in that: the alloy of one deck nickel-palladium-Jin is established in the recess place plating of this lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02292733 CN2591779Y (en) | 2002-12-20 | 2002-12-20 | Non-pin semiconductor assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02292733 CN2591779Y (en) | 2002-12-20 | 2002-12-20 | Non-pin semiconductor assembly |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2591779Y true CN2591779Y (en) | 2003-12-10 |
Family
ID=33750949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02292733 Expired - Lifetime CN2591779Y (en) | 2002-12-20 | 2002-12-20 | Non-pin semiconductor assembly |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2591779Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316611C (en) * | 2004-03-19 | 2007-05-16 | 矽品精密工业股份有限公司 | Wafer-level semiconductor package having lamination structure and making method thereof |
| TWI475658B (en) * | 2013-01-18 | 2015-03-01 | I Chiun Precision Ind Co Ltd | LED leadframe and manufacturing method thereof |
-
2002
- 2002-12-20 CN CN 02292733 patent/CN2591779Y/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316611C (en) * | 2004-03-19 | 2007-05-16 | 矽品精密工业股份有限公司 | Wafer-level semiconductor package having lamination structure and making method thereof |
| TWI475658B (en) * | 2013-01-18 | 2015-03-01 | I Chiun Precision Ind Co Ltd | LED leadframe and manufacturing method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Guangzhou Hailin Electronic Technology Co., Ltd. Assignor: UPI Semiconductor Corp Contract fulfillment period: 2009.8.10 to 2012.8.9 Contract record no.: 2009990001055 Denomination of utility model: Non-pin semiconductor assembly Granted publication date: 20031210 License type: Exclusive license Record date: 20090924 |
|
| LIC | Patent licence contract for exploitation submitted for record |
Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2009.8.10 TO 2012.8.9; CHANGE OF CONTRACT Name of requester: GUANGZHOU CITY HAILIN ELECTRONIC TECHNOLOGY DEVELO Effective date: 20090924 |
|
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20121220 Granted publication date: 20031210 |