CN221304696U - Silicon carbide MOSFET capable of increasing voltage endurance capacity - Google Patents
Silicon carbide MOSFET capable of increasing voltage endurance capacity Download PDFInfo
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- CN221304696U CN221304696U CN202222209954.6U CN202222209954U CN221304696U CN 221304696 U CN221304696 U CN 221304696U CN 202222209954 U CN202222209954 U CN 202222209954U CN 221304696 U CN221304696 U CN 221304696U
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 36
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 39
- 238000002955 isolation Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 description 19
- 238000005530 etching Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Abstract
The utility model provides a silicon carbide MOSFET capable of increasing pressure endurance capacity, comprising: the isolation region is arranged on the upper side surface of the silicon carbide substrate, and is provided with a first bulge and a second bulge; the source electrode source region is arranged on the upper side surface of the isolation region, and the left side surface of the source electrode source region is connected to the right side surface of the first protruding part; the drain electrode source region is arranged on the upper side surface of the isolation region, and the right side surface of the drain electrode source region is connected to the left side surface of the second bulge part; the conducting channel region is arranged on the upper side surface of the isolation region, and the left side and the right side of the conducting channel region are respectively connected with the right side surface of the second protruding part and the left side surface of the first protruding part; the insulating layer is arranged on the upper side surface of the first protruding part; the drain metal layer is connected to the drain source region; the grid metal layer is connected to the upper side surface of the insulating layer; and the source metal layer is connected to the source electrode region, so that the voltage resistance of the SiC LDMOSFET can be improved in a smaller area.
Description
Technical Field
The utility model relates to a silicon carbide MOSFET capable of increasing pressure endurance capacity.
Background
SiC device silicon carbide (SiC) materials are widely focused and studied due to their superior physical properties. The high-temperature high-power electronic device has the advantages of high input impedance, high switching speed, high working frequency, high temperature and high pressure resistance and the like, and is widely applied to the aspects of switching regulated power supplies, high-frequency heating, automobile electronics, power amplifiers and the like.
In a silicon carbide LD MOSFET, the withstand voltage capability and area of the device are positively correlated, the longer the lateral conduction channel, the stronger the withstand voltage capability, but the improvement in withstand voltage capability comes at the expense of the device area, which increases the area of the device, ultimately affecting the number of devices per unit area.
Disclosure of utility model
The utility model aims to solve the technical problem of providing a silicon carbide MOSFET capable of increasing the voltage endurance capability, which can realize the improvement of the voltage endurance capability of the SiC LDMOSFET on a smaller area.
The utility model is realized in the following way: a silicon carbide MOSFET that increases voltage withstand capability, comprising:
a silicon carbide substrate;
the isolation region is arranged on the upper side surface of the silicon carbide substrate, and a first protruding part and a second protruding part are arranged on the isolation region;
the source electrode source region is arranged on the upper side surface of the isolation region, and the left side surface of the source electrode source region is connected to the right side surface of the first protruding part;
The drain electrode source region is arranged on the upper side surface of the isolation region, and the right side surface of the drain electrode source region is connected to the left side surface of the second protruding part;
The conducting channel region is arranged on the upper side surface of the isolation region, the left side and the right side of the conducting channel region are respectively connected with the right side surface of the second protruding part and the left side surface of the first protruding part, the conducting channel region comprises a first conducting channel, a second conducting channel, a third conducting channel and a fourth conducting channel, and the doping concentration of the first conducting channel is less than that of the second conducting channel, and the doping concentration of the third conducting channel is less than that of the fourth conducting channel;
the insulating layer is arranged on the upper side surface of the first protruding part;
A drain metal layer connected to the drain source region;
a gate metal layer connected to an upper side of the insulating layer;
And a source metal layer connected to the source region.
Further, the conductive channel region includes at least two conductive channels, and the doping concentration of the conductive channel on the left side is smaller than the doping concentration of the conductive channel on the right side.
Further, the drain source region and the source region are both n+ type.
Further, an insulating layer is arranged among the drain electrode metal layer, the gate electrode metal layer and the source electrode metal layer.
Further, the conductive channel region and the isolation region are both P-type.
The utility model has the advantages that:
A lateral concentration gradient is constructed in the conduction channel of the LD MOSFET, and the concentration gradient gradually increases the doping concentration from the drain to the source; the number of concentration gradients can be redesigned according to different voltage withstand classes, and the voltage withstand capability of the silicon carbide LD MOSFET can be improved on a smaller area.
Drawings
The utility model will be further described with reference to examples of embodiments with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a silicon carbide MOSFET with increased voltage endurance according to the present utility model.
Fig. 2 is a flow chart of a method of fabricating a silicon carbide MOSFET with increased voltage endurance according to the present utility model.
Fig. 3 is a flow chart diagram of a second method for fabricating a silicon carbide MOSFET with increased voltage endurance capability according to the present utility model.
Fig. 4 is a flowchart of a method for fabricating a silicon carbide MOSFET with increased voltage endurance according to the present utility model.
Fig. 5 is a flow chart of a method for fabricating a silicon carbide MOSFET with increased voltage endurance according to the present utility model.
Fig. 6 is a flowchart of a method for fabricating a silicon carbide MOSFET with increased voltage endurance according to the present utility model.
Fig. 7 is a flowchart of a method for fabricating a silicon carbide MOSFET with increased voltage endurance according to the present utility model.
Fig. 8 is a flow chart of a method of fabricating a silicon carbide MOSFET with increased voltage endurance according to the present utility model.
Fig. 9 is a flowchart eight of a method for fabricating a silicon carbide MOSFET with increased voltage endurance capability according to the present utility model.
Detailed Description
As shown in fig. 1, a silicon carbide MOSFET of the present utility model for increasing withstand voltage includes:
A silicon carbide substrate 1;
the isolation region 2 is arranged on the upper side surface of the silicon carbide substrate 1, a first protruding portion 21 and a second protruding portion 22 are arranged on the isolation region 2, and the isolation region 2 is of a P type;
The source electrode source region 3 is arranged on the upper side surface of the isolation region 2, the left side surface of the source electrode source region 3 is connected to the right side surface of the first protruding portion 21, and the source electrode source regions 3 are all n+;
The drain-source region 4 is arranged on the upper side surface of the isolation region 2, the right side surface of the drain-source region 4 is connected to the left side surface of the second protruding portion 22, and the drain-source region 4 is of an n+ type;
A conductive channel region 5, where the conductive channel region 5 is disposed on the upper side of the isolation region 2, and the left and right sides of the conductive channel region 5 are respectively connected to the right side surface of the second protruding portion 22 and the left side surface of the first protruding portion 21, the conductive channel region 5 includes at least two conductive channels (as shown in fig. 1, the conductive channel region 5 includes a first conductive channel 51, a second conductive channel 52, a third conductive channel 53 and a fourth conductive channel 54, the doping concentration of the first conductive channel 51 < the doping concentration of the second conductive channel 52 < the doping concentration of the third conductive channel 53 < the doping concentration of the fourth conductive channel 54, the doping concentration from the drain metal layer to the source metal layer increases gradually, and the doping concentration of the conductive channel on the left side is less than the doping concentration of the conductive channel on the right side, and the conductive channel region 5 is P-type;
an insulating layer 6, wherein the insulating layer 6 is arranged on the upper side surface of the first protruding part 21;
A drain metal layer 7, the drain metal layer 7 being connected to the drain source region 4;
A gate metal layer 8, the gate metal layer 8 being connected to an upper side of the insulating layer 6;
And a source metal layer 9, the source metal layer 9 being connected to the source region 3.
An insulating layer 6 is arranged among the drain metal layer 7, the gate metal layer 8 and the source metal layer 9.
The MOSFET comprises at least two conductive channels, so that the doping concentration of the region between the drain metal layer 7 and the source metal layer 9 is gradually increased, and the voltage endurance is improved; the lowest doping concentration of the conducting channel near the drain electrode is that the LD MOSFET is a power device, the drain electrode metal layer 7 of the LD MOSFET is connected with a high-voltage end, and the low doping concentration can lead the withstand voltage to be mainly distributed near the drain electrode region; the doping concentration of the conducting channel close to the source electrode metal layer 9 is higher, and the voltage born in the region is less, so that the high withstand voltage has small influence on the potential near the source electrode metal layer 9, the control capability of the gate electrode metal layer 8 on the source electrode metal layer 9 is stronger, and the switching characteristic of the device is guaranteed; the device voltage resistance can be improved in the same transverse area, and the device voltage resistance is beneficial to improving the power density of the LD MOSFET device and improving the integration level of a circuit.
As shown in fig. 1 to 9, the method for manufacturing the MOSFET specifically includes the following steps:
Step 1, a barrier layer a is grown on an isolation region 2 of a silicon carbide substrate 1, a through hole is formed by etching the barrier layer a, and ion implantation is carried out on the isolation region 2 through the through hole to form a conductive channel region 5; repeating the steps until all the conducting channels are completed, wherein the conducting channel region 5 comprises at least two conducting channels, the doping concentration of the left conducting channel is smaller than that of the right conducting channel, and the conducting channel region and the isolation region are both of P type; for example, four conductive channels are formed: growing a barrier layer a on an isolation region 2 of a silicon carbide substrate 1, etching the barrier layer a to form a through hole, and performing ion implantation on the isolation region 2 through the through hole to form a first conductive channel 51; growing a barrier layer a on the isolation region 2 of the silicon carbide substrate 1, etching the barrier layer a to form a through hole, and performing ion implantation on the first conductive channel 51 through the through hole to form a second conductive channel 52; growing a barrier layer a on the isolation region 2 of the silicon carbide substrate 1, etching the barrier layer a to form a through hole, and performing ion implantation on the second conductive channel 52 through the through hole to form a third conductive channel 53; growing a barrier layer a on the isolation region 2 of the silicon carbide substrate 1, etching the barrier layer a to form a through hole, and performing ion implantation on the third conductive channel 53 through the through hole to form a fourth conductive channel 54;
Step 2, regrowing a barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation on the isolation region 2 through the through hole to form a drain source region 4 and a source region 3, wherein the drain source region 4 and the source region 3 are both of an N+ type;
Step 3, respectively depositing a drain metal layer 7 and a source metal layer 8 on the drain source region 4 and the source region 3;
step 4, regrowing the barrier layer a, etching the barrier layer a to form a through hole, and oxidizing to form an insulating layer 6;
Step 5, regrowing the barrier layer a, etching the barrier layer a to form a through hole, and etching to form a gate metal deposition area b;
And 6, regrowing a barrier layer a, etching the barrier layer a to form a through hole, depositing in a gate metal deposition area b to form a gate metal layer 8, and removing all the barrier layer a, wherein an insulating layer 6 is arranged among the drain metal layer 7, the gate metal layer 8 and the source metal layer 9.
While specific embodiments of the utility model have been described above, it will be appreciated by those skilled in the art that the specific embodiments described are illustrative only and not intended to limit the scope of the utility model, and that equivalent modifications and variations of the utility model in light of the spirit of the utility model will be covered by the claims of the present utility model.
Claims (2)
1. A silicon carbide MOSFET for increasing voltage endurance comprising:
a silicon carbide substrate;
the isolation region is arranged on the upper side surface of the silicon carbide substrate, and a first protruding part and a second protruding part are arranged on the isolation region;
the source electrode source region is arranged on the upper side surface of the isolation region, and the left side surface of the source electrode source region is connected to the right side surface of the first protruding part;
The drain electrode source region is arranged on the upper side surface of the isolation region, and the right side surface of the drain electrode source region is connected to the left side surface of the second protruding part;
The conducting channel region is arranged on the upper side surface of the isolation region, the left side and the right side of the conducting channel region are respectively connected with the right side surface of the second protruding part and the left side surface of the first protruding part, the conducting channel region comprises a first conducting channel, a second conducting channel, a third conducting channel and a fourth conducting channel, and the doping concentration of the first conducting channel is less than that of the second conducting channel, and the doping concentration of the third conducting channel is less than that of the fourth conducting channel;
the insulating layer is arranged on the upper side surface of the first protruding part;
A drain metal layer connected to the drain source region;
a gate metal layer connected to an upper side of the insulating layer;
and a source metal layer connected to the source region;
The drain source region and the source region are both of an N+ type, and the conducting channel region and the isolation region are both of a P type.
2. The silicon carbide MOSFET of claim 1 wherein an insulating layer is disposed between the drain metal layer, the gate metal layer, and the source metal layer.
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN221304696U true CN221304696U (en) | 2024-07-09 |
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