CN220774362U

CN220774362U - Integrated circuit substrate

Info

Publication number: CN220774362U
Application number: CN202322489720.6U
Authority: CN
Inventors: 王耀飞
Original assignee: Nanjing Qijian Semiconductor Technology Co ltd; Shanghai Hejian Industrial Software Group Co Ltd
Current assignee: Nanjing Qijian Semiconductor Technology Co ltd; Shanghai Hejian Industrial Software Group Co Ltd
Priority date: 2023-09-13
Filing date: 2023-09-13
Publication date: 2024-04-12
Anticipated expiration: 2033-09-13

Abstract

The utility model discloses an integrated circuit substrate, which comprises a chip substrate, wherein the surface of the chip substrate is provided with a plurality of groups of high-speed signal bonding pads and reference ground bonding pads, each high-speed signal bonding pad is respectively provided with a high-speed signal via hole, the chip substrate is provided with a plurality of groups of reference ground via holes, each group of reference ground via holes are respectively arranged in a staggered manner with the corresponding reference ground bonding pad, the surface of the chip substrate is provided with a reference ground copper sheet, and the reference ground copper sheet is used for intersecting and staggering the reference ground bonding pads and the reference ground via holes to form a whole. The reference ground via holes are formed in the chip substrate and are arranged in a staggered mode with the reference ground bonding pads, so that the number of the reference ground via holes is effectively increased, the risk of crosstalk between high-speed signals is reduced, and the use stability of the integrated circuit board is improved.

Description

Integrated circuit substrate

Technical Field

The present disclosure relates to integrated circuit substrates, and particularly to an integrated circuit substrate.

Background

The integrated circuit board is also called an integrated circuit board, is a carrier for carrying integrated circuits, and is widely used in various electronic components and electrical parts.

An integrated circuit board in the related art generally includes a chip substrate, on which a high-speed signal pad and a reference ground pad are disposed, the high-speed signal pad is provided with a high-speed signal via hole, and the reference ground pad is provided with a reference ground via hole. The high-speed signal on the chip passes through the high-speed signal pad and the high-speed signal via hole through the solder ball and then is connected to the inner layer wiring of the chip substrate, and the reference ground signal on the chip passes through the reference ground pad and the reference ground via hole through the solder ball and then is connected to the inner layer wiring of the chip substrate, so that communication is completed.

However, the reference ground is directly punched on the corresponding reference ground pad, the number of the reference ground pads is limited, the number of the reference ground vias is also limited, and in the use process of the integrated circuit substrate, the crosstalk between high-speed signals is serious, so that the use stability of the integrated circuit substrate is affected, and the use stability of the integrated circuit substrate needs to be improved.

Disclosure of Invention

Aiming at the defects existing in the prior art, the utility model aims to provide an integrated circuit substrate which has the effect of reducing the risk of crosstalk between high-speed signals, thereby improving the use stability of the integrated circuit substrate.

The technical aim of the utility model is realized by the following technical scheme: the integrated circuit substrate comprises a chip substrate, wherein a plurality of groups of high-speed signal bonding pads and reference ground bonding pads are arranged on the surface of the chip substrate, each high-speed signal bonding pad is provided with a plurality of groups of reference ground bonding holes, each group of reference ground bonding holes are arranged in a staggered manner with the corresponding reference ground bonding pad, a reference ground copper sheet is arranged on the surface of the chip substrate, and the reference ground copper sheet connects the reference ground bonding pads with the reference ground bonding holes in a staggered manner to form a whole.

The present utility model may be further configured in a preferred example to: each group of high-speed signal pads is at least provided with two rows, each row of high-speed signal pads are arranged at equal intervals, and two adjacent rows of high-speed signal pads are arranged in a staggered manner.

The present utility model may be further configured in a preferred example to: and a plurality of groups of the reference ground pads and a plurality of groups of the high-speed signal pads are arranged at intervals.

The present utility model may be further configured in a preferred example to: each group of the reference ground pads are arranged in a row at equal intervals, and each group of the reference ground vias surrounds the corresponding reference ground pad at the periphery and is close to the corresponding reference ground via.

The present utility model may be further configured in a preferred example to: and an elastic protection ring is arranged at the edge position of the bottom surface of the chip substrate.

The present utility model may be further configured in a preferred example to: the edge position of the bottom surface of the chip substrate is provided with a limit groove, the limit ring is connected with the guard ring in an integrated manner, and the limit ring is fixed in the limit groove.

The present utility model may be further configured in a preferred example to: the cross section of the limiting ring is T-shaped, and the circumferential inner wall of the limiting groove is matched with the circumferential side wall of the limiting ring, so that the limiting ring can be clamped and limited with the limiting groove.

The present utility model may be further configured in a preferred example to: and the protection ring is provided with a heat dissipation hole.

The present utility model may be further configured in a preferred example to: the heat dissipation holes are arranged in a plurality, and the heat dissipation holes are arranged at equal intervals along the circumferential direction of the protection ring.

In summary, the utility model has the following beneficial effects:

1. the reference ground via holes are formed in the chip substrate and are arranged in a staggered manner with the reference ground bonding pads, so that the number of the reference ground via holes is effectively increased, the risk of crosstalk between high-speed signals is reduced, and the use stability of the integrated circuit board is further improved;

2. the reference ground via holes surround the periphery of the corresponding reference ground pad and are close to the corresponding reference ground via holes, so that the reference ground via holes, the high-speed signal pad and the high-speed signal via holes keep smaller spacing, and the risk of crosstalk between high-speed signals is further reduced;

3. through setting up the protection ring, improve the buffering shock attenuation effect of chip base plate to improve the protection effect to parts such as chip base plate, reduce the risk that the chip is basically damaged, and then improve the essential stability in use of integrated circuit.

Drawings

FIG. 1 is a schematic overall structure of embodiment 1;

fig. 2 is a schematic structural diagram of embodiment 2.

Reference numerals: 1. a chip substrate; 2. a high-speed signal pad; 3. a reference ground pad; 4. high-speed signal vias; 5. a reference ground via; 6. a protective ring; 7. a limit groove; 8. a limiting ring; 9. and the heat dissipation holes.

Detailed Description

The present utility model will be described in further detail with reference to the accompanying drawings.

Example 1

Referring to fig. 1, an integrated circuit substrate includes a chip substrate 1, a plurality of groups of high-speed signal pads 2 and a reference ground pad 3 are disposed on a surface of the chip substrate 1, and high-speed signal vias 4 are respectively disposed on each high-speed signal pad 2.

Referring to fig. 1, a plurality of groups of reference ground vias 5 are formed on a chip substrate 1, and each group of reference ground vias 5 is arranged offset from a corresponding reference ground pad 3, that is, the reference ground vias 5 are not formed on the reference ground pad 3. Meanwhile, the surface of the chip substrate 1 is provided with a reference ground copper sheet, and the reference ground copper sheet connects the reference ground bonding pad 3 and the reference ground via 5 in a staggered manner to form a whole.

The reference ground through holes 5 are formed in the chip substrate 1, and the reference ground through holes 5 and the reference ground bonding pads 3 are arranged in a staggered mode, so that the number of the reference ground through holes 5 is effectively increased, the risk of crosstalk between high-speed signals is reduced, and the use stability of the integrated circuit board is improved.

Referring to fig. 1, each group of high-speed signal pads 2 is provided with at least two rows, each row of high-speed signal pads 2 is arranged at equal intervals, and two adjacent rows of high-speed signal pads 2 are arranged in a staggered manner. In the present embodiment, only two sets of high-speed signal pads 2 are shown, and each set of high-speed signal pads 2 is in a two-row state.

Referring to fig. 1, a plurality of sets of reference ground pads 3 are arranged at intervals from a plurality of sets of high-speed signal pads 2, and each set of reference ground pads 3 is arranged in a row at equal intervals. In the present embodiment, only three sets of reference ground pads 3 are shown in state, and each set of reference ground pads 3 is two.

Referring to fig. 1, each group of reference ground vias 5 surrounds the periphery of the corresponding reference ground pad 3 and is close to the corresponding reference ground via 5, so that not only can the utilization efficiency of the chip substrate 1 be improved, but also the reference ground vias 5 can keep smaller distances from the high-speed signal pad 2 and the high-speed signal via 4, and the risk of crosstalk between high-speed signals is further reduced.

Example 2

Referring to fig. 2, this embodiment is different from embodiment 1 in that: the elastic protection ring 6 is arranged at the edge position of the bottom surface of the chip substrate 1 so as to improve the buffering and damping effects of the chip substrate 1, thereby improving the protection effects on the components such as the chip substrate 1, reducing the risk of basic damage of the chip and further improving the basic use stability of the integrated circuit.

Referring to fig. 2, a limit groove 7 is formed at the edge of the bottom surface of the chip substrate 1, a limit ring 8 is integrally formed on the protection ring 6, and the limit ring 8 is fixed in the limit groove 7. In the present embodiment, the guard ring 6 is made of an elastic material such as rubber or latex, and the guard ring 6 is integrally injection-molded with the chip substrate 1.

Referring to fig. 2, the cross section of the limiting ring 8 is in a T shape, and the circumferential inner wall of the limiting groove 7 is matched with the circumferential side wall of the limiting ring 8, so that the limiting ring 8 and the limiting groove 7 can form a clamping limit, and the connection stability of the limiting ring 8 and the chip substrate 1 is improved.

Referring to fig. 2, a plurality of heat dissipation holes 9 are formed in the guard ring 6, and the plurality of heat dissipation holes 9 are arranged at equal intervals along the circumferential direction of the guard ring 6, so as to improve the heat dissipation effect of the guard ring 6 and the chip substrate 1, reduce the risk of the chip being basically overheated, and improve the basic use stability of the integrated circuit.

The present utility model is not limited by the specific embodiments, and modifications can be made to the embodiments without creative contribution by those skilled in the art after reading the present specification, but are protected by patent laws within the scope of claims of the present utility model.

Claims

1. An integrated circuit substrate, includes chip substrate (1), the surface of chip substrate (1) is provided with multiunit high-speed signal pad (2) and reference ground pad (3), its characterized in that: each high-speed signal bonding pad (2) is provided with a high-speed signal via hole (4), each chip substrate (1) is provided with a plurality of groups of reference ground via holes (5), each group of reference ground via holes (5) are arranged in a staggered manner with the corresponding reference ground bonding pad (3), the surface of the chip substrate (1) is provided with a reference ground copper sheet, and the reference ground copper sheet connects the reference ground bonding pad (3) with the reference ground via holes (5) in a staggered manner to form a whole.

2. An integrated circuit substrate according to claim 1, wherein: each group of high-speed signal pads (2) is at least provided with two rows, each row of high-speed signal pads (2) are arranged at equal intervals, and two adjacent rows of high-speed signal pads (2) are arranged in a staggered mode.

3. An integrated circuit substrate according to claim 2, wherein: and a plurality of groups of the reference ground pads (3) and a plurality of groups of the high-speed signal pads (2) are arranged at intervals.

4. An integrated circuit substrate according to claim 3, wherein: each group of the reference ground pads (3) are arranged in a row at equal intervals, and each group of the reference ground vias (5) respectively surrounds the periphery of the corresponding reference ground pad (3) and is close to the corresponding reference ground via (5).

5. An integrated circuit substrate according to claim 1, wherein: an elastic protection ring (6) is arranged at the edge position of the bottom surface of the chip substrate (1).

6. The integrated circuit substrate of claim 5, wherein: the edge position of the bottom surface of the chip substrate (1) is provided with a limit groove (7), the protection ring (6) is connected with a limit ring (8) in an integrated manner, and the limit ring (8) is fixed in the limit groove (7).

7. The integrated circuit substrate of claim 6, wherein: the cross section of the limiting ring (8) is T-shaped, and the circumferential inner wall of the limiting groove (7) is matched with the circumferential side wall of the limiting ring (8), so that the limiting ring (8) can be clamped and limited with the limiting groove (7).

8. The integrated circuit substrate of claim 5, wherein: and the protection ring (6) is provided with a heat dissipation hole (9).

9. The integrated circuit substrate of claim 8, wherein: the heat dissipation holes (9) are arranged in a plurality, and the heat dissipation holes (9) are arranged at equal intervals along the circumferential direction of the protection ring (6).