CN112701099A - Packaging structure and packaging method - Google Patents
Packaging structure and packaging method Download PDFInfo
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- CN112701099A CN112701099A CN201911004682.2A CN201911004682A CN112701099A CN 112701099 A CN112701099 A CN 112701099A CN 201911004682 A CN201911004682 A CN 201911004682A CN 112701099 A CN112701099 A CN 112701099A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims abstract description 8
- 229910000679 solder Inorganic materials 0.000 claims abstract description 121
- 239000000758 substrate Substances 0.000 claims abstract description 99
- 239000011295 pitch Substances 0.000 claims description 155
- 239000011159 matrix material Substances 0.000 claims description 3
- 230000010354 integration Effects 0.000 abstract description 12
- 230000017525 heat dissipation Effects 0.000 abstract description 11
- 238000010586 diagram Methods 0.000 description 7
- 238000012536 packaging technology Methods 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- Microelectronics & Electronic Packaging (AREA)
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- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The embodiment of the invention relates to the field of electronics, and discloses a packaging structure and a packaging method. The invention comprises a substrate and a solder ball arranged on the substrate; the substrate comprises a first area and a second area, wherein the solder balls are distributed in the first area; the solder balls are arranged in the first area at a first interval and arranged in the second area at a second interval, wherein the first interval is larger than the second interval. The packaging structure provided by the embodiment of the invention has higher integration level while keeping the signal integrity of the chip, and can improve the heat dissipation capability of a PCB (printed circuit board) level.
Description
Technical Field
The embodiment of the invention relates to the field of electronics, in particular to a packaging structure and a packaging method.
Background
Among chip packaging technologies, BGA (Ball Grid Array, Ball Grid Array or solder Ball Array) packaging technology is rapidly developed and becomes one of the mainstream packaging technologies. It is a high density surface mount package technology, where the pins of the signal pins are all spherical and arranged in a grid-like pattern at the bottom of the package, where there is an important parameter in the package-the solder ball pitch. The design of the solder ball pitch needs to consider the number of pins of the package size, the type of the pins and other factors.
The inventor finds that at least the following problems exist in the prior art: how to design the solder Ball pitch to meet the requirements of different situations is an important problem in the BGA (Ball Grid Array, Ball Grid Array or solder Ball Array) packaging technology.
Disclosure of Invention
The embodiment of the invention aims to provide a packaging structure, which enables a chip to have higher integration level while keeping signal integrity and can improve the heat dissipation capability of a PCB (printed circuit board) level. In order to solve the above technical problem, an embodiment of the present invention provides a package structure, including a substrate, solder balls disposed on the substrate; the substrate comprises a first area and a second area, wherein solder balls are distributed in the first area; the solder balls are arranged in the first area at a first interval and arranged in the second area at a second interval, wherein the first interval is larger than the second interval.
Embodiments of the present invention also provide a packaging method, including providing a substrate and solder balls disposed on the substrate; arranging a first area and a second area on a substrate, wherein solder balls are arranged in the first area and the second area; the solder balls are arranged in the first area at a first interval and arranged in the second area at a second interval, wherein the first interval is larger than the second interval.
Compared with the prior art, the embodiment of the invention uses the solder ball spaces with different sizes in a mixed manner in the packaging process, distributes the solder balls corresponding to different signal pins in different arrangement areas, packages the signal pins needing to keep signal integrity by using the larger first space, and can optimize three parameters of loss, crosstalk and impedance by using the larger first space so as to realize the purpose of keeping signal integrity; the signal pins with low signal integrity requirement are packaged by using a smaller second spacing, so that the integral integration level of the chip is better, the heat dissipation problem on the chip is improved, and the board level has good heat dissipation capability.
In addition, the first region is disposed around the second region, or the second region is disposed around the first region. The first area and the second area can be flexibly and freely distributed on the substrate, the applicability is wider, and the design freedom of arrangement of the first solder balls and the second solder balls is improved.
In addition, the first region comprises K sub-regions, and the K sub-regions are not adjacently embedded and distributed in the second region, wherein K is an integer larger than 0. The first area and the second area can be distributed on the substrate in a mixed mode, the first solder balls and the second solder balls are distributed more freely, the applicability is wider, and the design freedom degree of the arrangement of the first solder balls and the second solder balls is improved.
In addition, the spacing distance at the junction of the first area and the second area is a first spacing, or the spacing distance at the junction of the first area and the second area is a second spacing. For the distance between the junctions of the first area and the second area, the larger first spacing is used for arrangement, so that the larger first spacing can optimize three parameters of loss, crosstalk and impedance, and the signal integrity of the solder balls at the junctions is improved; or by using a smaller second pitch arrangement, the chip integration is made higher.
In addition, the solder balls are arranged in a row-column matrix manner, the first spacing is the row spacing and/or the column spacing of the solder balls arranged in the first area, and the second spacing is the row spacing and/or the column spacing of the solder balls arranged in the second area. In the process of arranging the solder balls in a matrix form, the first spacing can be the line spacing between each line of solder balls in the first area, or the column spacing between each line of solder balls, or the first spacing is simultaneously used for arranging in a row-column spacing, and the second spacing can be the line spacing between each line of solder balls in the second area, or the column spacing between each line of solder balls, or the second spacing is simultaneously used for arranging in a row-column spacing, so that the arrangement mode of the solder balls is more flexible and changeable, and the solder balls are suitable for various situations.
In addition, the first pitch includes M kinds of first sub pitches, where M is an integer greater than 0; in the first region, every two adjacent solder balls are arranged on the substrate at one of the M first sub pitches. The first interval is not only a fixed numerical value, but also comprises a plurality of sub intervals adapting to various conditions, and the sub intervals can be arranged on the substrate at various different intervals, so that the solder balls are suitable for electric connection of various pins, and the design requirements of diversified parameters of the pins are met.
In addition, the second pitch comprises N second sub-pitches, wherein N is an integer greater than 0; in the second region, every two adjacent solder balls are arranged on the substrate at one of the N second sub pitches. The second pitch is not only a fixed value, but also comprises a plurality of sub pitches adapted to various conditions, and the sub pitches can be arranged on the substrate at various different sub pitches, so that the solder balls are suitable for electric connection of various pins, and the design requirement of diversified parameters of the pins is met.
In addition, pins connected with the solder balls arranged in the first space in the first area are high-speed Serdes pins. After the solder balls are arranged in the first area at the larger first pitch, the solder balls are connected with the high-speed Serdes pins, and the signal integrity of the high-speed Serdes pins is ensured.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a schematic diagram of a package structure according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a package structure according to a second embodiment of the present invention;
FIG. 3 is a schematic diagram of a package structure according to a third embodiment of the present invention;
FIG. 4 is a diagram illustrating a package structure according to a fourth embodiment of the present invention;
fig. 5 is a schematic diagram of a package structure according to a fifth embodiment of the present invention;
FIG. 6 is a schematic diagram of a package structure according to a sixth embodiment of the present invention;
fig. 7 is a schematic diagram of a package structure according to a seventh embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that numerous technical details are set forth in order to provide a better understanding of the present application in various embodiments of the present invention. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present invention, and the embodiments may be mutually incorporated and referred to without contradiction.
A first embodiment of the present invention relates to a package structure, which includes a substrate 1 and solder balls 2, as shown in fig. 1. The substrate comprises a first area 3 in which the solder balls 2 are arranged and a second area 4 in which the solder balls 2 are arranged, the solder balls 2 are arranged in the first area 3 at a first distance D1 and in the second area 4 at a second distance D2, wherein the first distance D1 is larger than the second distance D2.
According to the embodiment of the invention, the signal pins are divided into high-speed signal pins and other signal pins according to the function of the chip functional module, the high-speed signal pins comprise pins in a processing chip and a switching chip, the high-speed signal pins have higher requirements on the pin spacing, and the deterioration of three SI parameters including impedance, loss and crosstalk can be caused by the excessively low pin spacing, so that the signal integrity of the high-speed signal pins is influenced; other signal pins comprise pins in a low-speed chip and a control chip, the requirements of the other signal pins on the pin spacing are not high, and the smaller pin spacing can be used for improving the integral integration level of the chip. And calculating the number of rows or columns required by the high-speed signal pins and other signal pins according to the counted number of the high-speed signal pins and other signal pins. And distributing respective arrangement areas of the high-speed signal pins and other signal pins on the substrate according to the number of rows or columns required by the high-speed signal pins and other signal pins, wherein the high-speed signal pins are in the first area 3, and the other signal pins are in the second area 4. Solder balls 2 are solder-arranged on a first region 3 of the substrate 1 assigned to high-speed signal pins at a first pitch D1, and solder-arranged on a second region 4 of the substrate 1 assigned to other signal pins at a second pitch D2, wherein the first pitch D1 is greater than the second pitch D2.
In this embodiment, the solder balls 2 are arranged on the substrate 1 at the first distance D1 that is larger than the second distance D2, the larger first distance D1 can optimize three parameters of loss, crosstalk and impedance, and maintain the signal integrity of high-speed signals, and the solder balls 2 are arranged on the substrate 1 at the second distance D2 that is smaller than the first distance D1, so that the chip has high integration level as a whole, the package size of the chip is reduced, the signal integrity is ensured, and at the same time, the package size is reduced and the layout distance is increased, and the heat dissipation at the chip PCB level is improved.
A second embodiment of the present invention relates to a package structure, and is substantially the same as the first embodiment, and mainly differs therefrom in that: in the second embodiment of the present invention, the first region 3 is disposed around the second region 4.
As shown in fig. 2, the package structure in this embodiment includes a substrate 1 and solder balls 2. The solder balls 2 are arranged in the first region 3 at a first pitch D1 and arranged in the second region 4 at a second pitch D2, wherein the first pitch D1 is greater than the second pitch D2. The first regions 3 and the second regions 4 are arranged at intervals of a first distance D1 at the boundary, the first regions 3 are located in the outer circle region on the substrate 1, and the second regions 4 are located in the inner circle region on the substrate 1. Furthermore, it can be understood by those skilled in the art that the embodiment is an IC package with a first pitch of 1.0mmmm, a second pitch of 0.6mm, and a package substrate of 16 rows by 16 columns, and the embodiment does not limit the specific values of the first pitch D1 and the second pitch D2 and the number of rows and columns of the package substrate.
According to the number of rows or columns needed by the high-speed signal pins and other signal pins, distributing the respective arrangement areas of the high-speed signal pins and other signal pins on the substrate, namely the high-speed signal pins are located in a first area 3 of an outer circle on the substrate 1, and the other signal pins are located in a second area 4 of an inner circle on the substrate 1. Solder balls 2 are solder-arranged in the first area 3 of the substrate 1 at a first pitch D1, and solder-arranged in the second area 4 of the substrate 1 at a second pitch D2, wherein the first pitch 1.0mm is greater than the second pitch 0.6 mm.
In the IC package with 16 rows by 16 columns of rows and columns of the package substrate, the solder balls 2 corresponding to the high-speed signal pins are distributed from the outermost row (the outermost column) to the third row (the third column) as the first region 3, the solder ball pitch with the first pitch D1 of 1.0mm is adopted in the 3 rows by 3 columns with the inner circle as the outer circle of the first region 3 of the second region 4, the solder ball pitch with the second pitch D2 of 0.6mm is adopted in all the inner second regions 4, the boundary between the first region 3 and the second region 4 is arranged between the third column and the fourth column, and the solder ball pitch with the first pitch D1 of 1.0mm is also adopted in the boundary for arrangement, so as to ensure the signal integrity of the high-speed signal pins at the boundary.
In this embodiment, the solder balls 2 are arranged in the first region 3 of the outer ring of the substrate 1 at the first distance D1 larger than the second distance D2, and arranged in the second region 4 of the inner ring of the substrate 1 at the second distance D2 smaller than the first distance D1, wherein the first distance D1 is also arranged at the boundary between the first region 3 and the second region 4, so that the signal integrity of high-speed signals is maintained, the chip has high integration level as a whole, the package size of the chip is reduced, and the chip has good heat dissipation capability.
A third embodiment of the present invention relates to a package structure, and is substantially the same as the second embodiment, and mainly differs therefrom in that: the second region 4 is circumferentially arranged around the first region 3.
As shown in fig. 3, the package structure in this embodiment includes a substrate 1 and solder balls 2. The solder balls 2 are arranged in the first region 3 at a first pitch D1 and arranged in the second region 4 at a second pitch D2, wherein the first pitch D1 is greater than the second pitch D2. The first regions 3 and the second regions 4 are arranged at the boundary with a first distance D1. The first region 3 is located in the inner circumferential region on the substrate 1, and the second region 4 is located in the outer circumferential region on the substrate 1. Furthermore, it can be understood by those skilled in the art that the embodiment is an IC package with the first pitch D1 being 1.0mm, the second pitch D2 being 0.6mm, and the package substrate being 16 rows by 16 columns, and the specific values of the first pitch D1 and the second pitch D2 and the number of rows and columns of the package substrate are not limited in this embodiment.
And calculating the number of rows or columns required by the high-speed signal pins and other signal pins according to the counted number of the high-speed signal pins and other signal pins. According to the number of rows or columns needed by the high-speed signal pins and other signal pins, distributing respective arrangement areas of the high-speed signal pins and other signal pins on the substrate, namely, the high-speed signal pins are located in a first area 3 of an inner circle on the substrate 1, and the other signal pins are located in a second area 4 of an outer circle on the substrate 1. Solder balls 2 are solder-arranged in the first area 3 of the substrate 1 at a first pitch D1, and solder-arranged in the second area 4 of the substrate 1 at a second pitch D2, wherein the first pitch 1.0mm is greater than the second pitch 0.6 mm.
In an IC package with 16 rows by 16 columns of packaging substrate rows, the whole IC package is designed according to the solder ball pitch of 0.6mm, 5 rows by 5 columns of an inner circle first area are distributed with first areas 3 corresponding to high-speed signal pins, and the rows and columns of the rest outer circle second areas 4 are distributed with solder balls 2 corresponding to other signal pins; the 5 rows and 5 columns of the inner circle first area 3 adopt a solder ball pitch with a first pitch D1 of 1.0mm, the outer circle second area 4 completely adopts a solder ball pitch with a second pitch D2 of 0.6mm, namely, the distance between every two solder balls 2 in the first area 3 is 1.0mm, the distance between every two solder balls 2 in the second area 4 is 0.6mm, and the junction of the first area 3 and the second area 4 is also arranged by adopting a solder ball pitch with a first pitch D1 of 1.0mm, so as to ensure the signal integrity of high-speed signal pins at the junction.
In this embodiment, the solder balls 2 are arranged in the inner first region 3 of the substrate 1 at the first distance D1 larger than the second distance D2, wherein the first distance D1 is also arranged at the boundary between the first region 3 and the second region 4, so as to maintain the signal integrity of the high-speed signal, and the solder balls 2 are arranged in the outer second region 4 of the substrate 1 at the second distance D2 smaller than the first distance D1, so as to make the chip have high integration level and reduce the package size of the chip, and at the same time, the solder balls 2 are arranged at the larger first distance D1, so as to make the chip have good heat dissipation capability.
A fourth embodiment of the present invention relates to a package structure, and is substantially the same as the second embodiment, and mainly differs therefrom in that: in the fourth embodiment of the present invention, the first region 3 includes K sub-regions, and the K sub-regions are not adjacently embedded and distributed in the second region 4, where K is an integer greater than 0.
As shown in fig. 4, the package structure in this embodiment includes a substrate 1 and solder balls 2. The solder balls 2 are arranged in the first region 3 at a first pitch D1 and arranged in the second region 4 at a second pitch D2, wherein the first pitch D1 is greater than the second pitch D2. Furthermore, it can be understood by those skilled in the art that the embodiment is an IC package in which the first pitch D1 is 1.0mm, the second pitch D2 is 0.6mm, and the package substrate is 16 rows by 16 columns, and the first region 3 includes 2 sub-regions, and the embodiment does not limit the specific values of the first pitch D1 and the second pitch D2, the number of rows and columns of the package substrate, and the number of sub-regions of the first region 3.
And calculating the number of rows or columns required by the high-speed signal pins and other signal pins according to the counted number of the high-speed signal pins and other signal pins. And distributing respective arrangement areas of the high-speed signal pins and other signal pins on the substrate according to the number of rows or columns required by the high-speed signal pins and other signal pins, wherein the first areas 3 for distributing the high-speed signal pins are positioned at the upper left part and the lower right part of the substrate 1.
In an IC package with 16 rows by 16 columns of packaging substrate rows, the whole IC package is designed according to a solder ball pitch with a second pitch D2 of 0.6mm, 5 rows by 5 columns of the lower right part of the substrate 1 and 3 rows by 3 columns of the upper left part of the substrate are distributed with first areas 3 corresponding to high-speed signal pins, and the other rows and columns are distributed with second areas 4 corresponding to other signal pins; the distance between every two solder balls 2 in the first area 3 is 1.0mm, the distance between every two solder balls 2 in the second area is 0.6mm, and the junction between the first area 3 and the second area 4 is also arranged by adopting the solder ball pitch with the first pitch D1 of 1.0mm, so as to ensure the signal integrity of high-speed signal pins at the junction.
In this embodiment, the first region 3 and the second region 4 are arranged on the substrate in a mixed manner, wherein the boundary between the first region 3 and the second region 4 is also arranged at the first distance D1, so that the signal integrity of the high-speed signal is maintained, the chip has a high integration level as a whole, the package size of the chip is reduced, and the solder balls 2 are arranged in the first region at the larger first distance D1, so that the chip has a good heat dissipation capability.
A fifth embodiment of the present invention relates to a package structure, and is substantially the same as the fourth embodiment, and mainly differs therefrom in that: in the fifth embodiment of the present invention, when the solder balls 2 are arranged in the first region 3, the solder ball row pitch is arranged at the first pitch D1.
As shown in fig. 5, the package structure in this embodiment includes a substrate 1 and solder balls 2. The solder balls 2 are arranged in the first region 3 at a first pitch D1 and arranged in the second region 4 at a second pitch D2, wherein the first pitch D1 is greater than the second pitch D2. The first regions 3 and the second regions 4 are arranged at the boundary with a first distance D1. When the solder balls 2 are arranged in the first area 3, the first spacing D1 is used as the solder ball column spacing, and the line spacing between the solder balls 2 is still the second spacing D2; the column pitch and the row pitch of the solder balls between the solder balls 2 in the second region 4 are both the second pitch D2. Furthermore, it can be understood by those skilled in the art that the embodiment is an IC package with the first pitch D1 being 1.0mm, the second pitch D2 being 0.6mm, and the package substrate being 16 rows by 16 columns, and the specific values of the first pitch D1 and the second pitch D2 and the number of rows and columns of the package substrate are not limited in this embodiment.
And calculating the number of rows or columns required by the high-speed signal pins and other signal pins according to the counted number of the high-speed signal pins and other signal pins. And distributing respective arrangement areas of the high-speed signal pins and other signal pins on the substrate according to the number of rows or columns required by the high-speed signal pins and other signal pins. In this embodiment, high-number signal pins are allocated to the middle portions of the left and right sides of the substrate 1, the high-speed signal pins are located in the first region 3, and the other signal pins are located in the second region 4. Solder balls 2 are solder-arranged in the first region 3 at a first pitch D1 and solder-arranged in the second region 4 at a second pitch D2, wherein the first pitch is 1.0mm larger than the second pitch, which is 0.6 mm.
In an IC package with 16 rows by 16 columns of rows and columns of a package substrate, a first pitch of 1.0mm is used as a column solder ball pitch for designing from a 1 st column to a 3 rd column and from a 4 th row to an 8 th row from a 14 th column to a 16 th column from left to right, and the first pitch is distributed to high-speed signals, and the row solder ball pitch on the whole substrate 1 is kept unchanged and is 0.6 mm.
In this embodiment, when the solder balls 2 are arranged on the substrate 1 in a mixed manner, the column solder ball pitch between the solder balls 2 in the first region 3 is the larger first pitch D1, and the row solder ball pitch is the second pitch D2, so that the signal integrity of the high-speed signal is maintained, the integration of the whole chip is further improved, the package size of the chip is reduced, and meanwhile, the solder balls 2 are arranged at the column solder ball pitch with the larger first pitch D1, so that the chip has good heat dissipation capability.
A sixth embodiment of the present invention relates to a package structure, and is substantially the same as the second embodiment, and mainly differs therefrom in that: in the sixth embodiment of the present invention, the second pitch D2 includes 2 second sub pitches D21, D22, and the solder balls 2 are simultaneously arranged in the second regions 4 on the substrate 1 at 2 different second sub pitches D21, D22.
As shown in fig. 6, the package structure in this embodiment includes a substrate 1 and solder balls 2. The solder balls 2 are in different arrangement regions on the substrate 1, the solder balls 2 are arranged in the first region 3 at a first pitch D1, and are respectively arranged in the second region 4 at 2 second sub-pitches D21 and D22, wherein the first pitch D1 is greater than the 2 second sub-pitches D21 and D22.
And calculating the number of rows or columns required by the high-speed signal pins and other signal pins according to the counted number of the high-speed signal pins and other signal pins. The respective arrangement areas of the high-speed signal pins and the other signal pins on the substrate are allocated according to the number of rows or columns needed by the high-speed signal pins and the other signal pins, in this embodiment, the allocated high-speed signal pins are located in the right half area, i.e., the first area 3, on the substrate 1, and the other signal pins are located in the left half area, i.e., the second area 4, on the substrate 1. Solder balls 2 are solder-arranged in the first region 3 of the substrate 1 at a first pitch D1, and solder-arranged in the second region 4 of the substrate 1 at 2 second sub-pitches D21 and D22, respectively, wherein the first pitch D1 is greater than the 2 second sub-pitches D21 and D22.
In an IC package with 16 rows by 16 columns of rows and columns of a package substrate, 8 columns of the right half part of the substrate 1 are distributed to a first area 3 corresponding to high-speed signal pins, and 8 columns of the left half part are distributed to a second area 4 corresponding to other signal pins; the right half 8 column adopts a solder ball pitch with a first pitch D1 of 1.0mm, the 1 st row to the 10 th row from top to bottom in the left half 8 column are arranged with a larger sub-pitch D21 in the second sub-pitch, and the rest of the substrate 1 is arranged with a second smaller sub-pitch D22 in the second sub-pitch.
In this embodiment, the solder balls 2 are arranged in the first region 3 of the substrate 1 at the first pitch D1 larger than the second pitch D2, and the solder balls 2 are arranged in the second region 4 of the substrate 1 at the second sub-pitches D21 and D22 smaller than the first pitch, so that the chip has high integration level as a whole, the package size of the chip is reduced, and the solder balls 2 are arranged at the larger first pitch, so that the chip has good heat dissipation capability.
A seventh embodiment of the present invention relates to a package structure, and is substantially the same as the second embodiment, and mainly differs therefrom in that: in the seventh embodiment of the present invention, the first pitch D1 includes 2 kinds of first sub pitches D11, D12, and the solder balls 2 are arranged on the substrate 1 at 2 different kinds of first sub pitches D11, D12 at the same time.
As shown in fig. 7, the package structure in this embodiment includes a substrate 1 and solder balls 2. The solder balls 2 are arranged in the first region 3 at first sub-pitches D11 and D12, and arranged in the second region 4 at a second pitch D2, wherein 2 kinds of the first sub-pitches are larger than the second pitch. The first region 3 is in the right half region on the substrate 1, and the second region 4 is in the left half region on the substrate 1.
And calculating the number of rows or columns required by the high-speed signal pins and other signal pins according to the counted number of the high-speed signal pins and other signal pins. The respective arrangement areas of the high-speed signal pins and the other signal pins on the substrate are allocated according to the number of rows or columns needed by the high-speed signal pins and the other signal pins, in this embodiment, the allocated high-speed signal pins are located in the right half area, i.e., the first area 3, on the substrate 1, and the other signal pins are located in the left half area, i.e., the second area 4, on the substrate 1. Solder balls 2 are soldered and arranged in the right half area of the substrate 1 at 2 first sub-pitches D11 and D12, and are soldered and arranged in the left half area of the substrate 1 at a second pitch D2, wherein the 2 first sub-pitches D11 and D12 are larger than the second pitch D2.
In an IC package with 16 rows by 16 columns of rows and columns of a package substrate, 8 columns of the right half part of the substrate 1 are distributed to a first area 3 corresponding to high-speed signal pins, and 8 columns of the left half part are distributed to a second area 4 corresponding to other signal pins; in the right half part 8 column, the 1 st row to the 3 rd row counted from top to bottom are arranged by using the larger sub-pitch D11 in the first sub-pitch, the 4 th row to the 9 th row are arranged by using the second smaller sub-pitch D12 in the first sub-pitch, and the left half part 8 column is arranged by using the second pitch D2 to arrange the solder balls 2.
In this embodiment, the solder balls 2 are arranged in the first region 3 of the substrate 1 at 2 first sub-pitches D11 and D12 larger than the second pitch D2, so that the signal integrity of the high-speed signal is maintained, and the solder balls 2 are arranged in the second region 4 of the substrate 1 at the second pitch D2 smaller than the first pitch D1, so that the chip has high integration level as a whole, the package size of the chip is reduced, and the solder balls 2 are arranged at the larger first pitch, so that the chip has good heat dissipation capability.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.
Claims (10)
1. The packaging structure is characterized by comprising a substrate and a solder ball arranged on the substrate;
the substrate comprises a first area and a second area, wherein the solder balls are distributed in the first area;
the solder balls are arranged in the first area at a first interval and arranged in the second area at a second interval, wherein the first interval is larger than the second interval.
2. The package structure of claim 1, wherein the first region is disposed around the second region, or wherein the second region is disposed around the first region.
3. The package structure according to claim 1, wherein the first region comprises K sub-regions, the K sub-regions are non-adjacently embedded and distributed in the second region, and K is an integer greater than 0.
4. The package structure according to any one of claims 1 to 3, wherein a boundary between the first region and the second region is separated by the first pitch, or wherein a boundary between the first region and the second region is separated by the second pitch.
5. The package structure according to claim 4, wherein the solder balls are arranged in a matrix of rows and columns, the first pitch is a row pitch and/or a column pitch of the solder balls arranged in the first region, and the second pitch is a row pitch and/or a column pitch of the solder balls arranged in the second region.
6. The package structure of claim 5, wherein the first pitch comprises M first sub-pitches, wherein M is an integer greater than 0;
in the first region, every two adjacent solder balls are arranged on the substrate at one of the M first sub pitches.
7. The package structure according to claim 5, wherein the second pitch comprises N second sub-pitches, where N is an integer greater than 0;
in the second region, every two adjacent solder balls are arranged on the substrate at one of the N second sub pitches.
8. The package structure of claim 1, wherein the solder balls arranged in the first area at the first pitch are high speed Serdes pins.
9. A method of packaging, comprising: providing a substrate;
solder balls arranged at a first interval are arranged in a first area of the substrate;
solder balls arranged at a second interval are arranged in a second area of the substrate;
wherein the first pitch is greater than the second pitch.
10. The method of claim 9, wherein the first region is disposed circumferentially around the second region, or wherein the second region is disposed circumferentially around the first region.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911004682.2A CN112701099A (en) | 2019-10-22 | 2019-10-22 | Packaging structure and packaging method |
| PCT/CN2020/121524 WO2021078071A1 (en) | 2019-10-22 | 2020-10-16 | Encapsulation structure and encapsulation method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911004682.2A CN112701099A (en) | 2019-10-22 | 2019-10-22 | Packaging structure and packaging method |
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| CN112701099A true CN112701099A (en) | 2021-04-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201911004682.2A Pending CN112701099A (en) | 2019-10-22 | 2019-10-22 | Packaging structure and packaging method |
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| Country | Link |
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| CN (1) | CN112701099A (en) |
| WO (1) | WO2021078071A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114927491A (en) * | 2022-05-17 | 2022-08-19 | 超聚变数字技术有限公司 | Electronic device, circuit board and chip |
| WO2023217277A1 (en) * | 2022-05-12 | 2023-11-16 | 哲库科技(上海)有限公司 | Package structure, processor chip, pop package assembly and electronic device |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3846611B2 (en) * | 1998-09-25 | 2006-11-15 | ソニー株式会社 | Mounting semiconductor component, mounting structure and mounting method |
| JP3645136B2 (en) * | 1999-06-22 | 2005-05-11 | 三菱電機株式会社 | Electronic circuit package and mounting board |
| JP2006202991A (en) * | 2005-01-20 | 2006-08-03 | Sony Corp | Circuit board and its manufacturing method, and semiconductor package and its manufacturing method |
| US7652361B1 (en) * | 2006-03-03 | 2010-01-26 | Amkor Technology, Inc. | Land patterns for a semiconductor stacking structure and method therefor |
| JP5143140B2 (en) * | 2007-11-15 | 2013-02-13 | パナソニック株式会社 | Semiconductor light emitting device |
| JP2010093109A (en) * | 2008-10-09 | 2010-04-22 | Renesas Technology Corp | Semiconductor device, method of manufacturing the same, and method of manufacturing semiconductor module |
| JP2010123602A (en) * | 2008-11-17 | 2010-06-03 | Nec Electronics Corp | Semiconductor device and method of manufacturing the same |
| DE102017218273B4 (en) * | 2017-10-12 | 2022-05-12 | Vitesco Technologies GmbH | semiconductor assembly |
| US10825774B2 (en) * | 2018-08-01 | 2020-11-03 | Samsung Electronics Co., Ltd. | Semiconductor package |
| JP2020061406A (en) * | 2018-10-05 | 2020-04-16 | 株式会社村田製作所 | Semiconductor device |
-
2019
- 2019-10-22 CN CN201911004682.2A patent/CN112701099A/en active Pending
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023217277A1 (en) * | 2022-05-12 | 2023-11-16 | 哲库科技(上海)有限公司 | Package structure, processor chip, pop package assembly and electronic device |
| CN114927491A (en) * | 2022-05-17 | 2022-08-19 | 超聚变数字技术有限公司 | Electronic device, circuit board and chip |
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| Publication number | Publication date |
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| WO2021078071A1 (en) | 2021-04-29 |
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